Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Use pcrel access and avoid GOT entries. Restructure a little to be more 

efficient.
This commit is contained in:
matt 2013-07-18 12:20:41 +00:00
parent 547d5de4df
commit 0bcd9d746a
1 changed files with 23 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
lib/libc/arch/powerpc/string/bzero.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bzero.S,v 1.11 2011/01/29 02:21:20 matt Exp $ */ /* $NetBSD: bzero.S,v 1.12 2013/07/18 12:20:41 matt Exp $ */
/*- /*-
* Copyright (C) 2001 Martin J. Laubach <mjl@NetBSD.org> * Copyright (C) 2001 Martin J. Laubach <mjl@NetBSD.org>
@ -32,7 +32,7 @@
#if defined(LIBC_SCCS) && !defined(lint) #if defined(LIBC_SCCS) && !defined(lint)
__RCSID("$NetBSD: bzero.S,v 1.11 2011/01/29 02:21:20 matt Exp $") __RCSID("$NetBSD: bzero.S,v 1.12 2013/07/18 12:20:41 matt Exp $")
#endif /* LIBC_SCCS && !lint */ #endif /* LIBC_SCCS && !lint */
#ifdef _KERNEL #ifdef _KERNEL
@ -76,17 +76,21 @@ cb_memset:
/* First find out cache line size */ /* First find out cache line size */
mflr %r9 mflr %r9
#ifdef PIC #ifdef PIC
PIC_GOTSETUP(%r10) bcl 20,31,1f
1: mflr %r5
mtlr %r9 mtlr %r9
lwz %r5,cache_info@got(%r10) addis %r5,%r5,cache_info+4-1b@ha
lwzu %r9,cache_info+4-1b@l(%r5)
#else #else
lis %r5,cache_info@h lis %r5,cache_info+4@ha
ori %r5,%r5,cache_info@l lwzu %r9,cache_info+4@l(%r5)
#endif #endif
lwz %r6, 4(%r5) lwz %r10,cache_sh-(cache_info+4)(%r5)
cmpwi %r6, -1 cmpwi %r9, -1
bne+ cb_cacheline_known bne+ cb_cacheline_known
addi %r5, %r5, -4 /* point r5 @ beginning of cache_info */
/*----------------------------------------------------------------------*/ /*----------------------------------------------------------------------*/
#define CTL_MACHDEP 7 #define CTL_MACHDEP 7
#define CPU_CACHELINE 1 #define CPU_CACHELINE 1
@ -172,33 +176,25 @@ cb_memset:
cntlzw %r6, %r9 /* compute shift value */ cntlzw %r6, %r9 /* compute shift value */
li %r5, 31 li %r5, 31
subf %r5, %r6, %r5 subf %r10, %r6, %r5
#ifdef PIC #ifdef PIC
mflr %r9 mflr %r9
PIC_GOTSETUP(%r10) bcl 20,31,1f
1: mflr %r5
mtlr %r9 mtlr %r9
lwz %r6, cache_sh@got(%r10)
stw %r5, 0(%r6) addis %r5, %r5, cache_info+4-1b@ha
lwzu %r9, cache_info+4-1b@l(%r5)
#else #else
lis %r6, cache_sh@ha lis %r5, cache_info+4@ha
stw %r5, cache_sh@l(%r6) lwzu %r9, cache_info+4@l(%r5)
#endif #endif
stw %r10, cache_sh-(cache_info+4)(%r5)
/*----------------------------------------------------------------------*/ /*----------------------------------------------------------------------*/
/* Okay, we know the cache line size (%r9) and shift value (%r10) */ /* Okay, we know the cache line size (%r9) and shift value (%r10) */
cb_cacheline_known: cb_cacheline_known:
#ifdef PIC
lwz %r5, cache_info@got(%r10)
lwz %r9, 4(%r5)
lwz %r5, cache_sh@got(%r10)
lwz %r10, 0(%r5)
#else
lis %r9, cache_info+4@ha
lwz %r9, cache_info+4@l(%r9)
lis %r10, cache_sh@ha
lwz %r10, cache_sh@l(%r10)
#endif
#else /* _KERNEL */ #else /* _KERNEL */
#ifdef MULTIPROCESSOR #ifdef MULTIPROCESSOR
mfsprg %r10, 0 /* Get cpu_info pointer */ mfsprg %r10, 0 /* Get cpu_info pointer */
@ -371,6 +367,7 @@ END(memset)
/*----------------------------------------------------------------------*/ /*----------------------------------------------------------------------*/
#ifndef _KERNEL #ifndef _KERNEL
.data .data
.p2align 2
cache_info: .long -1, -1, -1, -1 cache_info: .long -1, -1, -1, -1
cache_sh: .long 0 cache_sh: .long 0