implement pmap_wired_count(). use more macros for determining MMU type.
This commit is contained in:
chs
parent
bfbf7ea9b1
commit
0b7dee4b92
@ -1,4 +1,4 @@
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/* $NetBSD: cpuconf.h,v 1.2 2003/08/07 16:29:38 agc Exp $ */
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/* $NetBSD: cpuconf.h,v 1.3 2005/01/16 23:19:52 chs Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -128,10 +128,10 @@ extern int cputyp;
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#define CPU_ISSUN4U (0)
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/*
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* Step 3: Sun4M and Sun4D systems have an SRMMU. Define some
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* short-hand for this.
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* Step 3: Define some short-hand for the different MMUs.
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*/
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#define CPU_HAS_SRMMU (CPU_ISSUN4M || CPU_ISSUN4D)
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#define CPU_HAS_SUNMMU (CPU_ISSUN4 || CPU_ISSUN4C)
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#endif /* _KERNEL || _STANDALONE */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.73 2004/04/10 20:00:29 pk Exp $ */
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/* $NetBSD: pmap.h,v 1.74 2005/01/16 23:19:52 chs Exp $ */
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/*
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* Copyright (c) 1996
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@ -171,6 +171,7 @@ struct regmap {
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};
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struct segmap {
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uint64_t sg_wiremap; /* per-page wire bits (4m) */
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int *sg_pte; /* points to NPTESG PTEs */
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pmeg_t sg_pmeg; /* the MMU segment number (4c) */
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u_char sg_npte; /* number of valid PTEs in sg_pte
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@ -243,6 +244,7 @@ int pmap_dumpmmu(int (*)(dev_t, daddr_t, caddr_t, size_t), daddr_t);
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#define pmap_kernel() (&kernel_pmap_store)
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#define pmap_resident_count(pm) ((pm)->pm_stats.resident_count)
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#define pmap_wired_count(pm) ((pm)->pm_stats.wired_count)
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#define PMAP_PREFER(fo, ap) pmap_prefer((fo), (ap))
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.295 2004/05/01 08:20:11 pk Exp $ */
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/* $NetBSD: pmap.c,v 1.296 2005/01/16 23:19:52 chs Exp $ */
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/*
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* Copyright (c) 1996
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@ -56,7 +56,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.295 2004/05/01 08:20:11 pk Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.296 2005/01/16 23:19:52 chs Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -128,7 +128,6 @@ struct pmap_stats {
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int ps_unlink_pvfirst; /* # of pv_unlinks on head */
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int ps_unlink_pvsearch; /* # of pv_unlink searches */
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int ps_changeprots; /* # of calls to changeprot */
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int ps_useless_changeprots; /* # of changeprots for wiring */
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int ps_enter_firstpv; /* pv heads entered */
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int ps_enter_secondpv; /* pv nonheads entered */
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int ps_useless_changewire; /* useless wiring changes */
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@ -979,14 +978,14 @@ pgt_page_free(struct pool *pp, void *v)
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#define CTX_USABLE(pm,rp) ((pm)->pm_ctx != NULL )
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#endif
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#define GAP_WIDEN(pm,vr) do if (CPU_ISSUN4 || CPU_ISSUN4C) { \
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#define GAP_WIDEN(pm,vr) do if (CPU_HAS_SUNMMU) { \
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if (vr + 1 == pm->pm_gap_start) \
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pm->pm_gap_start = vr; \
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if (vr == pm->pm_gap_end) \
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pm->pm_gap_end = vr + 1; \
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} while (0)
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#define GAP_SHRINK(pm,vr) do if (CPU_ISSUN4 || CPU_ISSUN4C) { \
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#define GAP_SHRINK(pm,vr) do if (CPU_HAS_SUNMMU) { \
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int x; \
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x = pm->pm_gap_start + (pm->pm_gap_end - pm->pm_gap_start) / 2; \
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if (vr > x) { \
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@ -1078,7 +1077,7 @@ pmap_growkernel(vaddr_t eva)
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return (virtual_end);
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/* For now, only implemented for sun4/sun4c */
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KASSERT(CPU_ISSUN4 || CPU_ISSUN4C);
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KASSERT(CPU_HAS_SUNMMU);
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/*
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* Map in the next region(s)
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@ -2142,7 +2141,7 @@ ctx_alloc(pm)
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if (pmapdebug & PDB_CTX_ALLOC)
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printf("ctx_alloc[%d](%p)\n", cpu_number(), pm);
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#endif
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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gap_start = pm->pm_gap_start;
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gap_end = pm->pm_gap_end;
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}
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@ -2172,7 +2171,7 @@ ctx_alloc(pm)
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c->c_pmap->pm_ctx = NULL;
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c->c_pmap->pm_ctxnum = 0;
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doflush = (CACHEINFO.c_vactype != VAC_NONE);
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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if (gap_start < c->c_pmap->pm_gap_start)
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gap_start = c->c_pmap->pm_gap_start;
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if (gap_end > c->c_pmap->pm_gap_end)
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@ -2185,7 +2184,8 @@ ctx_alloc(pm)
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pm->pm_ctx = c;
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pm->pm_ctxnum = cnum;
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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/*
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* Write pmap's region (3-level MMU) or segment table into
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* the MMU.
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@ -2322,7 +2322,7 @@ ctx_free(pm)
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pm->pm_ctx = NULL;
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pm->pm_ctxnum = 0;
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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int octx = getcontext4();
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setcontext4(ctx);
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cache_flush_context(ctx);
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@ -2987,7 +2987,7 @@ static void pv_uncache(struct vm_page *pg)
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pv_changepte4m(pg, 0, SRMMU_PG_C);
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#endif
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4 || CPU_ISSUN4C)
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if (CPU_HAS_SUNMMU)
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pv_changepte4_4c(pg, PG_NC, 0);
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#endif
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simple_unlock(&pg->mdpage.pv_slock);
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@ -3122,7 +3122,7 @@ pmap_bootstrap(nctx, nregion, nsegment)
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#if defined(SUN4M) || defined(SUN4D)
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pmap_bootstrap4m(p);
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#endif
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} else if (CPU_ISSUN4 || CPU_ISSUN4C) {
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} else if (CPU_HAS_SUNMMU) {
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#if defined(SUN4) || defined(SUN4C)
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pmap_bootstrap4_4c(p, nctx, nregion, nsegment);
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#endif
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@ -4143,7 +4143,7 @@ pmap_init()
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}
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#endif /* SUN4M || SUN4D */
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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sz = NPTESG * sizeof(int);
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pool_init(&pte_pool, sz, 0, 0, 0, "ptemap", NULL);
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}
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@ -4180,26 +4180,22 @@ pmap_quiet_check(struct pmap *pm)
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{
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int vs, vr;
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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#if defined(SUN4_MMU3L)
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if (pm->pm_reglist.tqh_first)
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if (TAILQ_FIRST(&pm->pm_reglist))
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panic("pmap_destroy: region list not empty");
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#endif
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if (pm->pm_seglist.tqh_first)
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if (TAILQ_FIRST(&pm->pm_seglist))
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panic("pmap_destroy: segment list not empty");
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}
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for (vr = 0; vr < NUREG; vr++) {
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struct regmap *rp = &pm->pm_regmap[vr];
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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#if defined(SUN4_MMU3L)
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if (HASSUN4_MMU3L) {
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if (rp->rg_smeg != reginval)
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printf("pmap_chk: spurious smeg in "
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"user region %d\n", vr);
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}
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#endif
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if (HASSUN4_MMU3L) {
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if (rp->rg_smeg != reginval)
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printf("pmap_chk: spurious smeg in "
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"user region %d\n", vr);
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}
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if (CPU_HAS_SRMMU) {
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int n;
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@ -4230,7 +4226,7 @@ pmap_quiet_check(struct pmap *pm)
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printf("pmap_chk: ptes still "
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"allocated in segment %d\n", vs);
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}
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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if (sp->sg_pmeg != seginval)
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printf("pmap_chk: pm %p(%d,%d) "
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"spurious soft pmeg %d\n",
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@ -4242,7 +4238,7 @@ pmap_quiet_check(struct pmap *pm)
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/* Check for spurious pmeg entries in the MMU */
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if (pm->pm_ctx == NULL)
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continue;
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if ((CPU_ISSUN4 || CPU_ISSUN4C)) {
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if (CPU_HAS_SUNMMU) {
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int ctx;
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if (mmu_has_hole && (vr >= 32 || vr < (256 - 32)))
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continue;
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@ -4259,6 +4255,14 @@ pmap_quiet_check(struct pmap *pm)
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setcontext4(ctx);
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}
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}
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if (pm->pm_stats.resident_count) {
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printf("pmap_chk: res count %ld\n",
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pm->pm_stats.resident_count);
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}
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if (pm->pm_stats.wired_count) {
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printf("pmap_chk: wired count %ld\n",
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pm->pm_stats.wired_count);
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}
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}
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#endif /* DEBUG */
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@ -4286,7 +4290,7 @@ pmap_pmap_pool_ctor(void *arg, void *object, int flags)
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/* pm->pm_ctx = NULL; // already done */
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simple_lock_init(&pm->pm_lock);
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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TAILQ_INIT(&pm->pm_seglist);
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#if defined(SUN4_MMU3L)
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TAILQ_INIT(&pm->pm_reglist);
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@ -4393,7 +4397,7 @@ pmap_create()
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/* reset active CPU set */
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pm->pm_cpuset = 0;
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#endif
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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/* reset the region gap */
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pm->pm_gap_start = 0;
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pm->pm_gap_end = VA_VREG(VM_MAXUSER_ADDRESS);
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@ -4526,8 +4530,9 @@ static void pgt_lvl23_remove4_4c(struct pmap *pm, struct regmap *rp,
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/*
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* SRMMU helper to deallocate level 2 & 3 page tables.
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*/
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static void pgt_lvl23_remove4m(struct pmap *pm, struct regmap *rp,
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struct segmap *sp, int vr, int vs)
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static void
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pgt_lvl23_remove4m(struct pmap *pm, struct regmap *rp, struct segmap *sp,
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int vr, int vs)
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{
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/* Invalidate level 2 PTP entry */
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@ -4557,13 +4562,14 @@ static void pgt_lvl23_remove4m(struct pmap *pm, struct regmap *rp,
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}
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#endif /* SUN4M || SUN4D */
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void pmap_remove_all(struct pmap *pm)
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void
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pmap_remove_all(struct pmap *pm)
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{
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if (pm->pm_ctx == NULL)
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return;
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4 || CPU_ISSUN4C) {
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if (CPU_HAS_SUNMMU) {
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int ctx = getcontext4();
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setcontext4(pm->pm_ctxnum);
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cache_flush_context(pm->pm_ctxnum);
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@ -4713,8 +4719,10 @@ pmap_rmk4_4c(pm, va, endva, vr, vs)
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panic("pmap_rmk: too many PTEs in segment; "
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"va 0x%lx; endva 0x%lx", va, endva);
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#endif
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if (pte & PG_WIRED)
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if (pte & PG_WIRED) {
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sp->sg_nwired--;
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pm->pm_stats.wired_count--;
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}
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if (inmmu)
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setpte4(va, 0);
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@ -4883,8 +4891,10 @@ pmap_rmu4_4c(pm, va, endva, vr, vs)
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if (inmmu)
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setpte4(pteva, 0);
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if (pte & PG_WIRED)
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if (pte & PG_WIRED) {
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sp->sg_nwired--;
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pm->pm_stats.wired_count--;
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}
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*ptep = 0;
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pm->pm_stats.resident_count--;
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}
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@ -4979,6 +4989,10 @@ pmap_rmu4m(pm, va, endva, vr, vs)
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setpgt4m_va(va, &pte0[VA_SUN4M_VPG(va)], SRMMU_TEINVALID,
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pm->pm_ctx != NULL, pm->pm_ctxnum, PMAP_CPUSET(pm));
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pm->pm_stats.resident_count--;
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if (sp->sg_wiremap & (1 << VA_SUN4M_VPG(va))) {
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sp->sg_wiremap &= ~(1 << VA_SUN4M_VPG(va));
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pm->pm_stats.wired_count--;
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}
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}
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/*
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@ -5061,8 +5075,10 @@ pmap_page_protect4_4c(pg, prot)
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sp->sg_npte = --nleft;
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ptep = &sp->sg_pte[VA_VPG(va)];
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if (*ptep & PG_WIRED)
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if (*ptep & PG_WIRED) {
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sp->sg_nwired--;
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pm->pm_stats.wired_count--;
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}
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if (sp->sg_pmeg != seginval) {
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/* Update PV flags */
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@ -5259,9 +5275,11 @@ pmap_changeprot4_4c(pm, va, prot, flags)
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if (pte & PG_WIRED && (flags & PMAP_WIRED) == 0) {
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pte &= ~PG_WIRED;
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sp->sg_nwired--;
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pm->pm_stats.wired_count--;
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} else if ((pte & PG_WIRED) == 0 && flags & PMAP_WIRED) {
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pte |= PG_WIRED;
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sp->sg_nwired++;
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pm->pm_stats.wired_count++;
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}
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pte = (pte & ~PG_PROT) | newprot;
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/* Update S/W pte entry */
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@ -5335,13 +5353,6 @@ pmap_page_protect4m(pg, prot)
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printf("pmap_page_protect[%d](0x%lx, 0x%x)\n",
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cpu_number(), VM_PAGE_TO_PHYS(pg), prot);
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#endif
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/*
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* Skip unmanaged pages, or operations that do not take
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* away write permission.
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*/
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if (pg == NULL || prot & VM_PROT_WRITE)
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return;
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s = splvm();
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PMAP_HEAD_TO_MAP_LOCK();
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simple_lock(&pg->mdpage.pv_slock);
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@ -5393,6 +5404,10 @@ pmap_page_protect4m(pg, prot)
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pm->pm_ctx != NULL, pm->pm_ctxnum, PMAP_CPUSET(pm));
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pm->pm_stats.resident_count--;
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if (sp->sg_wiremap & (1 << VA_SUN4M_VPG(va))) {
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sp->sg_wiremap &= ~(1 << VA_SUN4M_VPG(va));
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pm->pm_stats.wired_count--;
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}
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if ((tpte & SRMMU_TETYPE) != SRMMU_TEPTE)
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panic("pmap_page_protect !PG_V: pg %p va %lx", pg, va);
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@ -5526,6 +5541,7 @@ pmap_changeprot4m(pm, va, prot, flags)
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int pte, newprot;
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struct regmap *rp;
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struct segmap *sp;
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boolean_t owired;
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#ifdef DEBUG
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if (pmapdebug & PDB_CHANGEPROT)
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@ -5541,10 +5557,15 @@ pmap_changeprot4m(pm, va, prot, flags)
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sp = &rp->rg_segmap[VA_VSEG(va)];
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pte = sp->sg_pte[VA_SUN4M_VPG(va)];
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if ((pte & SRMMU_PROT_MASK) == newprot) {
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/* only wiring changed, and we ignore wiring */
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pmap_stats.ps_useless_changeprots++;
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return;
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owired = sp->sg_wiremap & (1 << VA_SUN4M_VPG(va));
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if (owired) {
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pm->pm_stats.wired_count--;
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sp->sg_wiremap &= ~(1 << VA_SUN4M_VPG(va));
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}
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if (flags & PMAP_WIRED) {
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pm->pm_stats.wired_count++;
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sp->sg_wiremap |= (1 << VA_SUN4M_VPG(va));
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}
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if (pm->pm_ctx) {
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@ -5691,8 +5712,10 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
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*ptep = 0;
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if (inmmu)
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setpte4(va, 0);
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if (pte & PG_WIRED)
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if (pte & PG_WIRED) {
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sp->sg_nwired--;
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pm->pm_stats.wired_count--;
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}
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pm->pm_stats.resident_count--;
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} else {
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/* adding new entry */
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@ -5722,8 +5745,10 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
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/* Update S/W page table */
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*ptep = pteproto;
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if (pteproto & PG_WIRED)
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if (pteproto & PG_WIRED) {
|
||||
sp->sg_nwired++;
|
||||
pm->pm_stats.wired_count++;
|
||||
}
|
||||
pm->pm_stats.resident_count++;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
@ -5846,12 +5871,7 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
if ((pte & (PG_PFNUM|PG_TYPE)) ==
|
||||
(pteproto & (PG_PFNUM|PG_TYPE))) {
|
||||
/* just changing prot and/or wiring */
|
||||
/* caller should call this directly: */
|
||||
pmap_changeprot4_4c(pm, va, prot, flags);
|
||||
if ((flags & PMAP_WIRED) != 0)
|
||||
pm->pm_stats.wired_count++;
|
||||
else
|
||||
pm->pm_stats.wired_count--;
|
||||
splx(s);
|
||||
return (0);
|
||||
}
|
||||
@ -5884,8 +5904,10 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
}
|
||||
}
|
||||
if (pte & PG_WIRED)
|
||||
if (pte & PG_WIRED) {
|
||||
sp->sg_nwired--;
|
||||
pm->pm_stats.wired_count--;
|
||||
}
|
||||
pm->pm_stats.resident_count--;
|
||||
ptep[VA_VPG(va)] = 0;
|
||||
if (sp->sg_pmeg != seginval)
|
||||
@ -5893,12 +5915,6 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
} else {
|
||||
/* adding new entry */
|
||||
sp->sg_npte++;
|
||||
|
||||
/*
|
||||
* Increment counters
|
||||
*/
|
||||
if ((flags & PMAP_WIRED) != 0)
|
||||
pm->pm_stats.wired_count++;
|
||||
}
|
||||
}
|
||||
|
||||
@ -5915,8 +5931,10 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
/* Update S/W page table */
|
||||
ptep += VA_VPG(va);
|
||||
*ptep = pteproto;
|
||||
if (pteproto & PG_WIRED)
|
||||
if (pteproto & PG_WIRED) {
|
||||
sp->sg_nwired++;
|
||||
pm->pm_stats.wired_count++;
|
||||
}
|
||||
pm->pm_stats.resident_count++;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
@ -6025,7 +6043,7 @@ pmap_lockmmu(vaddr_t sva, size_t sz)
|
||||
struct segmap *sp;
|
||||
int vr, vs;
|
||||
|
||||
if (CPU_ISSUN4M || CPU_ISSUN4D)
|
||||
if (CPU_HAS_SRMMU)
|
||||
return;
|
||||
|
||||
eva = sva + sz;
|
||||
@ -6363,6 +6381,7 @@ pmap_enu4m(pm, va, prot, flags, pg, pteproto)
|
||||
int error = 0;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
boolean_t owired;
|
||||
|
||||
#ifdef DEBUG
|
||||
if (KERNBASE < va)
|
||||
@ -6436,6 +6455,7 @@ pmap_enu4m(pm, va, prot, flags, pg, pteproto)
|
||||
|
||||
sp = &rp->rg_segmap[vs];
|
||||
|
||||
owired = FALSE;
|
||||
if ((pte = sp->sg_pte) == NULL) {
|
||||
/* definitely a new mapping */
|
||||
int i;
|
||||
@ -6475,10 +6495,6 @@ pmap_enu4m(pm, va, prot, flags, pg, pteproto)
|
||||
/* just changing prot and/or wiring */
|
||||
/* caller should call this directly: */
|
||||
pmap_changeprot4m(pm, va, prot, flags);
|
||||
if ((flags & PMAP_WIRED) != 0)
|
||||
pm->pm_stats.wired_count++;
|
||||
else
|
||||
pm->pm_stats.wired_count--;
|
||||
simple_unlock(&pm->pm_lock);
|
||||
PMAP_MAP_TO_HEAD_UNLOCK();
|
||||
splx(s);
|
||||
@ -6517,15 +6533,10 @@ pmap_enu4m(pm, va, prot, flags, pg, pteproto)
|
||||
SRMMU_TEINVALID, pm->pm_ctx != NULL,
|
||||
pm->pm_ctxnum, PMAP_CPUSET(pm));
|
||||
pm->pm_stats.resident_count--;
|
||||
owired = sp->sg_wiremap & (1 << VA_SUN4M_VPG(va));
|
||||
} else {
|
||||
/* adding new entry */
|
||||
sp->sg_npte++;
|
||||
|
||||
/*
|
||||
* Increment counters
|
||||
*/
|
||||
if ((flags & PMAP_WIRED) != 0)
|
||||
pm->pm_stats.wired_count++;
|
||||
}
|
||||
}
|
||||
|
||||
@ -6544,6 +6555,14 @@ pmap_enu4m(pm, va, prot, flags, pg, pteproto)
|
||||
*/
|
||||
setpgt4m(&sp->sg_pte[VA_SUN4M_VPG(va)], pteproto);
|
||||
pm->pm_stats.resident_count++;
|
||||
if (owired) {
|
||||
pm->pm_stats.wired_count--;
|
||||
sp->sg_wiremap &= ~(1 << VA_SUN4M_VPG(va));
|
||||
}
|
||||
if (flags & PMAP_WIRED) {
|
||||
pm->pm_stats.wired_count++;
|
||||
sp->sg_wiremap |= (1 << VA_SUN4M_VPG(va));
|
||||
}
|
||||
|
||||
out:
|
||||
simple_unlock(&pm->pm_lock);
|
||||
@ -6696,30 +6715,33 @@ pmap_unwire(pm, va)
|
||||
struct pmap *pm;
|
||||
vaddr_t va;
|
||||
{
|
||||
int vr, vs, pte, *ptep;
|
||||
int vr, vs, *ptep;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
|
||||
/* For now, `wired page accounting' is only used on sun4/sun4c */
|
||||
if (CPU_HAS_SRMMU)
|
||||
return;
|
||||
boolean_t owired;
|
||||
|
||||
vr = VA_VREG(va);
|
||||
vs = VA_VSEG(va);
|
||||
rp = &pm->pm_regmap[vr];
|
||||
sp = &rp->rg_segmap[vs];
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
pte = *ptep;
|
||||
|
||||
#if defined(SUN4) || defined(SUN4C)
|
||||
if ((pte & PG_WIRED) == 0) {
|
||||
owired = FALSE;
|
||||
if (CPU_HAS_SUNMMU) {
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
owired = *ptep & PG_WIRED;
|
||||
*ptep &= ~PG_WIRED;
|
||||
}
|
||||
if (CPU_HAS_SRMMU) {
|
||||
owired = sp->sg_wiremap & (1 << VA_SUN4M_VPG(va));
|
||||
sp->sg_wiremap &= ~(1 << VA_SUN4M_VPG(va));
|
||||
}
|
||||
if (!owired) {
|
||||
pmap_stats.ps_useless_changewire++;
|
||||
return;
|
||||
}
|
||||
|
||||
pte &= ~PG_WIRED;
|
||||
*ptep = pte;
|
||||
if (--sp->sg_nwired <= 0) {
|
||||
pm->pm_stats.wired_count--;
|
||||
if (CPU_HAS_SUNMMU && --sp->sg_nwired <= 0) {
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
|
||||
panic("pmap_unwire: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
@ -6728,7 +6750,6 @@ pmap_unwire(pm, va)
|
||||
if (sp->sg_pmeg != seginval)
|
||||
mmu_pmeg_unlock(sp->sg_pmeg);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
@ -7746,7 +7767,7 @@ pmap_dumpsize()
|
||||
sz += npmemarr * sizeof(phys_ram_seg_t);
|
||||
sz += sizeof(kernel_segmap_store);
|
||||
|
||||
if (CPU_ISSUN4 || CPU_ISSUN4C)
|
||||
if (CPU_HAS_SUNMMU)
|
||||
/* For each pmeg in the MMU, we'll write NPTESG PTEs. */
|
||||
sz += (seginval + 1) * NPTESG * sizeof(int);
|
||||
|
||||
@ -7817,7 +7838,7 @@ pmap_dumpmmu(dump, blkno)
|
||||
kcpup->segmapoffset = segmapoffset =
|
||||
memsegoffset + npmemarr * sizeof(phys_ram_seg_t);
|
||||
|
||||
kcpup->npmeg = (CPU_ISSUN4 || CPU_ISSUN4C) ? seginval + 1 : 0;
|
||||
kcpup->npmeg = (CPU_HAS_SUNMMU) ? seginval + 1 : 0;
|
||||
kcpup->pmegoffset = pmegoffset =
|
||||
segmapoffset + kcpup->nsegmap * sizeof(struct segmap);
|
||||
|
||||
@ -8144,7 +8165,9 @@ int pmap_dump(struct pmap *pm)
|
||||
continue;
|
||||
}
|
||||
for (n = 0, i = 0; i < NPTESG; i++) {
|
||||
if (sp->sg_pte[i] & PG_WIRED)
|
||||
if (CPU_HAS_SUNMMU && sp->sg_pte[i] & PG_WIRED)
|
||||
n++;
|
||||
if (CPU_HAS_SRMMU && sp->sg_wiremap & (1 << i))
|
||||
n++;
|
||||
}
|
||||
if (n != sp->sg_nwired)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user