Replace a couple of (*foo_p)()'s with direct calls. All instances occurred
within in functions that were already mmu-arch specific. Some formatting nits.
This commit is contained in:
pk
parent
525cc1eebc
commit
0b59ea6fbd
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.57 1996/05/16 14:30:54 abrown Exp $ */
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/* $NetBSD: pmap.c,v 1.58 1996/05/16 19:19:33 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -415,6 +415,12 @@ u_int getptesw4m __P((struct pmap *pm, vm_offset_t va));
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*/
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#if defined(SUN4M)
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static void mmu_setup4m_L1 __P((int, caddr_t, struct pmap *, caddr_t *));
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static void mmu_setup4m_L2 __P((int, caddr_t, struct regmap *, caddr_t *,
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struct segmap *));
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static int mmu_setup4m_L3 __P((int, caddr_t));
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/*static*/ void mmu_reservemon4m __P((struct pmap *, caddr_t *));
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/*static*/ void pmap_rmk4m __P((struct pmap *, vm_offset_t, vm_offset_t,
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int, int));
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/*static*/ void pmap_rmu4m __P((struct pmap *, vm_offset_t, vm_offset_t,
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@ -430,6 +436,7 @@ u_int getptesw4m __P((struct pmap *pm, vm_offset_t va));
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#endif
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#if defined(SUN4) || defined(SUN4C)
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/*static*/ void mmu_reservemon4_4c __P((int *, int *));
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/*static*/ void pmap_rmk4_4c __P((struct pmap *, vm_offset_t, vm_offset_t,
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int, int));
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/*static*/ void pmap_rmu4_4c __P((struct pmap *, vm_offset_t, vm_offset_t,
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@ -447,22 +454,10 @@ u_int getptesw4m __P((struct pmap *pm, vm_offset_t va));
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#if !defined(SUN4M) && (defined(SUN4) || defined(SUN4C))
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#define pmap_rmk pmap_rmk4_4c
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#define pmap_rmu pmap_rmu4_4c
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#define pmap_enk pmap_enk4_4c
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#define pmap_enu pmap_enu4_4c
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#define pv_changepte pv_changepte4_4c
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#define pv_syncflags pv_syncflags4_4c
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#define pv_link pv_link4_4c
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#define pv_unlink pv_unlink4_4c
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#elif defined(SUN4M) && !(defined(SUN4) || defined(SUN4C))
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#define pmap_rmk pmap_rmk4m
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#define pmap_rmu pmap_rmu4m
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#define pmap_enk pmap_enk4m
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#define pmap_enu pmap_enu4m
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#define pv_changepte pv_changepte4m
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#define pv_syncflags pv_syncflags4m
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#define pv_link pv_link4m
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#define pv_unlink pv_unlink4m
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#else /* must use function pointers */
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@ -488,24 +483,9 @@ void (*pmap_rmk_p) __P((struct pmap *, vm_offset_t, vm_offset_t,
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int, int));
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void (*pmap_rmu_p) __P((struct pmap *, vm_offset_t, vm_offset_t,
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int, int));
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void (*pmap_enk_p) __P((struct pmap *, vm_offset_t, vm_prot_t,
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int, struct pvlist *, int));
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void (*pmap_enu_p) __P((struct pmap *, vm_offset_t, vm_prot_t,
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int, struct pvlist *, int));
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void (*pv_changepte_p) __P((struct pvlist *, int, int));
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int (*pv_syncflags_p) __P((struct pvlist *));
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int (*pv_link_p) __P((struct pvlist *, struct pmap *, vm_offset_t));
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void (*pv_unlink_p) __P((struct pvlist *, struct pmap *,
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vm_offset_t));
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#define pmap_rmk (*pmap_rmk_p)
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#define pmap_rmu (*pmap_rmu_p)
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#define pmap_enk (*pmap_enk_p)
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#define pmap_enu (*pmap_enu_p)
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#define pv_changepte (*pv_changepte_p)
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#define pv_syncflags (*pv_syncflags_p)
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#define pv_link (*pv_link_p)
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#define pv_unlink (*pv_unlink_p)
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#endif
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@ -589,12 +569,12 @@ getptesw4m(pm, va) /* Assumes L3 mapping! */
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rm = &pm->pm_regmap[VA_VREG(va)];
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#ifdef DEBUG
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if (rm == NULL)
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panic("getptesw4m: no regmap entry");
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panic("getptesw4m: no regmap entry");
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#endif
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sm = &rm->rg_segmap[VA_VSEG(va)];
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#ifdef DEBUG
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if (sm == NULL)
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panic("getptesw4m: no segmap");
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panic("getptesw4m: no segmap");
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#endif
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return (sm->sg_pte[VA_SUN4M_VPG(va)]); /* return pte */
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}
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@ -643,7 +623,8 @@ setpte4m(va, pte)
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if (vactype != VAC_NONE)
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cache_flush_page(va);
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/* Now walk tables to find pte. We use ctxinfo to locate the pmap
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/*
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* Now walk tables to find pte. We use ctxinfo to locate the pmap
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* from the current context
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*/
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#ifdef DEBUG
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@ -706,18 +687,9 @@ setpte4m(va, pte)
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} while (0)
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static void sortm __P((struct memarr *, int));
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void mmu_reservemon __P((int *, int *));
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void ctx_alloc __P((struct pmap *));
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void ctx_free __P((struct pmap *));
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void pv_changepte __P((struct pvlist *, int, int));
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int pv_syncflags __P((struct pvlist *));
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void pv_unlink __P((struct pvlist *, struct pmap *, vm_offset_t));
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int pv_link __P((struct pvlist *, struct pmap *, vm_offset_t));
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void pv_flushcache __P((struct pvlist *));
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void pmap_enk __P((struct pmap *, vm_offset_t, vm_prot_t, int,
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struct pvlist *, int));
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void pmap_enu __P((struct pmap *, vm_offset_t, vm_prot_t, int,
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struct pvlist *, int));
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void kvm_iocache __P((caddr_t, int));
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#ifdef DEBUG
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void pm_check __P((char *, struct pmap *));
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@ -895,7 +867,7 @@ pmap_pa_exists(pa)
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*/
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#if defined(SUN4) || defined(SUN4C)
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void
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mmu_reservemon(nrp, nsp)
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mmu_reservemon4_4c(nrp, nsp)
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register int *nrp, *nsp;
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{
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register u_int va = 0, eva = 0;
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@ -986,13 +958,8 @@ mmu_reservemon(nrp, nsp)
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* to the new kernel/ROM mappings.
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*/
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static void mmu_setup4m_L1 __P((int, caddr_t, struct pmap *, caddr_t *));
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static void mmu_setup4m_L2 __P((int, caddr_t, struct regmap *, caddr_t *,
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struct segmap *));
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static int mmu_setup4m_L3 __P((int, caddr_t));
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void mmu_reservemon4m __P((struct pmap *, caddr_t *));
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/* mmu_reservemon4m(): Copies the existing (ROM) page tables to kernel space,
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/*
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* mmu_reservemon4m(): Copies the existing (ROM) page tables to kernel space,
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* converting any L1/L2 PTEs to L3 PTEs. Does *not* copy the L1 entry mapping
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* the kernel at 0xf8000000 (KERNBASE) since we don't want to map 16M of
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* physical memory for the kernel. Thus the kernel must be installed later!
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@ -1762,10 +1729,12 @@ mmu_pagein4m(pm, va, prot)
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register int bits;
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pte = getpte4m(va);
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if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE) /* pte not found == not valid */
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return 0;
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if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE)
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/* pte not found == not valid */
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return 0;
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/* If pte has "correct" protection (according to bits), then
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/*
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* If pte has "correct" protection (according to bits), then
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* something bizarre has happened, so we return -1 to generate
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* a fault. Otherwise, we return 0 and let the VM code reload
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* the page.
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@ -1773,12 +1742,12 @@ mmu_pagein4m(pm, va, prot)
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*/
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if (prot != VM_PROT_NONE)
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bits = ((prot & VM_PROT_WRITE) ? PPROT_RWX_RWX : PPROT_RX_RX);
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bits = ((prot & VM_PROT_WRITE) ? PPROT_RWX_RWX : PPROT_RX_RX);
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else
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bits = 0;
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bits = 0;
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/* If we're in kernelland, mask out user RWX */
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/* if (getcontext() == 0)
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bits |= PPROT_S;
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bits |= PPROT_S;
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*/
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return (bits && (pte & bits) == bits ? -1 : 0);
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}
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@ -2246,7 +2215,7 @@ pv_unlink4_4c(pv, pm, va)
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if (BADALIAS(va, npv->pv_va))
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return;
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pv->pv_flags &= ~PV_NC;
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pv_changepte(pv, 0, PG_NC);
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pv_changepte4_4c(pv, 0, PG_NC);
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}
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}
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@ -2293,7 +2262,7 @@ pv_link4_4c(pv, pm, va)
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vm_first_phys + (pv-pv_table)*NBPG);
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#endif
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pv->pv_flags |= PV_NC;
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pv_changepte(pv, ret = PG_NC, 0);
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pv_changepte4_4c(pv, ret = PG_NC, 0);
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break;
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}
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}
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@ -2553,7 +2522,7 @@ pv_link4m(pv, pm, va)
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vm_first_phys + (pv-pv_table)*NBPG);
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#endif
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pv->pv_flags &= ~PV_C4M;
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pv_changepte(pv, 0, ret = SRMMU_PG_C);
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pv_changepte4m(pv, 0, ret = SRMMU_PG_C);
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/* cache_flush_page(va); XXX: needed? */
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break;
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}
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@ -2718,14 +2687,8 @@ pmap_bootstrap4_4c(nctx, nregion, nsegment)
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pmap_zero_page_p = pmap_zero_page4_4c;
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pmap_changeprot_p = pmap_changeprot4_4c;
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mmu_pagein_p = mmu_pagein4_4c;
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pmap_enk_p = pmap_enk4_4c;
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pmap_enu_p = pmap_enu4_4c;
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pmap_rmk_p = pmap_rmk4_4c;
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pmap_rmu_p = pmap_rmu4_4c;
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pv_changepte_p = pv_changepte4_4c;
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pv_syncflags_p = pv_syncflags4_4c;
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pv_link_p = pv_link4_4c;
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pv_unlink_p = pv_unlink4_4c;
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#endif /* defined SUN4M */
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/*
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@ -2768,7 +2731,7 @@ pmap_bootstrap4_4c(nctx, nregion, nsegment)
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* (otherwise L1-A crashes the machine!).
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*/
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mmu_reservemon(&nregion, &nsegment);
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mmu_reservemon4_4c(&nregion, &nsegment);
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#ifdef MMU_3L
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/* Reserve one region for temporary mappings */
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@ -3065,14 +3028,8 @@ pmap_bootstrap4m(void)
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pmap_zero_page_p = pmap_zero_page4m;
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pmap_changeprot_p = pmap_changeprot4m;
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mmu_pagein_p = mmu_pagein4m;
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pmap_enk_p = pmap_enk4m;
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pmap_enu_p = pmap_enu4m;
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pmap_rmk_p = pmap_rmk4m;
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pmap_rmu_p = pmap_rmu4m;
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pv_changepte_p = pv_changepte4m;
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pv_syncflags_p = pv_syncflags4m;
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pv_link_p = pv_link4m;
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pv_unlink_p = pv_unlink4m;
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#endif /* defined Sun4/Sun4c */
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/*
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@ -4014,7 +3971,7 @@ pmap_rmk4_4c(pm, va, endva, vr, vs)
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if (managed(i)) {
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pv = pvhead(i);
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pv->pv_flags |= MR4_4C(tpte);
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pv_unlink(pv, pm, va);
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pv_unlink4_4c(pv, pm, va);
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}
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}
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nleft--;
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@ -4116,7 +4073,7 @@ pmap_rmk4m(pm, va, endva, vr, vs)
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if (managed(i)) {
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pv = pvhead(i);
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pv->pv_flags |= MR4M(tpte);
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pv_unlink(pv, pm, va);
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pv_unlink4m(pv, pm, va);
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}
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}
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nleft--;
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@ -4133,7 +4090,8 @@ pmap_rmk4m(pm, va, endva, vr, vs)
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tlb_flush_segment(vr, vs); /* Paranoia? */
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/* We need to free the segment table. The problem is that
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/*
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* We need to free the segment table. The problem is that
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* we can't free the initial (bootstrap) mapping, so
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* we have to explicitly check for this case (ugh).
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*/
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@ -4207,7 +4165,7 @@ pmap_rmu4_4c(pm, va, endva, vr, vs)
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if ((tpte & PG_TYPE) == PG_OBMEM) {
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i = ptoa(HWTOSW(tpte & PG_PFNUM));
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if (managed(i))
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pv_unlink(pvhead(i), pm, va);
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pv_unlink4_4c(pvhead(i), pm, va);
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}
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nleft--;
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*pte = 0;
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@ -4272,7 +4230,7 @@ pmap_rmu4_4c(pm, va, endva, vr, vs)
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if (managed(i)) {
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pv = pvhead(i);
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pv->pv_flags |= MR4_4C(tpte);
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pv_unlink(pv, pm, va);
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pv_unlink4_4c(pv, pm, va);
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}
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}
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nleft--;
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@ -4391,7 +4349,7 @@ pmap_rmu4m(pm, va, endva, vr, vs)
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if (managed(i)) {
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pv = pvhead(i);
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pv->pv_flags |= MR4M(tpte);
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pv_unlink(pv, pm, va);
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pv_unlink4m(pv, pm, va);
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}
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}
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nleft--;
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@ -4464,7 +4422,7 @@ pmap_page_protect4_4c(pa, prot)
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return;
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write_user_windows(); /* paranoia */
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if (prot & VM_PROT_READ) {
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pv_changepte(pvhead(pa), 0, PG_W);
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pv_changepte4_4c(pvhead(pa), 0, PG_W);
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return;
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}
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@ -4907,7 +4865,7 @@ pmap_page_protect4m(pa, prot)
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flags |= MR4M(tpte);
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if (nleft)
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setptesw4m(pm, va, SRMMU_TEINVALID);
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setptesw4m(pm, va, SRMMU_TEINVALID);
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else {
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if (pm == pmap_kernel()) {
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tlb_flush_segment(vr, vs); /* Paranoid? */
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@ -5241,7 +5199,7 @@ printf("pmap_enk: changing existing va=>pa entry: va %lx, pteproto %x\n",
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*/
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addr = ptoa(HWTOSW(tpte & PG_PFNUM));
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if (managed(addr))
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pv_unlink(pvhead(addr), pm, va);
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pv_unlink4_4c(pvhead(addr), pm, va);
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if ((tpte & PG_NC) == 0) {
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setcontext(0); /* ??? */
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if (vactype != VAC_NONE)
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@ -5259,7 +5217,7 @@ printf("pmap_enk: changing existing va=>pa entry: va %lx, pteproto %x\n",
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* unique (hence will never cause a second call to malloc).
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*/
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if (pv != NULL)
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pteproto |= pv_link(pv, pm, va);
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pteproto |= pv_link4_4c(pv, pm, va);
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if (sp->sg_pmeg == seginval) {
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register int tva;
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@ -5432,7 +5390,7 @@ curproc->p_comm, curproc->p_pid, va);*/
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if ((tpte & PG_TYPE) == PG_OBMEM) {
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addr = ptoa(HWTOSW(tpte & PG_PFNUM));
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if (managed(addr))
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pv_unlink(pvhead(addr), pm, va);
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pv_unlink4_4c(pvhead(addr), pm, va);
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if (vactype != VAC_NONE &&
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doflush && (tpte & PG_NC) == 0)
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cache_flush_page((int)va);
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@ -5450,7 +5408,7 @@ curproc->p_comm, curproc->p_pid, va);*/
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}
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if (pv != NULL)
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pteproto |= pv_link(pv, pm, va);
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pteproto |= pv_link4_4c(pv, pm, va);
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/*
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* Update hardware & software PTEs.
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@ -5520,14 +5478,14 @@ pmap_enter4m(pm, va, pa, prot, wired)
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pm, va, pa, prot, wired);
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#endif
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if (!(pa & PMAP_NC)) /* Check & set cache bit */
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pteproto = SRMMU_PG_C;
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pteproto = SRMMU_PG_C;
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else
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pteproto = 0;
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pteproto = 0;
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if (pa & PMAP_TYPE4M) { /* this page goes in an iospace */
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if (cpumod == SUN4M_MS)
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panic("pmap_enter4m: attempt to use 36-bit iospace on "
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"MicroSPARC");
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panic("pmap_enter4m: attempt to use 36-bit iospace on"
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" MicroSPARC");
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pteproto |= (pa & PMAP_TYPE4M) << PMAP_PTESHFT4M;
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}
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@ -5558,9 +5516,9 @@ pmap_enter4m(pm, va, pa, prot, wired)
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ctx = getcontext();
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||||
|
||||
if (pm == pmap_kernel())
|
||||
pmap_enk(pm, va, prot, wired, pv, pteproto | PPROT_S);
|
||||
pmap_enk4m(pm, va, prot, wired, pv, pteproto | PPROT_S);
|
||||
else
|
||||
pmap_enu(pm, va, prot, wired, pv, pteproto);
|
||||
pmap_enu4m(pm, va, prot, wired, pv, pteproto);
|
||||
|
||||
setcontext(ctx);
|
||||
}
|
||||
|
|
@ -5618,7 +5576,7 @@ printf("pmap_enk4m: changing existing va=>pa entry: va %lx, pteproto %x, "
|
|||
addr = ptoa(HWTOSW((tpte & SRMMU_PPNMASK) >>
|
||||
SRMMU_PPNSHIFT));
|
||||
if (managed(addr))
|
||||
pv_unlink(pvhead(addr), pm, va);
|
||||
pv_unlink4m(pvhead(addr), pm, va);
|
||||
if (tpte & SRMMU_PG_C) {
|
||||
setcontext(0); /* ??? */
|
||||
if (vactype != VAC_NONE)
|
||||
|
|
@ -5667,17 +5625,6 @@ pmap_enu4m(pm, va, prot, wired, pv, pteproto)
|
|||
rp = &pm->pm_regmap[vr];
|
||||
s = splpmap(); /* XXX conservative */
|
||||
|
||||
/*
|
||||
* If there is no space in which the PTEs can be written
|
||||
* while they are not in the hardware, this must be a new
|
||||
* virtual segment. Get PTE space and count the segment.
|
||||
*
|
||||
* TO SPEED UP CTX ALLOC, PUT SEGMENT BOUNDS STUFF HERE
|
||||
* AND IN pmap_rmu()
|
||||
*/
|
||||
|
||||
GAP_SHRINK(pm,vr);
|
||||
|
||||
#ifdef DEBUG
|
||||
if (pm->pm_gap_end < pm->pm_gap_start) {
|
||||
printf("pmap_enu: gap_start %x, gap_end %x",
|
||||
|
|
@ -5787,7 +5734,7 @@ curproc->p_comm, curproc->p_pid, va);*/
|
|||
addr = ptoa(HWTOSW((tpte & SRMMU_PPNMASK) >>
|
||||
SRMMU_PPNSHIFT));
|
||||
if (managed(addr))
|
||||
pv_unlink(pvhead(addr), pm, va);
|
||||
pv_unlink4m(pvhead(addr), pm, va);
|
||||
if (vactype != VAC_NONE &&
|
||||
doflush && (tpte & SRMMU_PG_C))
|
||||
cache_flush_page((int)va);
|
||||
|
|
@ -5813,7 +5760,7 @@ curproc->p_comm, curproc->p_pid, va);*/
|
|||
setcontext(pm->pm_ctxnum);
|
||||
setpte4m(va, pteproto);
|
||||
} else
|
||||
setptesw4m(pm, va, pteproto);
|
||||
setptesw4m(pm, va, pteproto);
|
||||
/* XXX: restore previous context here? */
|
||||
|
||||
splx(s);
|
||||
|
|
@ -5929,7 +5876,7 @@ pmap_extract4m(pm, va)
|
|||
}
|
||||
#endif
|
||||
} else
|
||||
tpte = getptesw4m(pm, va);
|
||||
tpte = getptesw4m(pm, va);
|
||||
|
||||
setcontext(ctx);
|
||||
|
||||
|
|
@ -6001,22 +5948,6 @@ pmap_collect(pm)
|
|||
{
|
||||
}
|
||||
|
||||
/* XXX XXX XXX (%%%)
|
||||
* NOTE: In the following set of test/clear functions, we test for cpu
|
||||
* architecture explicitly with each call if a GENERIC kernel (i.e. both
|
||||
* SUN4M and (SUN4 || SUN4C) are defined. This could be a rather significant
|
||||
* performance hit (note that this does not apply to single-architecture
|
||||
* kernels). It might be wise to virtualize these functions via fn. pointers
|
||||
* in a manner similar to the other ...4m() functions. This should be tested.
|
||||
* Actually, they now are virtualized. Should still test to see if this is
|
||||
* worth the effort.
|
||||
*
|
||||
* Note also that the 4m-specific routines should eventually service these
|
||||
* requests from their page tables, and the whole pvlist bit mess should
|
||||
* be dropped for the 4m (unless this causes a performance hit from
|
||||
* tracing down pagetables/regmap/segmaps).
|
||||
*/
|
||||
|
||||
#if defined(SUN4) || defined(SUN4C)
|
||||
|
||||
/*
|
||||
|
|
@ -6030,7 +5961,7 @@ pmap_clear_modify4_4c(pa)
|
|||
|
||||
if ((pa & (PMAP_TNC & ~PMAP_NC)) == 0 && managed(pa)) {
|
||||
pv = pvhead(pa);
|
||||
(void) pv_syncflags(pv);
|
||||
(void) pv_syncflags4_4c(pv);
|
||||
pv->pv_flags &= ~PV_MOD;
|
||||
}
|
||||
}
|
||||
|
|
@ -6046,7 +5977,7 @@ pmap_is_modified4_4c(pa)
|
|||
|
||||
if ((pa & (PMAP_TNC & ~PMAP_NC)) == 0 && managed(pa)) {
|
||||
pv = pvhead(pa);
|
||||
if (pv->pv_flags & PV_MOD || pv_syncflags(pv) & PV_MOD)
|
||||
if (pv->pv_flags & PV_MOD || pv_syncflags4_4c(pv) & PV_MOD)
|
||||
return (1);
|
||||
}
|
||||
return (0);
|
||||
|
|
@ -6063,7 +5994,7 @@ pmap_clear_reference4_4c(pa)
|
|||
|
||||
if ((pa & (PMAP_TNC & ~PMAP_NC)) == 0 && managed(pa)) {
|
||||
pv = pvhead(pa);
|
||||
(void) pv_syncflags(pv);
|
||||
(void) pv_syncflags4_4c(pv);
|
||||
pv->pv_flags &= ~PV_REF;
|
||||
}
|
||||
}
|
||||
|
|
@ -6079,14 +6010,24 @@ pmap_is_referenced4_4c(pa)
|
|||
|
||||
if ((pa & (PMAP_TNC & ~PMAP_NC)) == 0 && managed(pa)) {
|
||||
pv = pvhead(pa);
|
||||
if (pv->pv_flags & PV_REF || pv_syncflags(pv) & PV_REF)
|
||||
if (pv->pv_flags & PV_REF || pv_syncflags4_4c(pv) & PV_REF)
|
||||
return (1);
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
#endif /*4,4c*/
|
||||
|
||||
#if defined(SUN4M) /* 4m versions of bit test/set routines */
|
||||
#if defined(SUN4M)
|
||||
|
||||
/*
|
||||
* 4m versions of bit test/set routines
|
||||
*
|
||||
* Note that the 4m-specific routines should eventually service these
|
||||
* requests from their page tables, and the whole pvlist bit mess should
|
||||
* be dropped for the 4m (unless this causes a performance hit from
|
||||
* tracing down pagetables/regmap/segmaps).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Clear the modify bit for the given physical page.
|
||||
*/
|
||||
|
|
@ -6098,7 +6039,7 @@ pmap_clear_modify4m(pa) /* XXX %%%: Should service from swpagetbl for 4m */
|
|||
|
||||
if ((pa & (PMAP_TNC & ~PMAP_NC)) == 0 && managed(pa)) {
|
||||
pv = pvhead(pa);
|
||||
(void) pv_syncflags(pv);
|
||||
(void) pv_syncflags4m(pv);
|
||||
pv->pv_flags &= ~PV_MOD4M;
|
||||
}
|
||||
}
|
||||
|
|
@ -6131,7 +6072,7 @@ pmap_clear_reference4m(pa)
|
|||
|
||||
if ((pa & (PMAP_TNC & ~PMAP_NC)) == 0 && managed(pa)) {
|
||||
pv = pvhead(pa);
|
||||
(void) pv_syncflags(pv);
|
||||
(void) pv_syncflags4m(pv);
|
||||
pv->pv_flags &= ~PV_REF4M;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue