Provide dotg(4) - a driver for the Synposys DesignWare OTG USB IP found
in the RaspberryPI. The driver supports host mode and control, interrupt, and bulk transfers only at this point. Heavily based on the FreeBSD driver by Hans Petter Selasky. Thanks to all who helped. Jared McNeill, Michael van Elst and other.
This commit is contained in:
skrll
parent
bc01998d73
commit
0b453b8d4b
134
sys/arch/arm/broadcom/bcm2835_dotg.c
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134
sys/arch/arm/broadcom/bcm2835_dotg.c
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@ -0,0 +1,134 @@
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/* $NetBSD: bcm2835_dotg.c,v 1.1 2013/01/09 22:23:44 skrll Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Nick Hudson
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bcm2835_dotg.c,v 1.1 2013/01/09 22:23:44 skrll Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <arm/broadcom/bcm2835reg.h>
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#include <arm/broadcom/bcm_amba.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usbdivar.h>
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#include <dev/usb/usb_mem.h>
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#include <dev/usb/dwc_otgvar.h>
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struct bcmdotg_softc {
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struct dwc_otg_softc sc_dotg;
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void *sc_ih;
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};
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static int bcmdotg_match(device_t, struct cfdata *, void *);
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static void bcmdotg_attach(device_t, device_t, void *);
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static void bcmdotg_deferred(device_t);
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CFATTACH_DECL_NEW(dotg_amba, sizeof(struct bcmdotg_softc),
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bcmdotg_match, bcmdotg_attach, NULL, NULL);
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/* ARGSUSED */
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static int
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bcmdotg_match(device_t parent, struct cfdata *match, void *aux)
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{
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struct amba_attach_args *aaa = aux;
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if (strcmp(aaa->aaa_name, "dotg") != 0)
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return 0;
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return 1;
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}
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/* ARGSUSED */
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static void
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bcmdotg_attach(device_t parent, device_t self, void *aux)
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{
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struct bcmdotg_softc *sc = device_private(self);
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struct amba_attach_args *aaa = aux;
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int error;
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sc->sc_dotg.sc_dev = self;
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sc->sc_dotg.sc_iot = aaa->aaa_iot;
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sc->sc_dotg.sc_bus.dmatag = aaa->aaa_dmat;
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error = bus_space_map(aaa->aaa_iot, aaa->aaa_addr, aaa->aaa_size, 0,
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&sc->sc_dotg.sc_ioh);
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if (error) {
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aprint_error_dev(self,
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"can't map registers for %s: %d\n", aaa->aaa_name, error);
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return;
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}
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aprint_naive(": USB controller\n");
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aprint_normal(": USB controller\n");
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sc->sc_ih = bcm2835_intr_establish(aaa->aaa_intr, IPL_USB,
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dwc_otg_intr, &sc->sc_dotg);
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if (sc->sc_ih == NULL) {
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aprint_error_dev(self, "failed to establish interrupt %d\n",
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aaa->aaa_intr);
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goto fail;
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}
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config_defer(self, bcmdotg_deferred);
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return;
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fail:
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if (sc->sc_ih) {
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intr_disestablish(sc->sc_ih);
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sc->sc_ih = NULL;
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}
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bus_space_unmap(sc->sc_dotg.sc_iot, sc->sc_dotg.sc_ioh, aaa->aaa_size);
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}
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static void
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bcmdotg_deferred(device_t self)
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{
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struct bcmdotg_softc *sc = device_private(self);
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int error;
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error = dwc_otg_init(&sc->sc_dotg);
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if (error != 0) {
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aprint_error_dev(self, "couldn't initialize host, error=%d\n",
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error);
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return;
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}
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sc->sc_dotg.sc_child = config_found(sc->sc_dotg.sc_dev, &sc->sc_dotg.sc_bus,
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usbctlprint);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: bcm2835_obio.c,v 1.10 2013/01/08 23:51:33 jmcneill Exp $ */
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/* $NetBSD: bcm2835_obio.c,v 1.11 2013/01/09 22:23:44 skrll Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bcm2835_obio.c,v 1.10 2013/01/08 23:51:33 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bcm2835_obio.c,v 1.11 2013/01/09 22:23:44 skrll Exp $");
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#include "locators.h"
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#include "obio.h"
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@ -119,7 +119,7 @@ static const struct ambadev_locators bcm2835_ambadev_locs[] = {
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.ad_intr = BCM2835_INT_EMMC,
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},
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{
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/* DOTG interface */
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/* DesignWare_OTG USB controller */
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.ad_name = "dotg",
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.ad_addr = BCM2835_USB_BASE,
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.ad_size = BCM2835_USB_SIZE,
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@ -1,4 +1,4 @@
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# $NetBSD: files.bcm2835,v 1.11 2013/01/08 23:52:48 jmcneill Exp $
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# $NetBSD: files.bcm2835,v 1.12 2013/01/09 22:23:44 skrll Exp $
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#
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# Configuration info for Broadcom BCM2835 ARM Peripherals
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#
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@ -50,6 +50,10 @@ file arch/arm/broadcom/bcm2835_plcom.c bcmplcom
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attach sdhc at obio with bcmemmc
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file arch/arm/broadcom/bcm2835_emmc.c bcmemmc
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# USB (BCM2835_USB_BASE)
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attach dotg at obio with dotg_amba
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file arch/arm/broadcom/bcm2835_dotg.c dotg needs-flag
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# GPIO misc. functions
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define bcm2835_gpio_subr
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file arch/arm/broadcom/bcm2835_gpio_subr.c bcm2835_gpio_subr
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@ -1,4 +1,4 @@
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/* $NetBSD: rpi_machdep.c,v 1.22 2013/01/09 00:24:54 jmcneill Exp $ */
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/* $NetBSD: rpi_machdep.c,v 1.23 2013/01/09 22:23:44 skrll Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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@ -30,11 +30,12 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rpi_machdep.c,v 1.22 2013/01/09 00:24:54 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rpi_machdep.c,v 1.23 2013/01/09 22:23:44 skrll Exp $");
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#include "opt_evbarm_boardtype.h"
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#include "sdhc.h"
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#include "dotg.h"
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#include "bcmspi.h"
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#include "bsciic.h"
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#include "plcom.h"
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@ -352,6 +353,9 @@ rpi_bootparams(void)
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#if (NPLCOM > 0)
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(1 << VCPM_POWER_UART0) |
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#endif
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#if (NDOTG > 0)
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(1 << VCPM_POWER_USB) |
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#endif
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#if (NBSCIIC > 0)
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(1 << VCPM_POWER_I2C0) | (1 << VCPM_POWER_I2C1) |
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/* (1 << VCPM_POWER_I2C2) | */
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@ -1,4 +1,4 @@
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# $NetBSD: files,v 1.1061 2012/11/14 02:03:25 rkujawa Exp $
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# $NetBSD: files,v 1.1062 2013/01/09 22:23:45 skrll Exp $
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# @(#)files.newconf 7.5 (Berkeley) 5/10/93
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version 20100430
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@ -1208,6 +1208,11 @@ defflag opt_slhci.h SLHCI_DEBUG SLHCI_TRY_LSVH SLHCI_PROFILE_TRANSFER
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device slhci: usbus, usbroothub
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file dev/ic/sl811hs.c slhci needs-flag
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# DesignWare OTG host controller
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#
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device dotg: usbus, usbroothub, usb_dma
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file dev/usb/dwc_otg.c dotg needs-flag
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# USB HID processing (as used by bluetooth and usb code)
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define hid
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file dev/usb/hid.c hid
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4636
sys/dev/usb/dwc_otg.c
Normal file
4636
sys/dev/usb/dwc_otg.c
Normal file
File diff suppressed because it is too large
Load Diff
880
sys/dev/usb/dwc_otgreg.h
Normal file
880
sys/dev/usb/dwc_otgreg.h
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@ -0,0 +1,880 @@
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/* $FreeBSD: src/sys/dev/usb/controller/dwc_otgreg.h,v 1.6 2012/09/27 15:23:38 hselasky Exp $ */
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/*-
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* Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DWC_OTGREG_H_
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#define _DWC_OTGREG_H_
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#define DOTG_REGSIZE 0x2000
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/* Core Global Registers *****************************************/
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#define DOTG_GOTGCTL 0x0000
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#define DOTG_GOTGINT 0x0004
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#define DOTG_GAHBCFG 0x0008
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#define DOTG_GUSBCFG 0x000C
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#define DOTG_GRSTCTL 0x0010
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#define DOTG_GINTSTS 0x0014
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#define DOTG_GINTMSK 0x0018
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#define DOTG_GRXSTSRD 0x001C
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#define DOTG_GRXSTSPD 0x0020
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#define DOTG_GRXFSIZ 0x0024
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#define DOTG_GNPTXFSIZ 0x0028
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#define DOTG_GNPTXSTS 0x002C
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#define DOTG_GI2CCTL 0x0030
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#define DOTG_GPVNDCTL 0x0034
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#define DOTG_GGPIO 0x0038
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#define DOTG_GUID 0x003C
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#define DOTG_GSNPSID 0x0040
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#define DOTG_GHWCFG1 0x0044
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#define DOTG_GHWCFG2 0x0048
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#define DOTG_GHWCFG3 0x004C
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#define DOTG_GHWCFG4 0x0050
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#define DOTG_GLPMCFG 0x0054
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#define DOTG_HPTXFSIZ 0x0100
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/* start from 0x104, but fifo0 does not exist */
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#define DOTG_DPTXFSIZ(fifo) (0x0100 + (4*(fifo)))
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#define DOTG_DIEPTXF(fifo) (0x0100 + (4*(fifo)))
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/* Device Global Registers ***************************************/
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#define DOTG_DCFG 0x0800
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#define DOTG_DCTL 0x0804
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#define DOTG_DSTS 0x0808
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#define DOTG_DIEPMSK 0x0810
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#define DOTG_DOEPMSK 0x0814
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#define DOTG_DAINT 0x0818
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#define DOTG_DAINTMSK 0x081C
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#define DOTG_DTKNQR1 0x0820
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#define DOTG_DTKNQR2 0x0824
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#define DOTG_DVBUSDIS 0x0828
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#define DOTG_DVBUSPULSE 0x082C
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#define DOTG_DTHRCTL 0x0830
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#define DOTG_DTKNQR4 0x0834
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#define DOTG_DIEPEMPMSK 0x0834
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#define DOTG_DEACHINT 0x0838
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#define DOTG_DEACHINTMSK 0x083C
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#define DOTG_DIEPEACHINTMSK(ch) (0x0840 + (4*(ch)))
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#define DOTG_DOEPEACHINTMSK(ch) (0x0880 + (4*(ch)))
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/* Device Endpoint Specific Registers ****************************/
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#define DOTG_DIEPCTL(ep) (0x0900 + (32*(ep)))
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#define DOTG_DIEPINT(ep) (0x0908 + (32*(ep)))
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#define DOTG_DIEPTSIZ(ep) (0x0910 + (32*(ep)))
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#define DOTG_DIEPDMA(ep) (0x0914 + (32*(ep)))
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#define DOTG_DTXFSTS(ep) (0x0918 + (32*(ep)))
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#define DOTG_DIEPDMAB(ep) (0x091c + (32*(ep)))
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#define DOTG_DOEPCTL(ep) (0x0B00 + (32*(ep)))
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#define DOTG_DOEPFN(ep) (0x0B04 + (32*(ep)))
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#define DOTG_DOEPINT(ep) (0x0B08 + (32*(ep)))
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#define DOTG_DOEPTSIZ(ep) (0x0B10 + (32*(ep)))
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#define DOTG_DOEPDMA(ep) (0x0B14 + (32*(ep)))
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#define DOTG_DOEPDMAB(ep) (0x0B1c + (32*(ep)))
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/* Host Global Registers *****************************************/
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#define DOTG_HCFG 0x0400
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#define DOTG_HFIR 0x0404
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#define DOTG_HFNUM 0x0408
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#define DOTG_HPTXSTS 0x0410
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#define DOTG_HAINT 0x0414
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#define DOTG_HAINTMSK 0x0418
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#define DOTG_HFLBADDR 0x041C
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#define DOTG_HPRT 0x0440
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/* Host Port CSRs ************************************************/
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/* Power and clock gating CSR */
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#define DOTG_PCGCCTL 0x0E00
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/* Host Channel Specific Registers *******************************/
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#define DOTG_HCCHAR(ch) (0x0500 + (32*(ch)))
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#define DOTG_HCSPLT(ch) (0x0504 + (32*(ch)))
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#define DOTG_HCINT(ch) (0x0508 + (32*(ch)))
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#define DOTG_HCINTMSK(ch) (0x050C + (32*(ch)))
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#define DOTG_HCTSIZ(ch) (0x0510 + (32*(ch)))
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#define DOTG_HCDMA(ch) (0x0514 + (32*(ch)))
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#define DOTG_HCDMAB(ch) (0x051C + (32*(ch)))
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||||
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/* FIFO Access Registers (PIO-mode) ******************************/
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#define DOTG_DFIFO(n) (0x1000 + (0x1000 * (n)))
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/*****************************************************************/
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/* Core Control and Status Register */
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#define GOTGCTL_CHIRP_ON (1<<27)
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#define GOTGCTL_BSESVLD (1<<19)
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#define GOTGCTL_ASESVLD (1<<18)
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#define GOTGCTL_DBNCTIME (1<<17)
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#define GOTGCTL_CONIDSTS (1<<16)
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#define GOTGCTL_DEVHNPEN (1<<11)
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#define GOTGCTL_HSTSETHNPEN (1<<10)
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#define GOTGCTL_HNPREQ (1<<9)
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#define GOTGCTL_HSTNEGSCS (1<<8)
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#define GOTGCTL_SESREQ (1<<1)
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#define GOTGCTL_SESREQSCS (1<<0)
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#define GOTGCTL_DBNCEDONE (1<<19)
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#define GOTGCTL_ADEVTOUTCHG (1<<18)
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#define GOTGCTL_HSTNEGDET (1<<17)
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#define GOTGCTL_HSTNEGSUCSTSCHG (1<<9)
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#define GOTGCTL_SESREQSUCSTSCHG (1<<8)
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#define GOTGCTL_SESENDDET (1<<2)
|
||||
|
||||
/* Core AHB Configuration Register */
|
||||
#define GAHBCFG_PTXFEMPLVL (1<<8)
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#define GAHBCFG_NPTXFEMPLVL (1<<7)
|
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#define GAHBCFG_DMAEN (1<<5)
|
||||
#define GAHBCFG_HBSTLEN_MASK 0x0000001e
|
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#define GAHBCFG_HBSTLEN_SHIFT 1
|
||||
#define GAHBCFG_GLBLINTRMSK (1<<0)
|
||||
|
||||
/* Core USB Configuration Register */
|
||||
#define GUSBCFG_CORRUPTTXPACKET (1<<31)
|
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#define GUSBCFG_FORCEDEVMODE (1<<30)
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#define GUSBCFG_FORCEHOSTMODE (1<<29)
|
||||
#define GUSBCFG_NO_PULLUP (1<<27)
|
||||
#define GUSBCFG_IC_USB_CAP (1<<26)
|
||||
#define GUSBCFG_TERMSELDLPULSE (1<<22)
|
||||
#define GUSBCFG_ULPIEXTVBUSINDICATOR (1<<21)
|
||||
#define GUSBCFG_ULPIEXTVBUSDRV (1<<20)
|
||||
#define GUSBCFG_ULPICLKSUSM (1<<19)
|
||||
#define GUSBCFG_ULPIAUTORES (1<<18)
|
||||
#define GUSBCFG_ULPIFSLS (1<<17)
|
||||
#define GUSBCFG_OTGI2CSEL (1<<16)
|
||||
#define GUSBCFG_PHYLPWRCLKSEL (1<<15)
|
||||
#define GUSBCFG_USBTRDTIM_MASK 0x00003c00
|
||||
#define GUSBCFG_USBTRDTIM_SHIFT 10
|
||||
#define GUSBCFG_TRD_TIM_SET(x) (((x) & 15) << 10)
|
||||
#define GUSBCFG_HNPCAP (1<<9)
|
||||
#define GUSBCFG_SRPCAP (1<<8)
|
||||
#define GUSBCFG_DDRSEL (1<<7)
|
||||
#define GUSBCFG_PHYSEL (1<<6)
|
||||
#define GUSBCFG_FSINTF (1<<5)
|
||||
#define GUSBCFG_ULPI_UTMI_SEL (1<<4)
|
||||
#define GUSBCFG_PHYIF (1<<3)
|
||||
#define GUSBCFG_TOUTCAL_MASK 0x00000007
|
||||
#define GUSBCFG_TOUTCAL_SHIFT 0
|
||||
|
||||
/* Core Reset Register */
|
||||
#define GRSTCTL_AHBIDLE (1<<31)
|
||||
#define GRSTCTL_DMAREQ (1<<30)
|
||||
#define GRSTCTL_TXFNUM_MASK 0x000007c0
|
||||
#define GRSTCTL_TXFNUM_SHIFT 6
|
||||
#define GRSTCTL_TXFIFO(n) (((n) & 31) << 6)
|
||||
#define GRSTCTL_TXFFLSH (1<<5)
|
||||
#define GRSTCTL_RXFFLSH (1<<4)
|
||||
#define GRSTCTL_INTKNQFLSH (1<<3)
|
||||
#define GRSTCTL_FRMCNTRRST (1<<2)
|
||||
#define GRSTCTL_HSFTRST (1<<1)
|
||||
#define GRSTCTL_CSFTRST (1<<0)
|
||||
|
||||
/* Core Interrupt Register */
|
||||
#define GINTSTS_WKUPINT (1<<31)
|
||||
#define GINTSTS_SESSREQINT (1<<30)
|
||||
#define GINTSTS_DISCONNINT (1<<29)
|
||||
#define GINTSTS_CONIDSTSCHNG (1<<28)
|
||||
#define GINTSTS_LPM (1<<27)
|
||||
#define GINTSTS_PTXFEMP (1<<26)
|
||||
#define GINTSTS_HCHINT (1<<25)
|
||||
#define GINTSTS_PRTINT (1<<24)
|
||||
#define GINTSTS_RESETDET (1<<23)
|
||||
#define GINTSTS_FETSUSP (1<<22)
|
||||
#define GINTSTS_INCOMPLP (1<<21)
|
||||
#define GINTSTS_INCOMPISOIN (1<<20)
|
||||
#define GINTSTS_OEPINT (1<<19)
|
||||
#define GINTSTS_IEPINT (1<<18)
|
||||
#define GINTSTS_EPMIS (1<<17)
|
||||
#define GINTSTS_RESTORE_DONE (1<<16)
|
||||
#define GINTSTS_EOPF (1<<15)
|
||||
#define GINTSTS_ISOOUTDROP (1<<14)
|
||||
#define GINTSTS_ENUMDONE (1<<13)
|
||||
#define GINTSTS_USBRST (1<<12)
|
||||
#define GINTSTS_USBSUSP (1<<11)
|
||||
#define GINTSTS_ERLYSUSP (1<<10)
|
||||
#define GINTSTS_I2CINT (1<<9)
|
||||
#define GINTSTS_ULPICKINT (1<<8)
|
||||
#define GINTSTS_GOUTNAKEFF (1<<7)
|
||||
#define GINTSTS_GINNAKEFF (1<<6)
|
||||
#define GINTSTS_NPTXFEMP (1<<5)
|
||||
#define GINTSTS_RXFLVL (1<<4)
|
||||
#define GINTSTS_SOF (1<<3)
|
||||
#define GINTSTS_OTGINT (1<<2)
|
||||
#define GINTSTS_MODEMIS (1<<1)
|
||||
#define GINTSTS_CURMOD (1<<0)
|
||||
|
||||
/* Core Interrupt Mask Register */
|
||||
#define GINTMSK_WKUPINTMSK (1<<31)
|
||||
#define GINTMSK_SESSREQINTMSK (1<<30)
|
||||
#define GINTMSK_DISCONNINTMSK (1<<29)
|
||||
#define GINTMSK_CONIDSTSCHNGMSK (1<<28)
|
||||
#define GINTMSK_PTXFEMPMSK (1<<26)
|
||||
#define GINTMSK_HCHINTMSK (1<<25)
|
||||
#define GINTMSK_PRTINTMSK (1<<24)
|
||||
#define GINTMSK_FETSUSPMSK (1<<22)
|
||||
#define GINTMSK_INCOMPLPMSK (1<<21)
|
||||
#define GINTMSK_INCOMPISOINMSK (1<<20)
|
||||
#define GINTMSK_OEPINTMSK (1<<19)
|
||||
#define GINTMSK_IEPINTMSK (1<<18)
|
||||
#define GINTMSK_EPMISMSK (1<<17)
|
||||
#define GINTMSK_EOPFMSK (1<<15)
|
||||
#define GINTMSK_ISOOUTDROPMSK (1<<14)
|
||||
#define GINTMSK_ENUMDONEMSK (1<<13)
|
||||
#define GINTMSK_USBRSTMSK (1<<12)
|
||||
#define GINTMSK_USBSUSPMSK (1<<11)
|
||||
#define GINTMSK_ERLYSUSPMSK (1<<10)
|
||||
#define GINTMSK_I2CINTMSK (1<<9)
|
||||
#define GINTMSK_ULPICKINTMSK (1<<8)
|
||||
#define GINTMSK_GOUTNAKEFFMSK (1<<7)
|
||||
#define GINTMSK_GINNAKEFFMSK (1<<6)
|
||||
#define GINTMSK_NPTXFEMPMSK (1<<5)
|
||||
#define GINTMSK_RXFLVLMSK (1<<4)
|
||||
#define GINTMSK_SOFMSK (1<<3)
|
||||
#define GINTMSK_OTGINTMSK (1<<2)
|
||||
#define GINTMSK_MODEMISMSK (1<<1)
|
||||
#define GINTMSK_CURMODMSK (1<<0)
|
||||
|
||||
/* Core Receive Status Queue Read Register (Host mode) */
|
||||
#define GRXSTSRH_PKTSTS_MASK 0x001e0000
|
||||
#define GRXSTSRH_PKTSTS_SHIFT 17
|
||||
#define GRXSTSRH_DPID_MASK 0x00018000
|
||||
#define GRXSTSRH_DPID_SHIFT 15
|
||||
#define GRXSTSRH_BCNT_MASK 0x00007ff0
|
||||
#define GRXSTSRH_BCNT_SHIFT 4
|
||||
#define GRXSTSRH_CHNUM_MASK 0x0000000f
|
||||
#define GRXSTSRH_CHNUM_SHIFT 0
|
||||
|
||||
/* Core Receive Status Queue Read Register (Device mode) */
|
||||
#define GRXSTSRD_FN_MASK 0x01e00000
|
||||
#define GRXSTSRD_FN_GET(x) (((x) >> 21) & 15)
|
||||
#define GRXSTSRD_FN_SHIFT 21
|
||||
#define GRXSTSRD_PKTSTS_MASK 0x001e0000
|
||||
#define GRXSTSRD_PKTSTS_SHIFT 17
|
||||
#define GRXSTSRH_IN_DATA (2<<17)
|
||||
#define GRXSTSRH_IN_COMPLETE (3<<17)
|
||||
#define GRXSTSRH_DT_ERROR (5<<17)
|
||||
#define GRXSTSRH_HALTED (7<<17)
|
||||
#define GRXSTSRD_GLOB_OUT_NAK (1<<17)
|
||||
#define GRXSTSRD_OUT_DATA (2<<17)
|
||||
#define GRXSTSRD_OUT_COMPLETE (3<<17)
|
||||
#define GRXSTSRD_STP_COMPLETE (4<<17)
|
||||
#define GRXSTSRD_STP_DATA (6<<17)
|
||||
#define GRXSTSRD_DPID_MASK 0x00018000
|
||||
#define GRXSTSRD_DPID_SHIFT 15
|
||||
#define GRXSTSRD_DPID_DATA0 (0<<15)
|
||||
#define GRXSTSRD_DPID_DATA1 (2<<15)
|
||||
#define GRXSTSRD_DPID_DATA2 (1<<15)
|
||||
#define GRXSTSRD_DPID_MDATA (3<<15)
|
||||
#define GRXSTSRD_BCNT_MASK 0x00007ff0
|
||||
#define GRXSTSRD_BCNT_GET(x) (((x) >> 4) & 0x7FF)
|
||||
#define GRXSTSRD_BCNT_SHIFT 4
|
||||
#define GRXSTSRD_CHNUM_MASK 0x0000000f
|
||||
#define GRXSTSRD_CHNUM_GET(x) ((x) & 15)
|
||||
#define GRXSTSRD_CHNUM_SHIFT 0
|
||||
|
||||
/* Core Receive FIFO Size Register */
|
||||
#define GRXFSIZ_RXFDEP_MASK 0x0000ffff
|
||||
#define GRXFSIZ_RXFDEP_SHIFT 0
|
||||
|
||||
/* Core Non-Periodic Transmit FIFO Size Register */
|
||||
#define GNPTXFSIZ_NPTXFDEP_MASK 0xffff0000
|
||||
#define GNPTXFSIZ_NPTXFDEP_SHIFT 0
|
||||
#define GNPTXFSIZ_NPTXFSTADDR_MASK 0x0000ffff
|
||||
#define GNPTXFSIZ_NPTXFSTADDR_SHIFT 16
|
||||
|
||||
/* Core Non-Periodic Transmit FIFO/Queue Status Register */
|
||||
#define GNPTXSTS_NPTXQTOP_SHIFT 24
|
||||
#define GNPTXSTS_NPTXQTOP_MASK 0x7f000000
|
||||
#define GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16
|
||||
#define GNPTXSTS_NPTXQSPCAVAIL_MASK 0x00ff0000
|
||||
#define GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0
|
||||
#define GNPTXSTS_NPTXFSPCAVAIL_MASK 0x0000ffff
|
||||
|
||||
/* Core I2C Access Register */
|
||||
#define GI2CCTL_BSYDNE_SC (1<<31)
|
||||
#define GI2CCTL_RW (1<<30)
|
||||
#define GI2CCTL_I2CDATSE0 (1<<28)
|
||||
#define GI2CCTL_I2CDEVADR_SHIFT 26
|
||||
#define GI2CCTL_I2CDEVADR_MASK 0x0c000000
|
||||
#define GI2CCTL_I2CSUSPCTL (1<<25)
|
||||
#define GI2CCTL_ACK (1<<24)
|
||||
#define GI2CCTL_I2CEN (1<<23)
|
||||
#define GI2CCTL_ADDR_SHIFT 16
|
||||
#define GI2CCTL_ADDR_MASK 0x007f0000
|
||||
#define GI2CCTL_REGADDR_SHIFT 8
|
||||
#define GI2CCTL_REGADDR_MASK 0x0000ff00
|
||||
#define GI2CCTL_RWDATA_SHIFT 0
|
||||
#define GI2CCTL_RWDATA_MASK 0x000000ff
|
||||
|
||||
/* Core Vendor Control Register */
|
||||
#define GPVNDCTL_DISULPIDRVR (1<<31)
|
||||
#define GPVNDCTL_VSTSDONE (1<<27)
|
||||
#define GPVNDCTL_VSTSBSY (1<<26)
|
||||
#define GPVNDCTL_NEWREGREQ (1<<25)
|
||||
#define GPVNDCTL_REGWR (1<<22)
|
||||
#define GPVNDCTL_REGADDR_SHIFT 16
|
||||
#define GPVNDCTL_REGADDR_MASK 0x003f0000
|
||||
#define GPVNDCTL_VCTRL_SHIFT 8
|
||||
#define GPVNDCTL_VCTRL_MASK 0x0000ff00
|
||||
#define GPVNDCTL_REGDATA_SHIFT 0
|
||||
#define GPVNDCTL_REGDATA_MASK 0x000000ff
|
||||
|
||||
/* Core General Purpose I/O Register */
|
||||
#define GGPIO_GPO_SHIFT 16
|
||||
#define GGPIO_GPO_MASK 0xffff0000
|
||||
#define GGPIO_GPI_SHIFT 0
|
||||
#define GGPIO_GPI_MASK 0x0000ffff
|
||||
|
||||
/* Core HW Config1 Register */
|
||||
#define GHWCFG1_GET_DIR(x, n) (((x) >> (2 * (n))) & 3)
|
||||
#define GHWCFG1_BIDIR 0
|
||||
#define GHWCFG1_IN 1
|
||||
#define GHWCFG1_OUT 2
|
||||
|
||||
/* Core HW Config2 Register */
|
||||
#define GHWCFG2_TKNQDEPTH_SHIFT 26
|
||||
#define GHWCFG2_TKNQDEPTH_MASK 0x7c000000
|
||||
#define GHWCFG2_PTXQDEPTH_SHIFT 24
|
||||
#define GHWCFG2_PTXQDEPTH_MASK 0x03000000
|
||||
#define GHWCFG2_NPTXQDEPTH_SHIFT 22
|
||||
#define GHWCFG2_NPTXQDEPTH_MASK 0x00c00000
|
||||
#define GHWCFG2_MPI (1<<20)
|
||||
#define GHWCFG2_DYNFIFOSIZING (1<<19)
|
||||
#define GHWCFG2_PERIOSUPPORT (1<<18)
|
||||
#define GHWCFG2_NUMHSTCHNL_SHIFT 14
|
||||
#define GHWCFG2_NUMHSTCHNL_MASK 0x0003c000
|
||||
#define GHWCFG2_NUMHSTCHNL_GET(x) ((((x) >> 14) & 15) + 1)
|
||||
#define GHWCFG2_NUMDEVEPS_SHIFT 10
|
||||
#define GHWCFG2_NUMDEVEPS_MASK 0x00003c00
|
||||
#define GHWCFG2_NUMDEVEPS_GET(x) ((((x) >> 10) & 15) + 1)
|
||||
#define GHWCFG2_FSPHYTYPE_SHIFT 8
|
||||
#define GHWCFG2_FSPHYTYPE_MASK 0x00000300
|
||||
#define GHWCFG2_HSPHYTYPE_SHIFT 6
|
||||
#define GHWCFG2_HSPHYTYPE_MASK 0x000000c0
|
||||
#define GHWCFG2_SINGPNT (1<<5)
|
||||
#define GHWCFG2_OTGARCH_SHIFT 3
|
||||
#define GHWCFG2_OTGARCH_MASK 0x00000018
|
||||
#define GHWCFG2_OTGMODE_SHIFT 0
|
||||
#define GHWCFG2_OTGMODE_MASK 0x00000007
|
||||
|
||||
#define OTGARCH_SLAVE_ONLY 0
|
||||
#define OTGARCH_EXT_DMA 1
|
||||
#define OTGARCH_INT_DMA 2
|
||||
|
||||
#define OTGMODE_HNP_SRP_OTG 0
|
||||
#define OTGMODE_SRP_ONLY_OTG 1
|
||||
#define OTGMODE_NO_HNP_SRP_OTG 2
|
||||
#define OTGMODE_SRP_CAPABLE_DEVICE 3
|
||||
#define OTGMODE_NO_SRP_CAPABLE_DEVICE 4
|
||||
#define OTGMODE_SRP_CAPABLE_HOST 5
|
||||
#define OTGMODE_NO_SRP_CAPABLE_HOST 6
|
||||
|
||||
#define HSPHYTYPE_UTMI 1
|
||||
#define HSPHYTYPE_ULPI 2
|
||||
#define HSPHYTYPE_UTMI_ULPI 3
|
||||
|
||||
/* Core HW Config3 Register */
|
||||
#define GHWCFG3_DFIFODEPTH_SHIFT 16
|
||||
#define GHWCFG3_DFIFODEPTH_MASK 0xffff0000
|
||||
#define GHWCFG3_DFIFODEPTH_GET(x) ((x) >> 16)
|
||||
#define GHWCFG3_RSTTYPE (1<<11)
|
||||
#define GHWCFG3_OPTFEATURE (1<<10)
|
||||
#define GHWCFG3_VNDCTLSUPT (1<<9)
|
||||
#define GHWCFG3_I2CINTSEL (1<<8)
|
||||
#define GHWCFG3_OTGEN (1<<7)
|
||||
#define GHWCFG3_PKTSIZEWIDTH_SHIFT 4
|
||||
#define GHWCFG3_PKTSIZEWIDTH_MASK 0x00000070
|
||||
#define GHWCFG3_PKTSIZE_GET(x) (0x10<<(((x) >> 4) & 7))
|
||||
#define GHWCFG3_XFERSIZEWIDTH_SHIFT 0
|
||||
#define GHWCFG3_XFERSIZEWIDTH_MASK 0x0000000f
|
||||
#define GHWCFG3_XFRRSIZE_GET(x) (0x400<<(((x) >> 0) & 15))
|
||||
|
||||
/* Core HW Config4 Register */
|
||||
#define GHWCFG4_NUM_IN_EP_GET(x) ((((x) >> 26) & 15) + 1)
|
||||
#define GHWCFG4_SESSENDFLTR (1<<24)
|
||||
#define GHWCFG4_BVALIDFLTR (1<<23)
|
||||
#define GHWCFG4_AVALIDFLTR (1<<22)
|
||||
#define GHWCFG4_VBUSVALIDFLTR (1<<21)
|
||||
#define GHWCFG4_IDDGFLTR (1<<20)
|
||||
#define GHWCFG4_NUMCTLEPS_SHIFT 16
|
||||
#define GHWCFG4_NUMCTLEPS_MASK 0x000f0000
|
||||
#define GHWCFG4_NUMCTLEPS_GET(x) (((x) >> 16) & 15)
|
||||
#define GHWCFG4_PHYDATAWIDTH_SHIFT 14
|
||||
#define GHWCFG4_PHYDATAWIDTH_MASK 0x0000c000
|
||||
#define GHWCFG4_AHBFREQ (1<<5)
|
||||
#define GHWCFG4_ENABLEPWROPT (1<<4)
|
||||
#define GHWCFG4_NUMDEVPERIOEPS_SHIFT 0
|
||||
#define GHWCFG4_NUMDEVPERIOEPS_MASK 0x0000000f
|
||||
#define GHWCFG4_NUMDEVPERIOEPS_GET(x) (((x) >> 0) & 15)
|
||||
|
||||
/* Core LPM Configuration Register */
|
||||
#define GLPMCFG_HSIC_CONN (1<<30)
|
||||
|
||||
/* Host Periodic Transmit FIFO Size Register */
|
||||
#define HPTXFSIZ_PTXFSIZE_SHIFT 16
|
||||
#define HPTXFSIZ_PTXFSIZE_MASK 0xffff0000
|
||||
#define HPTXFSIZ_PTXFSTADDR_SHIFT 0
|
||||
#define HPTXFSIZ_PTXFSTADDR_MASK 0x0000ffff
|
||||
|
||||
/* Device Periodic Transmit FIFO#n Size Register */
|
||||
#define DPTXFSIZN_DPTXFSIZE_SHIFT 16
|
||||
#define DPTXFSIZN_DPTXFSIZE_MASK 0xffff0000
|
||||
#define DPTXFSIZN_PTXFSTADDR_SHIFT 0
|
||||
#define DPTXFSIZN_PTXFSTADDR_MASK 0x0000ffff
|
||||
|
||||
/* Device Transmit FIFO#n Register */
|
||||
#define DIEPTXFN_INEPNTXFDEP_SHIFT 16
|
||||
#define DIEPTXFN_INEPNTXFDEP_MASK 0xffff0000
|
||||
#define DIEPTXFN_INEPNTXFSTADDR_SHIFT 0
|
||||
#define DIEPTXFN_INEPNTXFSTADDR_MASK 0x0000ffff
|
||||
|
||||
/* Host Configuration Register */
|
||||
#define HCFG_MODECHANGERDY (1<<31)
|
||||
#define HCFG_PERSCHEDENABLE (1<<26)
|
||||
#define HCFG_FLENTRIES_SHIFT 24
|
||||
#define HCFG_FLENTRIES_MASK 0x03000000
|
||||
#define HCFG_FLENTRIES_8 (0)
|
||||
#define HCFG_FLENTRIES_16 (1)
|
||||
#define HCFG_FLENTRIES_32 (2)
|
||||
#define HCFG_FLENTRIES_64 (3)
|
||||
#define HCFG_MULTISEGDMA (1<<23)
|
||||
#define HCFG_32KHZSUSPEND (1<<7)
|
||||
#define HCFG_FSLSSUPP (1<<2)
|
||||
#define HCFG_FSLSPCLKSEL_SHIFT 0
|
||||
#define HCFG_FSLSPCLKSEL_MASK 0x00000003
|
||||
|
||||
/* Host Frame Interval Register */
|
||||
#define HFIR_RELOADCTRL (1<<16)
|
||||
#define HFIR_FRINT_SHIFT 0
|
||||
#define HFIR_FRINT_MASK 0x0000ffff
|
||||
|
||||
/* Host Frame Number / Frame Remaining Register */
|
||||
#define HFNUM_FRREM_SHIFT 16
|
||||
#define HFNUM_FRREM_MASK 0xffff0000
|
||||
#define HFNUM_FRNUM_SHIFT 0
|
||||
#define HFNUM_FRNUM_MASK 0x0000ffff
|
||||
|
||||
/* Host Periodic Transmit FIFO / Queue Status Register */
|
||||
#define HPTXSTS_ODD (1<<31)
|
||||
#define HPTXSTS_CHAN_SHIFT 27
|
||||
#define HPTXSTS_CHAN_MASK 0x78000000
|
||||
#define HPTXSTS_TOKEN_SHIFT 25
|
||||
#define HPTXSTS_TOKEN_MASK 0x06000000
|
||||
#define HPTXSTS_TOKEN_ZL 0
|
||||
#define HPTXSTS_TOKEN_PING 1
|
||||
#define HPTXSTS_TOKEN_DISABLE 2
|
||||
#define HPTXSTS_TERMINATE (1<<24)
|
||||
#define HPTXSTS_PTXQSPCAVAIL_SHIFT 16
|
||||
#define HPTXSTS_PTXQSPCAVAIL_MASK 0x00ff0000
|
||||
#define HPTXSTS_PTXFSPCAVAIL_SHIFT 0
|
||||
#define HPTXSTS_PTXFSPCAVAIL_MASK 0x0000ffff
|
||||
|
||||
/* Host All Channels Interrupt Register */
|
||||
#define HAINT_HAINT_SHIFT 0
|
||||
#define HAINT_HAINT_MASK 0x0000ffff
|
||||
|
||||
/* Host All Channels Interrupt Mask Register */
|
||||
#define HAINTMSK_HAINTMSK_SHIFT 0
|
||||
#define HAINTMSK_HAINTMSK_MASK 0x0000ffff
|
||||
|
||||
/* Host Port Control and Status Rgeister */
|
||||
#define HPRT_PRTSPD_SHIFT 17
|
||||
#define HPRT_PRTSPD_MASK 0x00060000
|
||||
#define HPRT_PRTSPD_HIGH 0
|
||||
#define HPRT_PRTSPD_FULL 1
|
||||
#define HPRT_PRTSPD_LOW 2
|
||||
#define HPRT_PRTSPD_MASK 0x00060000
|
||||
#define HPRT_PRTTSTCTL_SHIFT 13
|
||||
#define HPRT_PRTTSTCTL_MASK 0x0001e000
|
||||
#define HPRT_PRTPWR (1<<12)
|
||||
#define HPRT_PRTLNSTS_SHIFT 10
|
||||
#define HPRT_PRTLNSTS_MASK 0x00000c00
|
||||
#define HPRT_PRTRST (1<<8)
|
||||
#define HPRT_PRTSUSP (1<<7)
|
||||
#define HPRT_PRTRES (1<<6)
|
||||
#define HPRT_PRTOVRCURRCHNG (1<<5)
|
||||
#define HPRT_PRTOVRCURRACT (1<<4)
|
||||
#define HPRT_PRTENCHNG (1<<3)
|
||||
#define HPRT_PRTENA (1<<2)
|
||||
#define HPRT_PRTCONNDET (1<<1)
|
||||
#define HPRT_PRTCONNSTS (1<<0)
|
||||
|
||||
/* Host Channel 0 Characteristic Register */
|
||||
#define HCCHAR_CHENA (1<<31)
|
||||
#define HCCHAR_CHDIS (1<<30)
|
||||
#define HCCHAR_ODDFRM (1<<29)
|
||||
#define HCCHAR_DEVADDR_SHIFT 22
|
||||
#define HCCHAR_DEVADDR_MASK 0x1fc00000
|
||||
#define HCCHAR_MC_SHIFT 20
|
||||
#define HCCHAR_MC_MASK 0x00300000
|
||||
#define HCCHAR_EPTYPE_SHIFT 18
|
||||
#define HCCHAR_EPTYPE_MASK 0x000c0000
|
||||
#define HCCHAR_LSPDDEV (1<<17)
|
||||
#define HCCHAR_EPDIR (1<<15)
|
||||
#define HCCHAR_EPDIR_IN (1<<15)
|
||||
#define HCCHAR_EPDIR_OUT 0
|
||||
#define HCCHAR_EPNUM_SHIFT 11
|
||||
#define HCCHAR_EPNUM_MASK 0x00007800
|
||||
#define HCCHAR_MPS_SHIFT 0
|
||||
#define HCCHAR_MPS_MASK 0x000007ff
|
||||
|
||||
/* Host Channel 0 Split Control Register */
|
||||
#define HCSPLT_SPLTENA (1<<31)
|
||||
#define HCSPLT_COMPSPLT (1<<16)
|
||||
#define HCSPLT_XACTPOS_SHIFT 14
|
||||
#define HCSPLT_XACTPOS_MASK 0x0000c000
|
||||
#define HCSPLT_HUBADDR_SHIFT 7
|
||||
#define HCSPLT_HUBADDR_MASK 0x00003f80
|
||||
#define HCSPLT_PRTADDR_SHIFT 0
|
||||
#define HCSPLT_PRTADDR_MASK 0x0000007f
|
||||
|
||||
#define HCINT_ERRORS \
|
||||
(HCINT_BBLERR | HCINT_XACTERR)
|
||||
#define HCINT_RETRY \
|
||||
(HCINT_DATATGLERR | HCINT_FRMOVRUN | HCINT_NAK)
|
||||
|
||||
/* Host Channel 0 Interrupt Register */
|
||||
#define HCINT_SOFTWARE_ONLY (1<<20) /* BSD only */
|
||||
#define HCINT_DATATGLERR (1<<10)
|
||||
#define HCINT_FRMOVRUN (1<<9)
|
||||
#define HCINT_BBLERR (1<<8)
|
||||
#define HCINT_XACTERR (1<<7)
|
||||
#define HCINT_NYET (1<<6)
|
||||
#define HCINT_ACK (1<<5)
|
||||
#define HCINT_NAK (1<<4)
|
||||
#define HCINT_STALL (1<<3)
|
||||
#define HCINT_AHBERR (1<<2)
|
||||
#define HCINT_CHHLTD (1<<1)
|
||||
#define HCINT_XFERCOMPL (1<<0)
|
||||
|
||||
/* Host Channel 0 Interrupt Mask Register */
|
||||
#define HCINTMSK_DATATGLERRMSK (1<<10)
|
||||
#define HCINTMSK_FRMOVRUNMSK (1<<9)
|
||||
#define HCINTMSK_BBLERRMSK (1<<8)
|
||||
#define HCINTMSK_XACTERRMSK (1<<7)
|
||||
#define HCINTMSK_NYETMSK (1<<6)
|
||||
#define HCINTMSK_ACKMSK (1<<5)
|
||||
#define HCINTMSK_NAKMSK (1<<4)
|
||||
#define HCINTMSK_STALLMSK (1<<3)
|
||||
#define HCINTMSK_AHBERRMSK (1<<2)
|
||||
#define HCINTMSK_CHHLTDMSK (1<<1)
|
||||
#define HCINTMSK_XFERCOMPLMSK (1<<0)
|
||||
|
||||
/* Host Channel 0 Transfer Size Register */
|
||||
#define HCTSIZ_DOPNG (1<<31)
|
||||
#define HCTSIZ_PID_SHIFT 29
|
||||
#define HCTSIZ_PID_MASK 0x60000000
|
||||
#define HCTSIZ_PID_DATA0 0
|
||||
#define HCTSIZ_PID_DATA2 1
|
||||
#define HCTSIZ_PID_DATA1 2
|
||||
#define HCTSIZ_PID_MDATA 3
|
||||
#define HCTSIZ_PID_SETUP 3
|
||||
#define HCTSIZ_PKTCNT_SHIFT 19
|
||||
#define HCTSIZ_PKTCNT_MASK 0x1ff80000
|
||||
#define HCTSIZ_XFERSIZE_SHIFT 0
|
||||
#define HCTSIZ_XFERSIZE_MASK 0x0007ffff
|
||||
#define HCTSIZ_NTD_SHIFT 8
|
||||
#define HCTSIZ_NTD_MASK 0x0000ff00
|
||||
#define HCTSIZ_SCHINFO_SHIFT 0
|
||||
#define HCTSIZ_SCHINFO_MASK 0x000000ff
|
||||
|
||||
/* Device Configuration Register */
|
||||
#define DCFG_EPMISCNT_SHIFT 18
|
||||
#define DCFG_EPMISCNT_MASK 0x007c0000
|
||||
#define DCFG_PERFRINT_SHIFT 11
|
||||
#define DCFG_PERFRINT_MASK 0x00001800
|
||||
#define DCFG_DEVADDR_SHIFT 4
|
||||
#define DCFG_DEVADDR_MASK 0x000007f0
|
||||
#define DCFG_DEVADDR_SET(x) (((x) & 0x7F) << 4)
|
||||
#define DCFG_NZSTSOUTHSHK (1<<2)
|
||||
#define DCFG_DEVSPD_SHIFT 0
|
||||
#define DCFG_DEVSPD_MASK 0x00000003
|
||||
#define DCFG_DEVSPD_SET(x) ((x) & 0x3)
|
||||
#define DCFG_DEVSPD_HI 0
|
||||
#define DCFG_DEVSPD_FULL20 1
|
||||
#define DCFG_DEVSPD_FULL10 3
|
||||
|
||||
/* Device Control Register */
|
||||
#define DCTL_PWRONPRGDONE (1<<11)
|
||||
#define DCTL_CGOUTNAK (1<<10)
|
||||
#define DCTL_SGOUTNAK (1<<9)
|
||||
#define DCTL_CGNPINNAK (1<<8)
|
||||
#define DCTL_SGNPINNAK (1<<7)
|
||||
#define DCTL_TSTCTL_SHIFT 4
|
||||
#define DCTL_TSTCTL_MASK 0x00000070
|
||||
#define DCTL_GOUTNAKSTS (1<<3)
|
||||
#define DCTL_GNPINNAKSTS (1<<2)
|
||||
#define DCTL_SFTDISCON (1<<1)
|
||||
#define DCTL_RMTWKUPSIG (1<<0)
|
||||
|
||||
/* Device Status Register */
|
||||
#define DSTS_SOFFN_SHIFT 8
|
||||
#define DSTS_SOFFN_MASK 0x003fff00
|
||||
#define DSTS_SOFFN_GET(x) (((x) >> 8) & 0x3FFF)
|
||||
#define DSTS_ERRTICERR (1<<3)
|
||||
#define DSTS_ENUMSPD_SHIFT 1
|
||||
#define DSTS_ENUMSPD_MASK 0x00000006
|
||||
#define DSTS_ENUMSPD_GET(x) (((x) >> 1) & 3)
|
||||
#define DSTS_ENUMSPD_HI 0
|
||||
#define DSTS_ENUMSPD_FULL20 1
|
||||
#define DSTS_ENUMSPD_LOW10 2
|
||||
#define DSTS_ENUMSPD_FULL10 3
|
||||
#define DSTS_SUSPSTS (1<<0)
|
||||
|
||||
/* Device IN EP Common Mask Register */
|
||||
#define DIEPMSK_TXFIFOUNDRNMSK (1<<8)
|
||||
#define DIEPMSK_INEPNAKEFFMSK (1<<6)
|
||||
#define DIEPMSK_INTKNEPMISMSK (1<<5)
|
||||
#define DIEPMSK_INTKNTXFEMPMSK (1<<4)
|
||||
#define DIEPMSK_FIFOEMPTY (1<<4)
|
||||
#define DIEPMSK_TIMEOUTMSK (1<<3)
|
||||
#define DIEPMSK_AHBERRMSK (1<<2)
|
||||
#define DIEPMSK_EPDISBLDMSK (1<<1)
|
||||
#define DIEPMSK_XFERCOMPLMSK (1<<0)
|
||||
|
||||
/* Device OUT EP Common Mask Register */
|
||||
#define DOEPMSK_OUTPKTERRMSK (1<<8)
|
||||
#define DOEPMSK_BACK2BACKSETUP (1<<6)
|
||||
#define DOEPMSK_OUTTKNEPDISMSK (1<<4)
|
||||
#define DOEPMSK_FIFOEMPTY (1<<4)
|
||||
#define DOEPMSK_SETUPMSK (1<<3)
|
||||
#define DOEPMSK_AHBERRMSK (1<<2)
|
||||
#define DOEPMSK_EPDISBLDMSK (1<<1)
|
||||
#define DOEPMSK_XFERCOMPLMSK (1<<0)
|
||||
|
||||
/* Device IN EP Interrupt Register */
|
||||
#define DIEPINT_TXFIFOUNDRN (1<<8)
|
||||
#define DIEPINT_INEPNAKEFF (1<<6)
|
||||
#define DIEPINT_INTKNEPMIS (1<<5)
|
||||
#define DIEPINT_INTKNTXFEMP (1<<4)
|
||||
#define DIEPINT_TIMEOUT (1<<3)
|
||||
#define DIEPINT_AHBERR (1<<2)
|
||||
#define DIEPINT_EPDISBLD (1<<1)
|
||||
#define DIEPINT_XFERCOMPL (1<<0)
|
||||
|
||||
/* Device OUT EP Interrupt Register */
|
||||
#define DOEPINT_OUTPKTERR (1<<8)
|
||||
#define DOEPINT_BACK2BACKSETUP (1<<6)
|
||||
#define DOEPINT_OUTTKNEPDIS (1<<4)
|
||||
#define DOEPINT_SETUP (1<<3)
|
||||
#define DOEPINT_AHBERR (1<<2)
|
||||
#define DOEPINT_EPDISBLD (1<<1)
|
||||
#define DOEPINT_XFERCOMPL (1<<0)
|
||||
|
||||
/* Device All EP Interrupt Register */
|
||||
#define DAINT_INEPINT_MASK 0xffff0000
|
||||
#define DAINT_INEPINT_SHIFT 0
|
||||
#define DAINT_OUTEPINT_MASK 0x0000ffff
|
||||
#define DAINT_OUTEPINT_SHIFT 16
|
||||
|
||||
/* Device All EP Interrupt Mask Register */
|
||||
#define DAINTMSK_INEPINT_MASK 0xffff0000
|
||||
#define DAINTMSK_INEPINT_SHIFT 0
|
||||
#define DAINTMSK_OUTEPINT_MASK 0x0000ffff
|
||||
#define DAINTMSK_OUTEPINT_SHIFT 16
|
||||
|
||||
/* Device IN Token Queue Read Register 1 */
|
||||
#define DTKNQR1_EPTKN_SHIFT 8
|
||||
#define DTKNQR1_EPTKN_MASK 0xffffff00
|
||||
#define DTKNQR1_WRAPBIT (1<<7)
|
||||
#define DTKNQR1_INTKNWPTR_SHIFT 0
|
||||
#define DTKNQR1_INTKNWPTR_MASK 0x0000001f
|
||||
|
||||
/* Device VBUS Discharge Register */
|
||||
#define DVBUSDIS_DVBUSDIS_SHIFT 0
|
||||
#define DVBUSDIS_DVBUSDIS_MASK 0x0000ffff
|
||||
|
||||
/* Device VBUS Pulse Register */
|
||||
#define DVBUSPULSE_DVBUSPULSE_SHIFT 0
|
||||
#define DVBUSPULSE_DVBUSPULSE_MASK 0x00000fff
|
||||
|
||||
/* Device Tresholding Control Register */
|
||||
#define DTHRCTL_ARBPRKEN (1<<27)
|
||||
#define DTHRCTL_RXTHRLEN_SHIFT 17
|
||||
#define DTHRCTL_RXTHRLEN_MASK 0x03fe0000
|
||||
#define DTHRCTL_RXTHREN (1<<16)
|
||||
#define DTHRCTL_TXTHRLEN_SHIFT 2
|
||||
#define DTHRCTL_TXTHRLEN_MASK 0x000007fc
|
||||
#define DTHRCTL_ISOTHREN (1<<1)
|
||||
#define DTHRCTL_NONISOTHREN (1<<0)
|
||||
|
||||
/* Device IN EPs Empty Interrupt Mask Register */
|
||||
#define DIEPEMPMSK_INEPTXFEMPMSK_SHIFT 0
|
||||
#define DIEPEMPMSK_INEPTXFEMPMSK_MASK 0x0000ffff
|
||||
|
||||
/* Device IN Endpoint Control Register */
|
||||
#define DIEPCTL_EPENA (1<<31)
|
||||
#define DIEPCTL_EPDIS (1<<30)
|
||||
#define DIEPCTL_SETD1PID (1<<29)
|
||||
#define DIEPCTL_SETD0PID (1<<28)
|
||||
#define DIEPCTL_SNAK (1<<27)
|
||||
#define DIEPCTL_CNAK (1<<26)
|
||||
#define DIEPCTL_TXFNUM_SHIFT 22
|
||||
#define DIEPCTL_TXFNUM_MASK 0x03c00000
|
||||
#define DIEPCTL_TXFNUM_SET(n) (((n) & 15) << 22)
|
||||
#define DIEPCTL_STALL (1<<21)
|
||||
#define DIEPCTL_EPTYPE_SHIFT 18
|
||||
#define DIEPCTL_EPTYPE_MASK 0x000c0000
|
||||
#define DIEPCTL_EPTYPE_SET(n) (((n) & 3) << 18)
|
||||
#define DIEPCTL_EPTYPE_CONTROL 0
|
||||
#define DIEPCTL_EPTYPE_ISOC 1
|
||||
#define DIEPCTL_EPTYPE_BULK 2
|
||||
#define DIEPCTL_EPTYPE_INTERRUPT 3
|
||||
#define DIEPCTL_NAKSTS (1<<17)
|
||||
#define DIEPCTL_USBACTEP (1<<15)
|
||||
#define DIEPCTL_NEXTEP_SHIFT 11
|
||||
#define DIEPCTL_NEXTEP_MASK 0x00007800
|
||||
#define DIEPCTL_MPS_SHIFT 0
|
||||
#define DIEPCTL_MPS_MASK 0x000007ff
|
||||
#define DIEPCTL_MPS_SET(n) ((n) & 0x7FF)
|
||||
#define DIEPCTL_MPS_64 (0<<0)
|
||||
#define DIEPCTL_MPS_32 (1<<0)
|
||||
#define DIEPCTL_MPS_16 (2<<0)
|
||||
#define DIEPCTL_MPS_8 (3<<0)
|
||||
|
||||
/* Device OUT Endpoint Control Register */
|
||||
#define DOEPCTL_EPENA (1<<31)
|
||||
#define DOEPCTL_EPDIS (1<<30)
|
||||
#define DOEPCTL_SETD1PID (1<<29)
|
||||
#define DOEPCTL_SETD0PID (1<<28)
|
||||
#define DOEPCTL_SNAK (1<<27)
|
||||
#define DOEPCTL_CNAK (1<<26)
|
||||
#define DOEPCTL_FNUM_SET(n) (((n) & 15) << 22)
|
||||
#define DOEPCTL_STALL (1<<21)
|
||||
#define DOEPCTL_EPTYPE_SHIFT 18
|
||||
#define DOEPCTL_EPTYPE_MASK 0x000c0000
|
||||
#define DOEPCTL_EPTYPE_SET(n) (((n) & 3) << 18)
|
||||
#define DOEPCTL_NAKSTS (1<<17)
|
||||
#define DOEPCTL_USBACTEP (1<<15)
|
||||
#define DOEPCTL_MPS_SHIFT 0
|
||||
#define DOEPCTL_MPS_MASK 0x000007ff
|
||||
#define DOEPCTL_MPS_SET(n) ((n) & 0x7FF)
|
||||
#define DOEPCTL_MPS_64 (0<<0)
|
||||
#define DOEPCTL_MPS_32 (1<<0)
|
||||
#define DOEPCTL_MPS_16 (2<<0)
|
||||
#define DOEPCTL_MPS_8 (3<<0)
|
||||
|
||||
/* common bits for DIEPCTL and DOEPCTL */
|
||||
#define DXEPINT_TXFEMP (1<<7)
|
||||
#define DXEPINT_SETUP (1<<3)
|
||||
#define DXEPINT_XFER_COMPL (1<<0)
|
||||
|
||||
/* Device IN Endpoint Transfer Size Register */
|
||||
#define DIEPTSIZ_XFERSIZE_MASK 0x0007ffff
|
||||
#define DIEPTSIZ_XFERSIZE_SHIFT 0
|
||||
#define DIEPTSIZ_PKTCNT_MASK 0x1ff80000
|
||||
#define DIEPTSIZ_PKTCNT_SHIFT 19
|
||||
#define DIEPTSIZ_MC_MASK 0x60000000
|
||||
#define DIEPTSIZ_MC_SHIFT 29
|
||||
|
||||
/* Device OUT Endpoint Transfer Size Register */
|
||||
#define DOEPTSIZ_XFERSIZE_MASK 0x0007ffff
|
||||
#define DOEPTSIZ_XFERSIZE_SHIFT 0
|
||||
#define DOEPTSIZ_PKTCNT_MASK 0x1ff80000
|
||||
#define DOEPTSIZ_PKTCNT_SHIFT 19
|
||||
#define DOEPTSIZ_MC_MASK 0x60000000
|
||||
#define DOEPTSIZ_MC_SHIFT 29
|
||||
|
||||
/* common bits for DIEPTSIZ and DOEPTSIZ */
|
||||
#define DXEPTSIZ_SET_MULTI(n) (((n) & 3) << 29)
|
||||
#define DXEPTSIZ_SET_NPKT(n) (((n) & 0x3FF) << 19)
|
||||
#define DXEPTSIZ_GET_NPKT(n) (((n) >> 19) & 0x3FF)
|
||||
#define DXEPTSIZ_SET_NBYTES(n) (((n) & 0x7FFFFF) << 0)
|
||||
#define DXEPTSIZ_GET_NBYTES(n) (((n) >> 0) & 0x7FFFFF)
|
||||
|
||||
/* Power and clock gating CSR */
|
||||
#define PCGCCTL_DEEP_SLEEP (1<<7)
|
||||
#define PCGCCTL_PHY_IN_SLEEP (1<<6)
|
||||
#define PCGCCTL_ENBL_SLEEP_GATING (1<<5)
|
||||
#define PCGCCTL_PHYSUSPEND (1<<4)
|
||||
#define PCGCCTL_RSTPDWNMODULE (1<<3)
|
||||
#define PCGCCTL_PWRCLMP (1<<2)
|
||||
#define PCGCCTL_GATEHCLK (1<<1)
|
||||
#define PCGCCTL_STOPPCLK (1<<0)
|
||||
|
||||
/*****************************************************************/
|
||||
|
||||
struct dotg_host_dma_desc {
|
||||
uint32_t status;
|
||||
uint32_t buffer;
|
||||
} dotg_host_dma_desc_t;
|
||||
|
||||
/* DMA Status quadlet */
|
||||
/* for non-isochronous transfers */
|
||||
#define HDDS_BYTES(x) ((x) & 0x0001ffff)
|
||||
#define HDDS_OFFSET(x) ((x) & 0x007e0000)
|
||||
#define HDDS_GET_OFFSET(x) (HDDS_GET_OFFSET(x) >> 17)
|
||||
#define HDDS_QTD (1<<23)
|
||||
#define HDDS_SUP (1<<24)
|
||||
|
||||
/* for isochronous transfers */
|
||||
#define HDDS_IBYTES(x) ((x) & 0x00000fff)
|
||||
|
||||
#define HDDS_IOC (1<<25)
|
||||
#define HDDS_EOL (1<<26)
|
||||
#define HDDS_STS(x) (((x) & 3) << 28)
|
||||
#define HDDS_A (1<<31)
|
||||
|
||||
struct dotg_dev_dma_desc {
|
||||
uint32_t status;
|
||||
uint32_t buffer;
|
||||
} dotg_dev_dma_desc_t;
|
||||
|
||||
/* DMA Status quadlet */
|
||||
/* for non-isochronous transfers */
|
||||
#define DDDS_BYTES(x) ((x) & 0xffff)
|
||||
#define DDDS_MTRF (1<<23)
|
||||
#define DDDS_SR (1<<24)
|
||||
|
||||
/* for isochronous transfers */
|
||||
#define DDDS_RXBYTES(x) ((x) & 0x000007ff)
|
||||
#define DDDS_TXBYTES(x) ((x) & 0x00000fff)
|
||||
#define DDDS_FRAMENUM(x) ((x) & 0x007ff000)
|
||||
#define DDDS_GET_FRAMENUM(x) (DDDS_FRAMENUM(x) >> 12)
|
||||
#define DDDS_PID(x) ((x) & 0x01800000)
|
||||
#define DDDS_GET_PID(x) (DDDS_PID(x) >> 23)
|
||||
|
||||
#define DDDS_IOC (1<<25)
|
||||
#define DDDS_SP (1<<26)
|
||||
#define DDDS_L (1<<27)
|
||||
#define DDDS_STS(x) (((x) & 3) << 28)
|
||||
#define DDDS_BS(x) (((x) & 3) << 30)
|
||||
|
||||
#define STS_SUCCESS 0
|
||||
#define STS_BUFFLUSH 1
|
||||
#define STS_BUFERR 3
|
||||
|
||||
#define BS_HOST_READY 0
|
||||
#define BS_DMA_BUSY 1
|
||||
#define BS_DMA_DONE 2
|
||||
#define BS_HOST_BUSY 3
|
||||
|
||||
#endif /* _DWC_OTGREG_H_ */
|
||||
250
sys/dev/usb/dwc_otgvar.h
Normal file
250
sys/dev/usb/dwc_otgvar.h
Normal file
@ -0,0 +1,250 @@
|
||||
/* $NetBSD: dwc_otgvar.h,v 1.1 2013/01/09 22:23:44 skrll Exp $ */
|
||||
|
||||
/* $FreeBSD: src/sys/dev/usb/controller/dwc_otg.h,v 1.12 2012/09/27 15:23:38 hselasky Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2012 Hans Petter Selasky. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DWC_OTGVAR_H_
|
||||
#define _DWC_OTGVAR_H_
|
||||
|
||||
#include <sys/pool.h>
|
||||
#include <sys/workqueue.h>
|
||||
|
||||
#define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32)
|
||||
#define DWC_OTG_FRAME_MASK 0x7FF
|
||||
#define DWC_OTG_MAX_TXP 4
|
||||
#define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP)
|
||||
#define DWC_OTG_MAX_CHANNELS 16
|
||||
#define DWC_OTG_MAX_ENDPOINTS 16
|
||||
#define DWC_OTG_HOST_TIMER_RATE 10 /* ms */
|
||||
|
||||
#define DWC_OTG_POOL_SIZE 4096 /* XXXNH measure */
|
||||
|
||||
struct dwc_otg_td;
|
||||
|
||||
typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_td *td);
|
||||
|
||||
typedef struct dwc_otg_td {
|
||||
struct dwc_otg_td *obj_next;
|
||||
dwc_otg_cmd_t *func;
|
||||
usbd_xfer_handle xfer;
|
||||
void *buf;
|
||||
uint32_t actlen;
|
||||
uint32_t tx_bytes;
|
||||
uint32_t offset;
|
||||
uint32_t remainder;
|
||||
uint32_t hcchar; /* HOST CFG */
|
||||
uint32_t hcsplt; /* HOST CFG */
|
||||
uint16_t max_packet_size; /* packet_size */
|
||||
uint16_t npkt;
|
||||
uint8_t errcnt;
|
||||
uint8_t retrycnt;
|
||||
uint8_t tmr_res;
|
||||
uint8_t tmr_val;
|
||||
uint8_t curr_frame;
|
||||
uint8_t ep_no;
|
||||
uint8_t channel;
|
||||
uint8_t state;
|
||||
#define DWC_CHAN_ST_START 0
|
||||
#define DWC_CHAN_ST_WAIT_ANE 1
|
||||
#define DWC_CHAN_ST_WAIT_S_ANE 2
|
||||
#define DWC_CHAN_ST_WAIT_C_ANE 3
|
||||
#define DWC_CHAN_ST_RX_PKT 4
|
||||
#define DWC_CHAN_ST_RX_SPKT 5
|
||||
#define DWC_CHAN_ST_RX_SPKT_SYNC 6
|
||||
#define DWC_CHAN_ST_TX_PKT 4
|
||||
#define DWC_CHAN_ST_TX_CPKT 5
|
||||
#define DWC_CHAN_ST_TX_PKT_SYNC 6
|
||||
uint8_t error:1;
|
||||
uint8_t error_any:1;
|
||||
uint8_t error_stall:1;
|
||||
uint8_t alt_next:1;
|
||||
uint8_t short_pkt:1;
|
||||
uint8_t did_stall:1;
|
||||
uint8_t toggle:1;
|
||||
uint8_t set_toggle:1;
|
||||
uint8_t got_short:1;
|
||||
uint8_t did_nak:1;
|
||||
} dwc_otg_td_t;
|
||||
|
||||
|
||||
struct dwc_otg_std_temp {
|
||||
dwc_otg_cmd_t *func;
|
||||
usbd_xfer_handle xfer;
|
||||
void *buf;
|
||||
struct dwc_otg_td *td;
|
||||
struct dwc_otg_td *td_next;
|
||||
uint32_t len;
|
||||
uint32_t offset;
|
||||
uint16_t max_frame_size;
|
||||
uint8_t short_pkt;
|
||||
|
||||
/*
|
||||
* short_pkt = 0: transfer should be short terminated
|
||||
* short_pkt = 1: transfer should not be short terminated
|
||||
*/
|
||||
uint8_t setup_alt_next;
|
||||
uint8_t did_stall;
|
||||
uint8_t bulk_or_control;
|
||||
};
|
||||
|
||||
struct dwc_otg_flags {
|
||||
uint8_t change_connect:1;
|
||||
uint8_t change_suspend:1;
|
||||
uint8_t change_reset:1;
|
||||
uint8_t change_enabled:1;
|
||||
uint8_t change_over_current:1;
|
||||
uint8_t status_suspend:1; /* set if suspended */
|
||||
uint8_t status_vbus:1; /* set if present */
|
||||
uint8_t status_bus_reset:1; /* set if reset complete */
|
||||
uint8_t status_high_speed:1; /* set if High Speed is selected */
|
||||
uint8_t status_low_speed:1; /* set if Low Speed is selected */
|
||||
uint8_t status_device_mode:1; /* set if device mode */
|
||||
uint8_t self_powered:1;
|
||||
uint8_t clocks_off:1;
|
||||
uint8_t port_powered:1;
|
||||
uint8_t port_enabled:1;
|
||||
uint8_t port_over_current:1;
|
||||
uint8_t d_pulled_up:1;
|
||||
};
|
||||
|
||||
#if 0
|
||||
typedef struct dwc_otg_soft_ed {
|
||||
} dwc_otg_soft_ed_t;
|
||||
|
||||
typedef struct dwc_otg_soft_td {
|
||||
dwc_otg_td_t *td;
|
||||
usb_dma_t dma;
|
||||
int offs;
|
||||
} dwc_otg_soft_td_t;
|
||||
#endif
|
||||
|
||||
struct dwc_otg_work {
|
||||
struct work wk;
|
||||
usbd_xfer_handle xfer;
|
||||
};
|
||||
|
||||
struct dwc_otg_xfer {
|
||||
struct usbd_xfer xfer; /* Needs to be first */
|
||||
struct usb_task abort_task;
|
||||
TAILQ_ENTRY(dwc_otg_xfer) xnext; /* list of active/complete xfers */
|
||||
bool queued;
|
||||
|
||||
void *td_start[1];
|
||||
dwc_otg_td_t *td_transfer_first;
|
||||
dwc_otg_td_t *td_transfer_last;
|
||||
dwc_otg_td_t *td_transfer_cache;
|
||||
|
||||
int toggle_next;
|
||||
|
||||
struct dwc_otg_work work;
|
||||
};
|
||||
|
||||
struct dwc_otg_chan_state {
|
||||
uint32_t hcint;
|
||||
uint8_t wait_sof;
|
||||
uint8_t allocated;
|
||||
uint8_t suspended;
|
||||
};
|
||||
|
||||
typedef struct dwc_otg_softc {
|
||||
device_t sc_dev;
|
||||
struct usbd_bus sc_bus;
|
||||
bus_space_tag_t sc_iot;
|
||||
bus_space_handle_t sc_ioh;
|
||||
bus_size_t sc_size;
|
||||
|
||||
kmutex_t sc_lock;
|
||||
kmutex_t sc_intr_lock;
|
||||
|
||||
void *sc_rhc_si;
|
||||
//void *sc_intr_si;
|
||||
|
||||
struct workqueue *sc_wq;
|
||||
struct dwc_otg_work sc_wk;
|
||||
|
||||
int sc_noport;
|
||||
|
||||
usbd_xfer_handle sc_intrxfer;
|
||||
|
||||
device_t sc_child; /* /dev/usb# device */
|
||||
char sc_dying;
|
||||
struct usb_dma_reserve sc_dma_reserve;
|
||||
|
||||
char sc_vendor[32]; /* vendor string for root hub */
|
||||
int sc_id_vendor; /* vendor ID for root hub */
|
||||
|
||||
TAILQ_HEAD(, dwc_otg_xfer) sc_active; /* active transfers */
|
||||
TAILQ_HEAD(, dwc_otg_xfer) sc_complete; /* complete transfers */
|
||||
|
||||
SIMPLEQ_HEAD(, usbd_xfer) sc_free_xfers; /* free xfers */
|
||||
|
||||
struct pool sc_tdpool;
|
||||
|
||||
/* From FreeBSD softc */
|
||||
struct callout sc_timer;
|
||||
void *sc_timer_si;
|
||||
|
||||
uint32_t sc_rx_bounce_buffer[1024 / 4];
|
||||
uint32_t sc_tx_bounce_buffer[(512 * DWC_OTG_MAX_TXP) / 4];
|
||||
|
||||
uint32_t sc_fifo_size;
|
||||
uint32_t sc_irq_mask;
|
||||
uint32_t sc_last_rx_status;
|
||||
#if 0
|
||||
uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS];
|
||||
uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS];
|
||||
#endif
|
||||
struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS];
|
||||
uint32_t sc_hprt_val;
|
||||
uint32_t sc_tmr_val; /* timer value */
|
||||
uint16_t sc_active_rx_ep;
|
||||
|
||||
uint8_t sc_timer_active;
|
||||
uint8_t sc_dev_ep_max;
|
||||
uint8_t sc_dev_in_ep_max;
|
||||
uint8_t sc_host_ch_max;
|
||||
|
||||
uint8_t sc_addr; /* device address */
|
||||
uint8_t sc_conf; /* device configuration */
|
||||
uint8_t sc_mode; /* mode of operation */
|
||||
#define DWC_MODE_OTG 0 /* both modes */
|
||||
#define DWC_MODE_DEVICE 1 /* device only */
|
||||
#define DWC_MODE_HOST 2 /* host only */
|
||||
|
||||
struct dwc_otg_flags sc_flags;
|
||||
|
||||
} dwc_otg_softc_t;
|
||||
|
||||
usbd_status dwc_otg_init(dwc_otg_softc_t *);
|
||||
int dwc_otg_intr(void *);
|
||||
int dwc_otg_detach(dwc_otg_softc_t *, int);
|
||||
bool dwc_otg_shutdown(device_t, int);
|
||||
void dwc_otg_childdet(device_t, device_t);
|
||||
int dwc_otg_activate(device_t, enum devact);
|
||||
bool dwc_otg_resume(device_t, const pmf_qual_t *);
|
||||
bool dwc_otg_suspend(device_t, const pmf_qual_t *);
|
||||
|
||||
#endif /* _DWC_OTGVAR_H_ */
|
||||
Loading…
Reference in New Issue
Block a user