Explicitly mark MCUCTL_ISP_OFFSET as an unknown module to prevent confusion
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@ -178,7 +178,7 @@
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#define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */
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#define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */
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#define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */
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#define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX micro controller control unit? */
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#define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* power module control unit? */
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#define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */
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#define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000
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#define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000
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@ -1,4 +1,4 @@
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/* $NetBSD: exynos5_reg.h,v 1.4 2014/05/21 13:02:46 reinoud Exp $ */
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/* $NetBSD: exynos5_reg.h,v 1.5 2014/06/03 15:51:59 reinoud Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -144,7 +144,7 @@
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#define EXYNOS5_USB2_DEVICE_LINK_OFFSET 0x02140000
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#define EXYNOS5_MIPI_HSI_OFFSET 0x02160000
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#define EXYNOS5_SATA PHY CONTROL_OFFSET 0x02170000
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#define EXYNOS5_MCUCTL_IOP_OFFSET 0x02180000
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#define EXYNOS5_MCUCTL_IOP_OFFSET 0x02180000 /* XXX unknown XXX */
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#define EXYNOS5_WDT_IOP_OFFSET 0x02190000
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#define EXYNOS5_PDMA0 0x021A0000
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#define EXYNOS5_PDMA1 0x021B0000
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