- rectify nonsense and bugs around statistics counter managment.
- scoop up counter values in one second interval comsolidating with phy_tick. - reformat register definitions for ease to see.
This commit is contained in:
nisimura
parent
7fafc0d589
commit
0a488c77af
@ -1,4 +1,4 @@
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/* $NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $ */
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/* $NetBSD: if_kse.c,v 1.56 2020/09/20 23:48:09 nisimura Exp $ */
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/*-
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* Copyright (c) 2006 The NetBSD Foundation, Inc.
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.56 2020/09/20 23:48:09 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -42,8 +42,9 @@ __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $")
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#include <sys/device.h>
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#include <sys/callout.h>
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#include <sys/ioctl.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/rndsource.h>
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#include <sys/errno.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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@ -71,36 +72,38 @@ __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $")
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#define CSR_WRITE_2(sc, off, val) \
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bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (off), (val))
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#define MDTXC 0x000 /* DMA transmit control */
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#define MDRXC 0x004 /* DMA receive control */
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#define MDTSC 0x008 /* DMA transmit start */
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#define MDRSC 0x00c /* DMA receive start */
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#define TDLB 0x010 /* transmit descriptor list base */
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#define RDLB 0x014 /* receive descriptor list base */
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#define MTR0 0x020 /* multicast table 31:0 */
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#define MTR1 0x024 /* multicast table 63:32 */
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#define INTEN 0x028 /* interrupt enable */
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#define INTST 0x02c /* interrupt status */
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#define MAAL0 0x080 /* additional MAC address 0 low */
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#define MAAH0 0x084 /* additional MAC address 0 high */
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#define MARL 0x200 /* MAC address low */
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#define MARM 0x202 /* MAC address middle */
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#define MARH 0x204 /* MAC address high */
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#define GRR 0x216 /* global reset */
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#define SIDER 0x400 /* switch ID and function enable */
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#define SGCR3 0x406 /* switch function control 3 */
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#define CR3_USEHDX (1U<<6) /* use half-duplex 8842 host port */
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#define CR3_USEFC (1U<<5) /* use flowcontrol 8842 host port */
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#define IACR 0x4a0 /* indirect access control */
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#define IADR1 0x4a2 /* indirect access data 66:63 */
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#define IADR2 0x4a4 /* indirect access data 47:32 */
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#define IADR3 0x4a6 /* indirect access data 63:48 */
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#define IADR4 0x4a8 /* indirect access data 15:0 */
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#define IADR5 0x4aa /* indirect access data 31:16 */
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#define P1CR4 0x512 /* port 1 control 4 */
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#define P1SR 0x514 /* port 1 status */
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#define P2CR4 0x532 /* port 2 control 4 */
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#define P2SR 0x534 /* port 2 status */
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#define MDTXC 0x000 /* DMA transmit control */
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#define MDRXC 0x004 /* DMA receive control */
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#define MDTSC 0x008 /* trigger DMA transmit (SC) */
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#define MDRSC 0x00c /* trigger DMA receive (SC) */
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#define TDLB 0x010 /* transmit descriptor list base */
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#define RDLB 0x014 /* receive descriptor list base */
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#define MTR0 0x020 /* multicast table 31:0 */
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#define MTR1 0x024 /* multicast table 63:32 */
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#define INTEN 0x028 /* interrupt enable */
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#define INTST 0x02c /* interrupt status */
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#define MAAL0 0x080 /* additional MAC address 0 low */
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#define MAAH0 0x084 /* additional MAC address 0 high */
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#define MARL 0x200 /* MAC address low */
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#define MARM 0x202 /* MAC address middle */
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#define MARH 0x204 /* MAC address high */
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#define GRR 0x216 /* global reset */
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#define SIDER 0x400 /* switch ID and function enable */
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#define SGCR3 0x406 /* switch function control 3 */
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#define CR3_USEHDX (1U<<6) /* use half-duplex 8842 host port */
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#define CR3_USEFC (1U<<5) /* use flowcontrol 8842 host port */
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#define IACR 0x4a0 /* indirect access control */
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#define IADR1 0x4a2 /* indirect access data 66:63 */
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#define IADR2 0x4a4 /* indirect access data 47:32 */
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#define IADR3 0x4a6 /* indirect access data 63:48 */
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#define IADR4 0x4a8 /* indirect access data 15:0 */
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#define IADR5 0x4aa /* indirect access data 31:16 */
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#define IADR_LATCH (1U<<30) /* latch completed indication */
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#define IADR_OVF (1U<<31) /* overflow detected */
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#define P1CR4 0x512 /* port 1 control 4 */
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#define P1SR 0x514 /* port 1 status */
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#define P2CR4 0x532 /* port 2 control 4 */
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#define P2SR 0x534 /* port 2 status */
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#define PxCR_STARTNEG (1U<<9) /* restart auto negotiation */
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#define PxCR_AUTOEN (1U<<7) /* auto negotiation enable */
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#define PxCR_SPD100 (1U<<6) /* force speed 100 */
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@ -112,9 +115,10 @@ __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $")
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#define PxSR_LINKUP (1U<<5) /* link is good */
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#define PxSR_RXFLOW (1U<<12) /* receive flow control active */
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#define PxSR_TXFLOW (1U<<11) /* transmit flow control active */
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#define P1VIDCR 0x504 /* port 1 vtag */
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#define P2VIDCR 0x524 /* port 2 vtag */
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#define P3VIDCR 0x544 /* 8842 host vtag */
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#define P1VIDCR 0x504 /* port 1 vtag */
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#define P2VIDCR 0x524 /* port 2 vtag */
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#define P3VIDCR 0x544 /* 8842 host vtag */
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#define EVCNTBR 0x1c00 /* 3 sets of 34 event counters */
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#define TXC_BS_MSK 0x3f000000 /* burst size */
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#define TXC_BS_SFT (24) /* 1,2,4,8,16,32 or 0 for unlimited */
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@ -147,6 +151,14 @@ __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $")
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#define INT_DMRBUS (1U<<27) /* Rx descriptor pool is full */
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#define INT_DMxPSS (3U<<25) /* 26:25 DMA Tx/Rx have stopped */
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struct tdes {
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uint32_t t0, t1, t2, t3;
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};
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struct rdes {
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uint32_t r0, r1, r2, r3;
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};
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#define T0_OWN (1U<<31) /* desc is ready to Tx */
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#define R0_OWN (1U<<31) /* desc is empty */
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@ -192,14 +204,6 @@ __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.55 2020/09/20 20:15:11 nisimura Exp $")
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#define KSE_NRXDESC_MASK (KSE_NRXDESC - 1)
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#define KSE_NEXTRX(x) (((x) + 1) & KSE_NRXDESC_MASK)
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struct tdes {
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uint32_t t0, t1, t2, t3;
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};
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struct rdes {
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uint32_t r0, r1, r2, r3;
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};
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struct kse_control_data {
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struct tdes kcd_txdescs[KSE_NTXDESC];
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struct rdes kcd_rxdescs[KSE_NRXDESC];
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@ -259,8 +263,9 @@ struct kse_softc {
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uint32_t sc_inten;
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uint32_t sc_chip;
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krndsource_t rnd_source; /* random source */
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#ifdef KSE_EVENT_COUNTERS
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callout_t sc_stat_ch; /* statistics counter callout */
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struct ksext {
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char evcntname[3][8];
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struct evcnt pev[3][34];
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@ -505,7 +510,6 @@ kse_attach(device_t parent, device_t self, void *aux)
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mii->mii_statchg = kse_mii_statchg;
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/* Initialize ifmedia structures. */
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sc->sc_flowflags = 0;
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if (sc->sc_chip == 0x8841) {
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/* use port 1 builtin PHY as index 1 device */
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sc->sc_ethercom.ec_mii = mii;
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@ -558,6 +562,8 @@ kse_attach(device_t parent, device_t self, void *aux)
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IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
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IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
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sc->sc_flowflags = 0;
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if_attach(ifp);
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if_deferred_start_init(ifp, NULL);
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ether_ifattach(ifp, enaddr);
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@ -565,83 +571,56 @@ kse_attach(device_t parent, device_t self, void *aux)
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callout_init(&sc->sc_tick_ch, 0);
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callout_setfunc(&sc->sc_tick_ch, phy_tick, sc);
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rnd_attach_source(&sc->rnd_source, device_xname(self),
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RND_TYPE_NET, RND_FLAG_DEFAULT);
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#ifdef KSE_EVENT_COUNTERS
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const char *events[34] = {
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"RxLoPriotyByte",
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"RxHiPriotyByte",
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"RxUndersizePkt",
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"RxFragments",
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"RxOversize",
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"RxJabbers",
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"RxSymbolError",
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"RxCRCError",
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"RxAlignmentError",
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"RxControl8808Pkts",
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"RxPausePkts",
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"RxBroadcast",
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"RxMulticast",
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"RxUnicast",
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"Rx64Octets",
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"Rx65To127Octets",
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"Rx128To255Octets",
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"Rx255To511Octets",
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"Rx512To1023Octets",
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"Rx1024To1522Octets",
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"TxLoPriotyByte",
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"TxHiPriotyByte",
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"TxLateCollision",
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"TxPausePkts",
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"TxBroadcastPkts",
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"TxMulticastPkts",
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"TxUnicastPkts",
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"TxDeferred",
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"TxTotalCollision",
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"TxExcessiveCollision",
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"TxSingleCollision",
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"TxMultipleCollision",
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"TxDropPkts",
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"RxDropPkts",
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};
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struct ksext *ee = &sc->sc_ext;
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int p = (sc->sc_chip == 0x8842) ? 3 : 1;
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for (i = 0; i < p; i++) {
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struct ksext *ee = &sc->sc_ext;
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snprintf(ee->evcntname[i], sizeof(ee->evcntname[i]),
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"%s.%d", device_xname(sc->sc_dev), i+1);
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evcnt_attach_dynamic(&ee->pev[i][0], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxLoPriotyByte");
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evcnt_attach_dynamic(&ee->pev[i][1], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxHiPriotyByte");
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evcnt_attach_dynamic(&ee->pev[i][2], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxUndersizePkt");
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evcnt_attach_dynamic(&ee->pev[i][3], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxFragments");
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evcnt_attach_dynamic(&ee->pev[i][4], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxOversize");
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evcnt_attach_dynamic(&ee->pev[i][5], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxJabbers");
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evcnt_attach_dynamic(&ee->pev[i][6], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxSymbolError");
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evcnt_attach_dynamic(&ee->pev[i][7], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxCRCError");
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evcnt_attach_dynamic(&ee->pev[i][8], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxAlignmentError");
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evcnt_attach_dynamic(&ee->pev[i][9], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxControl8808Pkts");
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evcnt_attach_dynamic(&ee->pev[i][10], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxPausePkts");
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evcnt_attach_dynamic(&ee->pev[i][11], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxBroadcast");
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evcnt_attach_dynamic(&ee->pev[i][12], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxMulticast");
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evcnt_attach_dynamic(&ee->pev[i][13], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxUnicast");
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evcnt_attach_dynamic(&ee->pev[i][14], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "Rx64Octets");
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evcnt_attach_dynamic(&ee->pev[i][15], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "Rx65To127Octets");
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evcnt_attach_dynamic(&ee->pev[i][16], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "Rx128To255Octets");
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evcnt_attach_dynamic(&ee->pev[i][17], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "Rx255To511Octets");
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evcnt_attach_dynamic(&ee->pev[i][18], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "Rx512To1023Octets");
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evcnt_attach_dynamic(&ee->pev[i][19], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "Rx1024To1522Octets");
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evcnt_attach_dynamic(&ee->pev[i][20], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxLoPriotyByte");
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evcnt_attach_dynamic(&ee->pev[i][21], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxHiPriotyByte");
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evcnt_attach_dynamic(&ee->pev[i][22], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxLateCollision");
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evcnt_attach_dynamic(&ee->pev[i][23], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxPausePkts");
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evcnt_attach_dynamic(&ee->pev[i][24], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxBroadcastPkts");
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evcnt_attach_dynamic(&ee->pev[i][25], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxMulticastPkts");
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evcnt_attach_dynamic(&ee->pev[i][26], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxUnicastPkts");
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evcnt_attach_dynamic(&ee->pev[i][27], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxDeferred");
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evcnt_attach_dynamic(&ee->pev[i][28], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxTotalCollision");
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evcnt_attach_dynamic(&ee->pev[i][29], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxExcessiveCollision");
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evcnt_attach_dynamic(&ee->pev[i][30], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxSingleCollision");
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evcnt_attach_dynamic(&ee->pev[i][31], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxMultipleCollision");
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evcnt_attach_dynamic(&ee->pev[i][32], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "TxDropPkts");
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evcnt_attach_dynamic(&ee->pev[i][33], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], "RxDropPkts");
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for (int ev = 0; ev < 34; ev++) {
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evcnt_attach_dynamic(&ee->pev[i][ev], EVCNT_TYPE_MISC,
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NULL, ee->evcntname[i], events[ev]);
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}
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}
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callout_init(&sc->sc_stat_ch, 0);
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callout_setfunc(&sc->sc_stat_ch, stat_tick, sc);
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#endif
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return;
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@ -813,10 +792,11 @@ kse_init(struct ifnet *ifp)
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sc->sc_rxc |= (kse_burstsize << RXC_BS_SFT);
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if (sc->sc_chip == 0x8842) {
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/* make PAUSE flow control to run */
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sc->sc_txc |= TXC_FCE;
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sc->sc_rxc |= RXC_FCE;
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CSR_WRITE_2(sc, SGCR3,
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CSR_READ_2(sc, SGCR3) | CR3_USEFC);
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i = CSR_READ_2(sc, SGCR3);
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CSR_WRITE_2(sc, SGCR3, i | CR3_USEFC);
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}
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/* accept multicast frame or run promisc mode */
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@ -841,14 +821,11 @@ kse_init(struct ifnet *ifp)
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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if (sc->sc_chip == 0x8841) {
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/* start one second timer */
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callout_schedule(&sc->sc_tick_ch, hz);
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}
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/* start one second timer */
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callout_schedule(&sc->sc_tick_ch, hz);
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#ifdef KSE_EVENT_COUNTERS
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/* start statistics gather 1 minute timer. should be tunable */
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zerostats(sc);
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callout_schedule(&sc->sc_stat_ch, hz * 60);
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#endif
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out:
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@ -867,11 +844,8 @@ kse_stop(struct ifnet *ifp, int disable)
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struct kse_txsoft *txs;
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int i;
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if (sc->sc_chip == 0x8841)
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callout_stop(&sc->sc_tick_ch);
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#ifdef KSE_EVENT_COUNTERS
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callout_stop(&sc->sc_stat_ch);
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#endif
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callout_stop(&sc->sc_tick_ch);
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sc->sc_txc &= ~TXC_TEN;
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sc->sc_rxc &= ~RXC_REN;
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CSR_WRITE_4(sc, MDTXC, sc->sc_txc);
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@ -1391,8 +1365,8 @@ kse_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
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mii_pollstat(mii);
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ifmr->ifm_status = mii->mii_media_status;
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ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
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sc->sc_flowflags;
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ifmr->ifm_active = sc->sc_flowflags |
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(mii->mii_media_active & ~IFM_ETH_FMASK);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -1418,10 +1392,14 @@ phy_tick(void *arg)
|
||||
struct mii_data *mii = &sc->sc_mii;
|
||||
int s;
|
||||
|
||||
s = splnet();
|
||||
mii_tick(mii);
|
||||
splx(s);
|
||||
|
||||
if (sc->sc_chip == 0x8841) {
|
||||
s = splnet();
|
||||
mii_tick(mii);
|
||||
splx(s);
|
||||
}
|
||||
#ifdef KSE_EVENT_COUNTERS
|
||||
stat_tick(arg);
|
||||
#endif
|
||||
callout_schedule(&sc->sc_tick_ch, hz);
|
||||
}
|
||||
|
||||
@ -1518,17 +1496,19 @@ stat_tick(void *arg)
|
||||
{
|
||||
struct kse_softc *sc = arg;
|
||||
struct ksext *ee = &sc->sc_ext;
|
||||
int nport, p, i, val;
|
||||
int nport, p, i, reg, val;
|
||||
|
||||
nport = (sc->sc_chip == 0x8842) ? 3 : 1;
|
||||
for (p = 0; p < nport; p++) {
|
||||
/* read 34 ev counters by indirect read via IACR */
|
||||
for (i = 0; i < 32; i++) {
|
||||
val = 0x1c00 | (p * 0x20 + i);
|
||||
CSR_WRITE_2(sc, IACR, val);
|
||||
reg = EVCNTBR + p * 0x20 + i;
|
||||
CSR_WRITE_2(sc, IACR, reg);
|
||||
/* 30-bit counter value are halved in IADR5 & IADR4 */
|
||||
do {
|
||||
val = CSR_READ_2(sc, IADR5) << 16;
|
||||
} while ((val & (1U << 30)) == 0);
|
||||
if (val & (1U << 31)) {
|
||||
} while ((val & IADR_LATCH) == 0);
|
||||
if (val & IADR_OVF) {
|
||||
(void)CSR_READ_2(sc, IADR4);
|
||||
val = 0x3fffffff; /* has made overflow */
|
||||
}
|
||||
@ -1536,34 +1516,40 @@ stat_tick(void *arg)
|
||||
val &= 0x3fff0000; /* 29:16 */
|
||||
val |= CSR_READ_2(sc, IADR4); /* 15:0 */
|
||||
}
|
||||
ee->pev[p][i].ev_count += val; /* i (0-31) */
|
||||
ee->pev[p][i].ev_count += val; /* ev0 thru 31 */
|
||||
}
|
||||
CSR_WRITE_2(sc, IACR, 0x1c00 + 0x100 + p);
|
||||
ee->pev[p][32].ev_count = CSR_READ_2(sc, IADR4); /* 32 */
|
||||
CSR_WRITE_2(sc, IACR, 0x1c00 + 0x100 + p * 3 + 1);
|
||||
ee->pev[p][33].ev_count = CSR_READ_2(sc, IADR4); /* 33 */
|
||||
/* ev32 and ev33 are 16-bit counter */
|
||||
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p);
|
||||
ee->pev[p][32].ev_count += CSR_READ_2(sc, IADR4); /* ev32 */
|
||||
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p * 3 + 1);
|
||||
ee->pev[p][33].ev_count += CSR_READ_2(sc, IADR4); /* ev33 */
|
||||
}
|
||||
callout_schedule(&sc->sc_stat_ch, hz * 60);
|
||||
}
|
||||
|
||||
static void
|
||||
zerostats(struct kse_softc *sc)
|
||||
{
|
||||
struct ksext *ee = &sc->sc_ext;
|
||||
int nport, p, i, val;
|
||||
int nport, p, i, reg, val;
|
||||
|
||||
/* Make sure all the HW counters get zero */
|
||||
nport = (sc->sc_chip == 0x8842) ? 3 : 1;
|
||||
for (p = 0; p < nport; p++) {
|
||||
for (i = 0; i < 31; i++) {
|
||||
val = 0x1c00 | (p * 0x20 + i);
|
||||
CSR_WRITE_2(sc, IACR, val);
|
||||
for (i = 0; i < 32; i++) {
|
||||
reg = EVCNTBR + p * 0x20 + i;
|
||||
CSR_WRITE_2(sc, IACR, reg);
|
||||
do {
|
||||
val = CSR_READ_2(sc, IADR5) << 16;
|
||||
} while ((val & (1U << 30)) == 0);
|
||||
} while ((val & IADR_LATCH) == 0);
|
||||
(void)CSR_READ_2(sc, IADR4);
|
||||
ee->pev[p][i].ev_count = 0;
|
||||
}
|
||||
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p);
|
||||
(void)CSR_READ_2(sc, IADR4);
|
||||
CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p * 3 + 1);
|
||||
(void)CSR_READ_2(sc, IADR4);
|
||||
ee->pev[p][32].ev_count = 0;
|
||||
ee->pev[p][33].ev_count = 0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user