From 0a449abb14c8c86b349354a66647fd986c655bc6 Mon Sep 17 00:00:00 2001 From: tsutsui Date: Mon, 11 Jun 2012 16:51:04 +0000 Subject: [PATCH] Make i915drm work on Atom N4xx/D410/D510 + GMA3150 integrated graphic devices. Patch is taken from FreeBSD: http://www.freebsd.org/cgi/query-pr.cgi?pr=143427 and tested on MSI U135DX running NetBSD/i386 6.0_BETA2 with this patch. Should be pulled up to netbsd-6. --- sys/external/bsd/drm/dist/bsd-core/drm_pciids.h | 4 +++- sys/external/bsd/drm/dist/shared-core/drm_pciids.txt | 4 +++- sys/external/bsd/drm/dist/shared-core/i915_drv.h | 10 ++++++++-- sys/external/bsd/drm/dist/shared-core/i915_reg.h | 4 ++++ 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/sys/external/bsd/drm/dist/bsd-core/drm_pciids.h b/sys/external/bsd/drm/dist/bsd-core/drm_pciids.h index 83095b362fb0..528a6bb073b8 100644 --- a/sys/external/bsd/drm/dist/bsd-core/drm_pciids.h +++ b/sys/external/bsd/drm/dist/bsd-core/drm_pciids.h @@ -581,7 +581,9 @@ {0x8086, 0x29B2, CHIP_I9XX|CHIP_I915, "Intel Q35"}, \ {0x8086, 0x29D2, CHIP_I9XX|CHIP_I915, "Intel Q33"}, \ {0x8086, 0x2A42, CHIP_I9XX|CHIP_I965, "Mobile Intel® GM45 Express Chipset"}, \ - {0x8086, 0x2E02, CHIP_I9XX|CHIP_I965, "Intel Integrated Graphics Device"}, \ + {0x8086, 0x2E02, CHIP_I9XX|CHIP_I965, "Intel Eaglelake"}, \ + {0x8086, 0xA001, CHIP_I9XX|CHIP_I965, "Intel Pineview"}, \ + {0x8086, 0xA011, CHIP_I9XX|CHIP_I965, "Intel Pineview (M)"}, \ {0x8086, 0x2E12, CHIP_I9XX|CHIP_I965, "Intel Q45/Q43"}, \ {0x8086, 0x2E22, CHIP_I9XX|CHIP_I965, "Intel G45/G43"}, \ {0, 0, 0, NULL} diff --git a/sys/external/bsd/drm/dist/shared-core/drm_pciids.txt b/sys/external/bsd/drm/dist/shared-core/drm_pciids.txt index f1aa9dea3c32..86294731d359 100644 --- a/sys/external/bsd/drm/dist/shared-core/drm_pciids.txt +++ b/sys/external/bsd/drm/dist/shared-core/drm_pciids.txt @@ -514,7 +514,9 @@ 0x8086 0x29B2 CHIP_I9XX|CHIP_I915 "Intel Q35" 0x8086 0x29D2 CHIP_I9XX|CHIP_I915 "Intel Q33" 0x8086 0x2A42 CHIP_I9XX|CHIP_I965 "Mobile Intel® GM45 Express Chipset" -0x8086 0x2E02 CHIP_I9XX|CHIP_I965 "Intel Integrated Graphics Device" +0x8086 0x2E02 CHIP_I9XX|CHIP_I965 "Intel Eaglelake" +0x8086 0xA001 CHIP_I9XX|CHIP_I965 "Intel Pineview" +0x8086 0xA011 CHIP_I9XX|CHIP_I965 "Intel Pineview (M)" 0x8086 0x2E12 CHIP_I9XX|CHIP_I965 "Intel Q45/Q43" 0x8086 0x2E22 CHIP_I9XX|CHIP_I965 "Intel G45/G43" diff --git a/sys/external/bsd/drm/dist/shared-core/i915_drv.h b/sys/external/bsd/drm/dist/shared-core/i915_drv.h index 296b49f68005..07b10378db11 100644 --- a/sys/external/bsd/drm/dist/shared-core/i915_drv.h +++ b/sys/external/bsd/drm/dist/shared-core/i915_drv.h @@ -633,15 +633,21 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); (dev)->pci_device == 0x2E12 || \ (dev)->pci_device == 0x2E22) +#define IS_IGDG(dev) ((dev)->pci_device == 0xA001) +#define IS_IGDGM(dev) ((dev)->pci_device == 0xA011) +#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) + #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ (dev)->pci_device == 0x29B2 || \ - (dev)->pci_device == 0x29D2) + (dev)->pci_device == 0x29D2 || \ + IS_IGD(dev)) #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ - IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) + IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ + IS_IGD(dev)) #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) diff --git a/sys/external/bsd/drm/dist/shared-core/i915_reg.h b/sys/external/bsd/drm/dist/shared-core/i915_reg.h index 75647757c063..91e8add2dbb3 100644 --- a/sys/external/bsd/drm/dist/shared-core/i915_reg.h +++ b/sys/external/bsd/drm/dist/shared-core/i915_reg.h @@ -334,6 +334,7 @@ #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) #define I915_CRC_ERROR_ENABLE (1UL<<29) @@ -410,6 +411,7 @@ */ #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 /* i830, required in DVO non-gang */ #define PLL_P2_DIVIDE_BY_4 (1 << 23) #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ @@ -476,10 +478,12 @@ #define FPB0 0x06048 #define FPB1 0x0604c #define FP_N_DIV_MASK 0x003f0000 +#define FP_N_IGD_DIV_MASK 0x00ff0000 #define FP_N_DIV_SHIFT 16 #define FP_M1_DIV_MASK 0x00003f00 #define FP_M1_DIV_SHIFT 8 #define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_IGD_DIV_MASK 0x000000ff #define FP_M2_DIV_SHIFT 0 #define DPLL_TEST 0x606c #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)