Add yet another Shared L2 TLB (2M/4M pages).
XXX need redesign.
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b4914b1997
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0a42effe43
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@ -1,4 +1,4 @@
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/* $NetBSD: cacheinfo.h,v 1.23 2018/03/05 05:44:07 msaitoh Exp $ */
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/* $NetBSD: cacheinfo.h,v 1.24 2018/03/09 08:49:32 msaitoh Exp $ */
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#ifndef _X86_CACHEINFO_H_
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#define _X86_CACHEINFO_H_
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@ -35,9 +35,10 @@ struct x86_cache_info {
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#define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */
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#define CAI_L2_STLB 16 /* Shared L2 TLB (4K pages) */
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#define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */
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#define CAI_PREFETCH 18 /* Prefetch */
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#define CAI_L2_STLB3 18 /* Shared L2 TLB (2M/4M pages) */
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#define CAI_PREFETCH 19 /* Prefetch */
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#define CAI_COUNT 19
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#define CAI_COUNT 20
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/*
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* AMD Cache Info:
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@ -1,4 +1,4 @@
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/* $NetBSD: i386.c,v 1.82 2018/03/05 10:54:05 msaitoh Exp $ */
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/* $NetBSD: i386.c,v 1.83 2018/03/09 08:49:32 msaitoh Exp $ */
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/*-
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* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
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@ -57,7 +57,7 @@
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#include <sys/cdefs.h>
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#ifndef lint
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__RCSID("$NetBSD: i386.c,v 1.82 2018/03/05 10:54:05 msaitoh Exp $");
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__RCSID("$NetBSD: i386.c,v 1.83 2018/03/09 08:49:32 msaitoh Exp $");
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#endif /* not lint */
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#include <sys/types.h>
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@ -1094,6 +1094,7 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
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x86_cpuid(0x18, descs);
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iterations = descs[0];
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for (i = 0; i <= iterations; i++) {
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uint32_t pgsize;
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bool full;
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x86_cpuid2(0x18, i, descs);
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@ -1101,13 +1102,48 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
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if (type == CPUID_DATP_TCTYPE_N)
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continue;
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level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL);
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pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE);
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switch (level) {
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case 1:
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if (type == CPUID_DATP_TCTYPE_I)
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caitype = CAI_ITLB; /* XXX or ITLB2? */
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else if (type == CPUID_DATP_TCTYPE_D)
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caitype = CAI_DTLB;
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else
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if (type == CPUID_DATP_TCTYPE_I) {
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switch (pgsize) {
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case CPUID_DATP_PGSIZE_4KB:
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caitype = CAI_ITLB;
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break;
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case CPUID_DATP_PGSIZE_2MB
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| CPUID_DATP_PGSIZE_4MB:
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caitype = CAI_ITLB2;
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break;
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case CPUID_DATP_PGSIZE_1GB:
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caitype = CAI_L1_1GBITLB;
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break;
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default:
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aprint_error_dev(ci->ci_dev,
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"error: unknown ITLB size (%d)\n",
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pgsize);
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caitype = CAI_ITLB;
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break;
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}
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} else if (type == CPUID_DATP_TCTYPE_D) {
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switch (pgsize) {
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case CPUID_DATP_PGSIZE_4KB:
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caitype = CAI_DTLB;
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break;
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case CPUID_DATP_PGSIZE_2MB
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| CPUID_DATP_PGSIZE_4MB:
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caitype = CAI_DTLB2;
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break;
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case CPUID_DATP_PGSIZE_1GB:
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caitype = CAI_L1_1GBDTLB;
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break;
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default:
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aprint_error_dev(ci->ci_dev,
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"error: unknown DTLB size (%d)\n",
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pgsize);
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caitype = CAI_DTLB;
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break;
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}
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} else
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caitype = -1;
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break;
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case 2:
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@ -1115,9 +1151,27 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
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caitype = CAI_L2_ITLB;
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else if (type == CPUID_DATP_TCTYPE_D)
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caitype = CAI_L2_DTLB;
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else if (type == CPUID_DATP_TCTYPE_U)
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caitype = CAI_L2_STLB;
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else
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else if (type == CPUID_DATP_TCTYPE_U) {
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switch (pgsize) {
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case CPUID_DATP_PGSIZE_4KB:
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caitype = CAI_L2_STLB;
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break;
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case CPUID_DATP_PGSIZE_4KB
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| CPUID_DATP_PGSIZE_2MB:
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caitype = CAI_L2_STLB2;
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break;
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case CPUID_DATP_PGSIZE_2MB
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| CPUID_DATP_PGSIZE_4MB:
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caitype = CAI_L2_STLB3;
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break;
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default:
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aprint_error_dev(ci->ci_dev,
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"error: unknown L2 STLB size (%d)\n",
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pgsize);
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caitype = CAI_DTLB;
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break;
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}
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} else
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caitype = -1;
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break;
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case 3:
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@ -1134,7 +1188,7 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
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level, type);
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continue;
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}
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switch (__SHIFTOUT(descs[1], CPUID_DATP_PGSIZE)) {
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switch (pgsize) {
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case CPUID_DATP_PGSIZE_4KB:
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linesize = 4 * 1024;
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break;
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@ -1165,7 +1219,7 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
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= ways * sets; /* entries */
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ci->ci_cinfo[caitype].cai_associativity
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= full ? 0xff : ways;
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ci->ci_cinfo[caitype].cai_linesize = linesize; /* page size */
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ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */
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}
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}
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@ -2276,6 +2330,7 @@ x86_print_cache_and_tlb_info(struct cpu_info *ci)
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if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
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sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL);
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sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
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sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep);
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if (sep != NULL)
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aprint_verbose("\n");
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}
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