Add microSPARC-IIep support. Protect mostek clock code with NMK48TXX
so that this file doesn't require obio, iommu and sbus to link the kernel. Make todr_handle and establish_hostid() non-static.
This commit is contained in:
uwe
parent
59ee8a3dfb
commit
0a2b7fe7d7
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.82 2001/12/04 00:05:06 darrenr Exp $ */
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/* $NetBSD: clock.c,v 1.83 2001/12/11 04:17:48 uwe Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -60,6 +60,30 @@
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*/
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#include "opt_sparc_arch.h"
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/*
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* This file lumps together a lot of loosely related stuff with
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* confusingly similar names.
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*
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* First, there are kernel's clocks provided by "timer" device. The
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* hardclock is provided by the timer register (aka system counter).
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* The statclock is provided by per cpu counter register(s) (aka
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* processor counter(s)).
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*
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* The "clock" device is the time-of-day clock provided by MK48Txx.
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* idprom is located in the NVRAM area of the chip.
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*
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* microSPARC-IIep machines use DS1287A at EBus for TOD clock and the
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* driver for it ("rtc") is in a separate file to prevent this file
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* from being cluttered even further.
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*/
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/*
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* ifdef out mk48txx TOD clock code for the sake of ms-IIep so that
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* this file doesn't require obio, iommu and sbus to link the kernel.
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*/
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#include "mk48txx.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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@ -87,6 +111,20 @@
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#include <sparc/sparc/cpuvar.h>
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#include <sparc/sparc/timerreg.h>
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#if defined(MSIIEP)
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#include <sparc/sparc/msiiepreg.h>
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/* XXX: move this stuff to msiiepreg.h? */
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/* ms-IIep PCIC registers mapped at fixed VA (see vaddrs.h) */
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#define msiiep ((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)
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/*
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* ms-IIep counters tick every 4 cpu clock @100MHz.
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* counter is reset to 1 when new limit is written.
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*/
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#define tmr_ustolimIIep(n) ((n)* 25 + 1)
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#endif /* MSIIEP */
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/*
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* Statistics clock interval and variance, in usec. Variance must be a
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* power of two. Since this gives us an even number, not an odd number,
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@ -124,11 +162,7 @@ extern struct idprom sun4_idprom_store;
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static int oldclk = 0;
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bus_space_tag_t i7_bt;
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bus_space_handle_t i7_bh;
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#endif
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/* Location and size of the MK48xx TOD clock, if present */
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static bus_space_handle_t mk_nvram_base;
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static bus_size_t mk_nvram_size;
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#endif /* SUN4 */
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static int oclockmatch(struct device *, struct cfdata *, void *);
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static void oclockattach(struct device *, struct device *, void *);
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@ -137,11 +171,6 @@ struct cfattach oclock_ca = {
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sizeof(struct device), oclockmatch, oclockattach
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};
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extern struct cfdriver oclock_cd;
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static struct intrhand level10 = { clockintr };
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static struct intrhand level14 = { statintr };
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/*
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* Sun 4 machines use the old-style (a'la Sun 3) EEPROM. On the
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* 4/100's and 4/200's, this is at a separate obio space. On the
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@ -168,7 +197,13 @@ struct cfattach eeprom_ca = {
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sizeof(struct device), eeprom_match, eeprom_attach
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};
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extern struct cfdriver eeprom_cd;
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#if NMK48TXX > 0
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/* Location and size of the MK48xx TOD clock, if present */
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static bus_space_handle_t mk_nvram_base;
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static bus_size_t mk_nvram_size;
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static int clk_wenable(todr_chip_handle_t, int);
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static int clockmatch_mainbus (struct device *, struct cfdata *, void *);
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static int clockmatch_obio(struct device *, struct cfdata *, void *);
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@ -184,8 +219,11 @@ struct cfattach clock_mainbus_ca = {
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struct cfattach clock_obio_ca = {
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sizeof(struct device), clockmatch_obio, clockattach_obio
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};
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#endif /* NMK48TXX > 0 */
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extern struct cfdriver clock_cd;
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static struct intrhand level10 = { clockintr };
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static struct intrhand level14 = { statintr };
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static int timermatch_mainbus(struct device *, struct cfdata *, void *);
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static int timermatch_obio(struct device *, struct cfdata *, void *);
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@ -194,6 +232,13 @@ static void timerattach_obio(struct device *, struct device *, void *);
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static void timerattach(volatile int *, volatile int *);
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/*
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* On ms-IIep counters are part of PCIC, so msiiep_attach will simply
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* call this function to configure the counters.
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*/
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void timerattach_msiiep(void);
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/*struct counter_4m *counterreg_4m;*/
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struct timer_4m *timerreg4m;
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#define counterreg4m cpuinfo.counterreg_4m
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@ -209,16 +254,15 @@ struct cfattach timer_obio_ca = {
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};
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/* Global TOD clock handle & idprom pointer */
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static todr_chip_handle_t todr_handle;
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todr_chip_handle_t todr_handle;
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struct idprom *idprom;
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static int clk_wenable(todr_chip_handle_t, int);
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static void stopcounter(struct counter_4m *);
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static void establish_hostid(struct idprom *);
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void establish_hostid(struct idprom *);
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void myetheraddr(u_char *);
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int timerblurb = 10; /* Guess a value; used before clock is attached */
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/*
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* old clock match routine
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*/
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@ -324,7 +368,7 @@ oclockattach(parent, self, aux)
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if ((todr_handle = intersil7170_attach(bt, bh, 1968)) == NULL)
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panic("Can't attach tod clock");
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establish_hostid(idprom = &sun4_idprom_store);
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establish_hostid(&sun4_idprom_store);
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#endif /* SUN4 */
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}
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@ -393,6 +437,9 @@ eeprom_attach(parent, self, aux)
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#endif /* SUN4 */
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}
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#if NMK48TXX > 0
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/*
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* The OPENPROM calls the clock the "eeprom", so we have to have our
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* own special match function to call it the "clock".
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@ -573,6 +620,42 @@ clockattach(node, bt, bh)
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establish_hostid(idp);
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}
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/*
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* Write en/dis-able TOD clock registers. This is a safety net to
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* save idprom (part of mk48txx TOD clock) from being accidentally
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* stomped on by a buggy code. We coordinate so that several writers
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* can run simultaneously.
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*/
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int
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clk_wenable(handle, onoff)
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todr_chip_handle_t handle;
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int onoff;
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{
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int s;
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vm_prot_t prot;/* nonzero => change prot */
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int npages;
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vaddr_t base;
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static int writers;
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/* XXX - we ignore `handle' here... */
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s = splhigh();
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if (onoff)
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prot = writers++ == 0 ? VM_PROT_READ|VM_PROT_WRITE : 0;
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else
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prot = --writers == 0 ? VM_PROT_READ : 0;
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splx(s);
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npages = round_page((vsize_t)mk_nvram_size) << PAGE_SHIFT;
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base = trunc_page((vaddr_t)mk_nvram_base);
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if (prot)
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pmap_changeprot(pmap_kernel(), base, prot, npages);
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return (0);
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}
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#endif /* NMK48TXX > 0 */ /* "clock" device driver */
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/*
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* The sun4c OPENPROM calls the timer the "counter-timer".
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*/
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@ -783,48 +866,59 @@ timerattach(cntreg, limreg)
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timerok = 1;
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}
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#if defined(MSIIEP)
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/*
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* Write en/dis-able clock registers. We coordinate so that several
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* writers can run simultaneously.
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* Attach system and cpu counters (kernel hard and stat clocks) for ms-IIep.
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* Counters are part of the PCIC and there's no PROM node for them.
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* msiiep_attach() will call this function directly.
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*/
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int
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clk_wenable(handle, onoff)
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todr_chip_handle_t handle;
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int onoff;
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{
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int s;
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vm_prot_t prot;/* nonzero => change prot */
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int npages;
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vaddr_t base;
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static int writers;
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/* XXX - we ignore `handle' here... */
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s = splhigh();
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if (onoff)
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prot = writers++ == 0 ? VM_PROT_READ|VM_PROT_WRITE : 0;
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else
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prot = --writers == 0 ? VM_PROT_READ : 0;
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splx(s);
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npages = round_page((vsize_t)mk_nvram_size) << PAGE_SHIFT;
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base = trunc_page((vaddr_t)mk_nvram_base);
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if (prot)
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pmap_changeprot(pmap_kernel(), base, prot, npages);
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return (0);
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}
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void
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stopcounter(creg)
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struct counter_4m *creg;
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timerattach_msiiep()
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{
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/* Stop the clock */
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/* Put processor counter in "counter" mode */
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msiiep->pcic_pc_ctl = 0; /* stop user timer (just in case) */
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msiiep->pcic_pc_cfg = 0; /* timer mode disabled (processor counter) */
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/*
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* Calibrate delay() by tweaking the magic constant
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* until a delay(100) actually reads (at least) 100 us on the clock.
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* Note: ms-IIep clocks ticks every 4 processor cycles.
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*/
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for (timerblurb = 1; ; ++timerblurb) {
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volatile int discard;
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discard = creg->t_limit;
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creg->t_limit = 0;
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creg->t_ss = 0;
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int t;
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discard = msiiep->pcic_pclr; /* clear the limit bit */
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msiiep->pcic_pclr = 0; /* reset counter to 1, free run */
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delay(100);
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t = msiiep->pcic_pccr;
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if (t & TMR_LIMIT) /* cannot happen */
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panic("delay calibration");
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/* counter ticks -> usec, inverse of tmr_ustolimIIep */
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t = (t - 1) / 25;
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if (t >= 100)
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break;
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}
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printf(" delay constant %d\n", timerblurb);
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/*
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* Set counter interrupt priority assignment:
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* upper 4 bits are for system counter: level 10
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* lower 4 bits are for processor counter: level 14
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*/
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msiiep->pcic_cipar = 0xae;
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/* link interrupt handlers */
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intr_establish(10, &level10);
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intr_establish(14, &level14);
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timerok = 1;
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}
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#endif /* MSIIEP */
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/*
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* XXX this belongs elsewhere
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@ -863,8 +957,8 @@ establish_hostid(idp)
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/*
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* Set up the real-time and statistics clocks. Leave stathz 0 only if
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* no alternative timer is available.
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* Set up the real-time and statistics clocks.
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* Leave stathz 0 only if no alternative timer is available.
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*
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* The frequencies of these clocks must be an even number of microseconds.
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*/
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@ -911,7 +1005,9 @@ cpu_initclocks()
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minint = statint / 2 + 100;
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while (statvar > minint)
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statvar >>= 1;
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statmin = statint - (statvar >> 1);
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#if defined(SUN4M) && !defined(MSIIEP)
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if (CPU_ISSUN4M) {
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int n;
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timerreg4m->t_limit = tmr_ustolim4m(tick);
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@ -921,23 +1017,25 @@ cpu_initclocks()
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continue;
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cpi->counterreg_4m->t_limit = tmr_ustolim4m(statint);
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}
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ienab_bic(SINTR_T);
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}
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#endif
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#if defined(MSIIEP)
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/* ms-IIep kernels support *only* IIep */ {
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msiiep->pcic_sclr = tmr_ustolimIIep(tick);
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msiiep->pcic_pclr = tmr_ustolimIIep(statint);
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/* XXX: ensure interrupt target mask doesn't masks them? */
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}
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#endif
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#if defined(SUN4) || defined(SUN4C)
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if (CPU_ISSUN4OR4C) {
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timerreg4->t_c10.t_limit = tmr_ustolim(tick);
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timerreg4->t_c14.t_limit = tmr_ustolim(statint);
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}
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statmin = statint - (statvar >> 1);
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#if defined(SUN4M)
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if (CPU_ISSUN4M)
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ienab_bic(SINTR_T);
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#endif
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if (CPU_ISSUN4OR4C)
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ienab_bis(IE_L14 | IE_L10);
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}
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#endif
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}
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/*
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@ -952,9 +1050,9 @@ setstatclockrate(newhz)
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}
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/*
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* Level 10 (clock) interrupts. If we are using the FORTH PROM for
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* console input, we need to check for that here as well, and generate
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* a software interrupt to read it.
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* Level 10 (clock) interrupts from system counter.
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* If we are using the FORTH PROM for console input, we need to check
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* for that here as well, and generate a software interrupt to read it.
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*/
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int
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clockintr(cap)
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@ -979,9 +1077,14 @@ clockintr(cap)
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goto forward;
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}
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#endif
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/* read the limit register to clear the interrupt */
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if (CPU_ISSUN4M) {
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#if !defined(MSIIEP)
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discard = timerreg4m->t_limit;
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#else
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discard = msiiep->pcic_sclr;
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#endif
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}
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if (CPU_ISSUN4OR4C) {
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@ -997,7 +1100,7 @@ forward:
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}
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/*
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* Level 14 (stat clock) interrupt handler.
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* Level 14 (stat clock) interrupts from processor counter.
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*/
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int
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statintr(cap)
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@ -1015,12 +1118,27 @@ statintr(cap)
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/* read the limit register to clear the interrupt */
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if (CPU_ISSUN4M) {
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#if !defined(MSIIEP)
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discard = counterreg4m->t_limit;
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#else
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discard = msiiep->pcic_pclr;
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#endif
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if (timerok == 0) {
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/* Stop the clock */
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printf("note: counter running!\n");
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stopcounter(counterreg4m);
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#if !defined(MSIIEP)
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discard = counterreg4m->t_limit;
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counterreg4m->t_limit = 0;
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counterreg4m->t_ss = 0;
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timerreg4m->t_cfg = TMR_CFG_USER;
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#else
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/*
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* Turn interrupting processor counter
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* into non-interrupting user timer.
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*/
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msiiep->pcic_pc_cfg = 1; /* make it a user timer */
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msiiep->pcic_pc_ctl = 0; /* stop user timer */
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#endif
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return 1;
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}
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}
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@ -1028,6 +1146,7 @@ statintr(cap)
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if (CPU_ISSUN4OR4C) {
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discard = timerreg4->t_c14.t_limit;
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}
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statclock((struct clockframe *)cap);
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/*
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@ -1047,7 +1166,11 @@ statintr(cap)
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* loose the counter ticks that happened since this
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* interrupt was raised.
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*/
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#if !defined(MSIIEP)
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counterreg4m->t_limit_nr = tmr_ustolim4m(newint);
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#else
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msiiep->pcic_pclr_nr = tmr_ustolimIIep(newint);
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#endif
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}
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if (CPU_ISSUN4OR4C) {
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