New, improved "le" driver from Charles Hannum and Paul Richards.
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gwr
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@ -1,51 +1,28 @@
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/* $NetBSD: if_le.h,v 1.5 1994/12/12 18:59:14 gwr Exp $ */
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/* $NetBSD: if_le.h,v 1.6 1995/01/03 15:43:38 gwr Exp $ */
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/*
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* Ethernet software status per interface.
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*/
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/* Per interface statistics */
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struct lestats {
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long lexints; /* transmitter interrupts */
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long lerints; /* receiver interrupts */
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long lerbufs; /* total buffers received during interrupts */
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long lerhits; /* times current rbuf was full */
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long lerscans; /* rbufs scanned before finding first full */
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};
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/*
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*
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* Each interface is referenced by a network interface structure,
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* le_if, which the routing code uses to locate the interface.
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* arpcom, which the routing code uses to locate the interface.
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* This structure contains the output queue for the interface,
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* its address, ...
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*/
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struct le_softc {
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struct device sc_dev; /* base device */
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struct arpcom sc_ac; /* common Ethernet structures */
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#define sc_if sc_ac.ac_if /* network-visible interface */
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#define sc_addr sc_ac.ac_enaddr /* hardware Ethernet address */
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#define sc_if sc_ac.ac_if /* network-visible interface */
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#define sc_enaddr sc_ac.ac_enaddr /* hardware Ethernet address */
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struct evcnt sc_intrcnt; /* # of interrupts, per le */
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struct evcnt sc_errcnt; /* # of errors, per le */
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volatile struct le_regs *sc_regs; /* LANCE registers */
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void *sc_mem; /* Shared RAM */
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volatile struct lereg1 *sc_r1; /* LANCE registers */
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volatile struct lereg2 *sc_r2; /* dual-port RAM */
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int sc_rmd; /* predicted next rmd to process */
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int sc_runt;
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int sc_jab;
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int sc_merr;
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int sc_babl;
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int sc_cerr;
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int sc_miss;
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int sc_xint;
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int sc_xown;
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int sc_uflo;
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int sc_rxlen;
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int sc_rxoff;
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int sc_txoff;
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int sc_busy;
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short sc_iflags;
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struct lestats sc_lestats; /* per interface statistics */
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volatile struct init_block *sc_init; /* Lance init. block */
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volatile struct mds *sc_rd, *sc_td;
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u_char *sc_rbuf, *sc_tbuf;
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int sc_last_rd, sc_last_td;
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int sc_no_td;
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#ifdef LEDEBUG
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int sc_debug;
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#endif
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};
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@ -1,4 +1,4 @@
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/* $NetBSD: if_le_subr.c,v 1.10 1994/12/13 18:31:51 gwr Exp $ */
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/* $NetBSD: if_le_subr.c,v 1.11 1995/01/03 15:43:39 gwr Exp $ */
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/*
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* Copyright (c) 1994 Gordon W. Ross
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@ -61,6 +61,8 @@
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#include "if_le.h"
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#include "if_le_subr.h"
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extern caddr_t dvma_malloc(); /* XXX */
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int
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le_md_match(parent, vcf, args)
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struct device *parent;
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@ -75,7 +77,7 @@ le_md_match(parent, vcf, args)
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if (ca->ca_intpri == -1)
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ca->ca_intpri = 3;
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/* The peek returns non-zero on bus error. */
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/* The peek returns -1 on bus error. */
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x = bus_peek(ca->ca_bustype, ca->ca_paddr, 1);
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return (x != -1);
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}
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@ -91,17 +93,17 @@ le_md_attach(parent, self, args)
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caddr_t p;
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/* register access */
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sc->sc_r1 = (struct lereg1 *)
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sc->sc_regs = (struct le_regs *)
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obio_alloc(ca->ca_paddr, OBIO_AMD_ETHER_SIZE);
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if (!sc->sc_r1)
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if (sc->sc_regs == NULL)
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panic(": not enough obio space\n");
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/* allocate "shared" memory */
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sc->sc_r2 = (struct lereg2 *) dvma_malloc(sizeof(struct lereg2));
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if (!sc->sc_r2)
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sc->sc_mem = dvma_malloc(MEMSIZE);
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if (sc->sc_mem == NULL)
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panic(": not enough dvma space");
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/* Install interrupt handler. */
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isr_add_autovect(le_intr, (void *)sc, ca->ca_intpri);
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idprom_etheraddr(sc->sc_addr); /* ethernet addr */
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isr_add_autovect(leintr, (void *)sc, ca->ca_intpri);
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idprom_etheraddr(sc->sc_enaddr); /* ethernet addr */
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}
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@ -1,8 +1,8 @@
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/* $NetBSD: if_le_subr.h,v 1.6 1994/12/12 18:59:16 gwr Exp $ */
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/* $NetBSD: if_le_subr.h,v 1.7 1995/01/03 15:43:40 gwr Exp $ */
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/* One might also set: LE_C3_ACON | LE_C3_BCON */
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#define LE_C3_CONFIG LE_C3_BSWP
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/* One might also set: LE_ACON | LE_BCON */
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#define LE_CONF3 (LE_BSWP)
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extern int le_md_match(struct device *, void *, void *args);
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extern void le_md_attach(struct device *, struct device *, void *);
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extern int le_intr(void *);
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extern int leintr(void *);
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@ -1,167 +1,127 @@
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/* $NetBSD: if_lereg.h,v 1.8 1994/12/12 18:59:17 gwr Exp $ */
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/* $NetBSD: if_lereg.h,v 1.9 1995/01/03 15:43:41 gwr Exp $ */
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/*-
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* Copyright (c) 1982, 1992, 1993
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* The Regents of the University of California. All rights reserved.
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/*
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* LANCE Ethernet driver header file
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* Copyright (c) 1995 Gordon W. Ross
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* Copyright (c) 1994 Charles Hannum.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_lereg.h 8.2 (Berkeley) 10/30/93
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* Copyright (C) 1993, Paul Richards. This software may be used, modified,
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* copied, distributed, and sold, in both source and binary form provided
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* that the above copyright and these terms are retained. Under no
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* circumstances is the author responsible for the proper functioning
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* of this software, nor does the author assume any responsibility
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* for damages incurred with its use.
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*/
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#define LEMTU 1518
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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#define LERBUF 8
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#define LERBUFLOG2 3
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#define LE_RLEN (LERBUFLOG2 << 13)
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#define LETBUF 1
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#define LETBUFLOG2 0
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#define LE_TLEN (LETBUFLOG2 << 13)
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/* Declarations specific to this driver */
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#define NTBUF 2
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#define TLEN 1
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#define NRBUF 8
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#define RLEN 3
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#define BUFSIZE 1518
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#define MEMSIZE 0x4000
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/* Local Area Network Controller for Ethernet (LANCE) registers */
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struct lereg1 {
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u_short ler1_rdp; /* register data port */
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u_short ler1_rap; /* register address port */
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struct le_regs {
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u_short lereg_data; /* data port */
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u_short lereg_addr; /* address port */
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};
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/* register addresses */
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#define LE_CSR0 0 /* Control and status register */
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#define LE_CSR1 1 /* low address of init block */
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#define LE_CSR2 2 /* high address of init block */
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#define LE_CSR3 3 /* Bus master and control */
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/* Control and status register 0 (csr0) */
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#define LE_C0_ERR 0x8000 /* error summary */
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#define LE_C0_BABL 0x4000 /* transmitter timeout error */
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#define LE_C0_CERR 0x2000 /* collision */
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#define LE_C0_MISS 0x1000 /* missed a packet */
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#define LE_C0_MERR 0x0800 /* memory error */
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#define LE_C0_RINT 0x0400 /* receiver interrupt */
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#define LE_C0_TINT 0x0200 /* transmitter interrupt */
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#define LE_C0_IDON 0x0100 /* initalization done */
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#define LE_C0_INTR 0x0080 /* interrupt condition */
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#define LE_C0_INEA 0x0040 /* interrupt enable */
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#define LE_C0_RXON 0x0020 /* receiver on */
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#define LE_C0_TXON 0x0010 /* transmitter on */
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#define LE_C0_TDMD 0x0008 /* transmit demand */
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#define LE_C0_STOP 0x0004 /* disable all external activity */
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#define LE_C0_STRT 0x0002 /* enable external activity */
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#define LE_C0_INIT 0x0001 /* begin initalization */
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#define LE_C0_BITS \
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"\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
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\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Control and status register 3 (csr3) */
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#define LE_C3_BSWP 0x4 /* byte swap */
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#define LE_C3_ACON 0x2 /* ALE control, eh? */
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#define LE_C3_BCON 0x1 /* byte control */
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/*
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* Current size is 13,758 bytes with 8 x 1518 receive buffers and
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* 1 x 1518 transmit buffer.
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* Control and status bits
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*/
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struct lereg2 {
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/* initialization block */
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u_short ler2_mode; /* mode */
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u_char ler2_padr[6]; /* physical address */
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u_short ler2_ladrf[4]; /* logical address filter */
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u_short ler2_rdra; /* receive descriptor addr */
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u_short ler2_rlen; /* rda high and ring size */
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u_short ler2_tdra; /* transmit descriptor addr */
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u_short ler2_tlen; /* tda high and ring size */
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/* receive message descriptors. bits/hadr are byte order dependent. */
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struct lermd {
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u_short rmd0; /* low address of packet */
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u_char rmd1_bits; /* descriptor bits */
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u_char rmd1_hadr; /* high address of packet */
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short rmd2; /* buffer byte count */
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u_short rmd3; /* message byte count */
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} ler2_rmd[LERBUF];
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/* transmit message descriptors */
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struct letmd {
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u_short tmd0; /* low address of packet */
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u_char tmd1_bits; /* descriptor bits */
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u_char tmd1_hadr; /* high address of packet */
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short tmd2; /* buffer byte count */
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u_short tmd3; /* transmit error bits */
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} ler2_tmd[LETBUF];
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char ler2_rbuf[LERBUF][LEMTU];
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char ler2_tbuf[LETBUF][LEMTU];
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#define LE_SERR 0x8000
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#define LE_BABL 0x4000
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#define LE_CERR 0x2000
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#define LE_MISS 0x1000
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#define LE_MERR 0x0800
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#define LE_RINT 0x0400
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#define LE_TINT 0x0200
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#define LE_IDON 0x0100
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#define LE_INTR 0x0080
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#define LE_INEA 0x0040
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#define LE_RXON 0x0020
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#define LE_TXON 0x0010
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#define LE_TDMD 0x0008
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#define LE_STOP 0x0004
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#define LE_STRT 0x0002
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#define LE_INIT 0x0001
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#define LE_BSWP 0x0004
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#define LE_ACON 0x0002
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#define LE_BCON 0x0001
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/*
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* LANCE initialization block
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*/
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struct init_block {
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u_short mode; /* mode register */
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u_char padr[6]; /* ethernet address */
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u_long ladrf[2]; /* logical address filter (multicast) */
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u_short rdra; /* low order pointer to receive ring */
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u_short rlen; /* high order pointer and no. rings */
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u_short tdra; /* low order pointer to transmit ring */
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u_short tlen; /* high order pointer and no rings */
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};
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/* Initialzation block (mode) */
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#define LE_MODE_PROM 0x8000 /* promiscuous mode */
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/* 0x7f80 reserved, must be zero */
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#define LE_MODE_INTL 0x0040 /* internal loopback */
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#define LE_MODE_DRTY 0x0020 /* disable retry */
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#define LE_MODE_COLL 0x0010 /* force a collision */
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#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
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#define LE_MODE_LOOP 0x0004 /* loopback mode */
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#define LE_MODE_DTX 0x0002 /* disable transmitter */
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#define LE_MODE_DRX 0x0001 /* disable receiver */
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#define LE_MODE_NORMAL 0 /* none of the above */
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/*
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* Mode bits -- init_block
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*/
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#define LE_PROM 0x8000 /* promiscuous */
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#define LE_INTL 0x0040 /* internal loopback */
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#define LE_DRTY 0x0020 /* disable retry */
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#define LE_COLL 0x0010 /* force collision */
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#define LE_DTCR 0x0008 /* disable transmit crc */
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#define LE_LOOP 0x0004 /* loopback */
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#define LE_DTX 0x0002 /* disable transmitter */
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#define LE_DRX 0x0001 /* disable receiver */
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#define LE_NORMAL 0x0000
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/*
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* Message descriptor
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*/
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struct mds {
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u_short addr;
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u_short flags;
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u_short bcnt;
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u_short mcnt;
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};
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/* Message descriptor flags */
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#define LE_OWN 0x8000 /* owner bit, 0=host, 1=LANCE */
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#define LE_ERR 0x4000 /* error */
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#define LE_STP 0x0200 /* start of packet */
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#define LE_ENP 0x0100 /* end of packet */
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/* Receive ring status flags */
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#define LE_FRAM 0x2000 /* framing error error */
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#define LE_OFLO 0x1000 /* silo overflow */
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#define LE_CRC 0x0800 /* CRC error */
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#define LE_RBUFF 0x0400 /* buffer error */
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/* Transmit ring status flags */
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#define LE_MORE 0x1000 /* more than 1 retry */
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#define LE_ONE 0x0800 /* one retry */
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#define LE_DEF 0x0400 /* deferred transmit */
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/* Transmit errors */
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#define LE_TBUFF 0x8000 /* buffer error */
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#define LE_UFLO 0x4000 /* silo underflow */
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#define LE_LCOL 0x1000 /* late collision */
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#define LE_LCAR 0x0800 /* loss of carrier */
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#define LE_RTRY 0x0400 /* tried 16 times */
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/* Receive message descriptor 1 (rmd1_bits) */
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#define LE_R1_OWN 0x80 /* LANCE owns the packet */
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#define LE_R1_ERR 0x40 /* error summary */
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#define LE_R1_FRAM 0x20 /* framing error */
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#define LE_R1_OFLO 0x10 /* overflow error */
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#define LE_R1_CRC 0x08 /* CRC error */
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#define LE_R1_BUFF 0x04 /* buffer error */
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#define LE_R1_STP 0x02 /* start of packet */
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#define LE_R1_ENP 0x01 /* end of packet */
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/* DEPCA-specific definitions */
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#define DEPCA_CSR 0x0
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#define DEPCA_CSR_SHE 0x80 /* Shared memory enabled */
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#define DEPCA_CSR_SWAP32 0x40 /* Byte swapped */
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#define DEPCA_CSR_DUM 0x08 /* rev E compatibility */
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#define DEPCA_CSR_IM 0x04 /* Interrupt masked */
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#define DEPCA_CSR_IEN 0x02 /* Interrupt enabled */
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#define DEPCA_CSR_NORMAL \
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(DEPCA_CSR_SHE | DEPCA_CSR_DUM | DEPCA_CSR_IEN)
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#define LE_R1_BITS \
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"\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
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/* Transmit message descriptor 1 (tmd1_bits) */
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#define LE_T1_OWN 0x80 /* LANCE owns the packet */
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#define LE_T1_ERR 0x40 /* error summary */
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#define LE_T1_MORE 0x10 /* multiple collisions */
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#define LE_T1_ONE 0x08 /* single collision */
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#define LE_T1_DEF 0x04 /* defferred transmit */
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#define LE_T1_STP 0x02 /* start of packet */
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#define LE_T1_ENP 0x01 /* end of packet */
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#define LE_T1_BITS \
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"\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
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/* Transmit message descriptor 3 (tmd3) */
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#define LE_T3_BUFF 0x8000 /* buffer error */
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#define LE_T3_UFLO 0x4000 /* underflow error */
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#define LE_T3_LCOL 0x1000 /* late collision */
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#define LE_T3_LCAR 0x0800 /* loss of carrier */
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#define LE_T3_RTRY 0x0400 /* retry error */
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#define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
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#define LE_XMD2_ONES 0xf000
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#define LE_T3_BITS \
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"\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
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#define DEPCA_ADP 0xc
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