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Enable the cycle counter when a CPU hatches and store an estimate of the

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frequency in ci_data.cpu_cc_freq.
This commit is contained in:
jmcneill 2020-03-30 11:38:29 +00:00
parent 3d593cdb32
commit 08d87523dd
3 changed files with 32 additions and 24 deletions
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27
sys/arch/aarch64/aarch64/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.41 2020/02/15 08:16:10 skrll Exp $ */
/* $NetBSD: cpu.c,v 1.42 2020/03/30 11:38:29 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.41 2020/02/15 08:16:10 skrll Exp $");
__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.42 2020/03/30 11:38:29 jmcneill Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@ -46,6 +46,7 @@ __KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.41 2020/02/15 08:16:10 skrll Exp $");
#include <aarch64/armreg.h>
#include <aarch64/cpu.h>
#include <aarch64/cpufunc.h>
#include <aarch64/cpu_counter.h>
#include <aarch64/machdep.h>
#include <arm/cpu_topology.h>
@ -64,6 +65,7 @@ static void identify_aarch64_model(uint32_t, char *, size_t);
static void cpu_identify(device_t self, struct cpu_info *);
static void cpu_identify1(device_t self, struct cpu_info *);
static void cpu_identify2(device_t self, struct cpu_info *);
static void cpu_init_counter(struct cpu_info *);
static void cpu_setup_id(struct cpu_info *);
static void cpu_setup_sysctl(device_t, struct cpu_info *);
@ -107,8 +109,6 @@ cpu_attach(device_t dv, cpuid_t id)
ci->ci_cpl = IPL_HIGH;
ci->ci_cpuid = id;
// XXX big.LITTLE
ci->ci_data.cpu_cc_freq = cpu_info_store[0].ci_data.cpu_cc_freq;
/* ci_id is stored by own cpus when hatching */
cpu_info[ncpu] = ci;
@ -150,6 +150,8 @@ cpu_attach(device_t dv, cpuid_t id)
aarch64_printcacheinfo(dv);
cpu_identify2(dv, ci);
cpu_init_counter(ci);
cpu_setup_sysctl(dv, ci);
}
@ -422,6 +424,21 @@ cpu_identify2(device_t self, struct cpu_info *ci)
aprint_normal("\n");
}
/*
* Enable the performance counter, then estimate frequency for
* the current PE and store the result in cpu_cc_freq.
*/
static void
cpu_init_counter(struct cpu_info *ci)
{
reg_pmcr_el0_write(PMCR_E | PMCR_C);
reg_pmcntenset_el0_write(PMCNTEN_C);
const uint32_t prev = cpu_counter32();
delay(100000);
ci->ci_data.cpu_cc_freq = (cpu_counter32() - prev) * 10;
}
/*
* Fill in this CPUs id data. Must be called from hatched cpus.
*/
@ -500,6 +517,8 @@ cpu_hatch(struct cpu_info *ci)
mutex_exit(&cpu_hatch_lock);
cpu_init_counter(ci);
intr_cpu_init(ci);
#ifdef FDT

5
sys/arch/aarch64/include/armreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: armreg.h,v 1.38 2020/03/06 20:28:26 ryo Exp $ */
/* $NetBSD: armreg.h,v 1.39 2020/03/30 11:38:29 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@ -1121,6 +1121,9 @@ AARCH64REG_READ_INLINE(pmceid1_el0)
AARCH64REG_WRITE_INLINE(pmcntenclr_el0)
AARCH64REG_WRITE_INLINE(pmcntenset_el0)
#define PMCNTEN_C __BIT(31) // Enable the cycle counter
#define PMCNTEN_P __BITS(30,0) // Enable event counter bits
AARCH64REG_READ_INLINE(pmcr_el0)
AARCH64REG_WRITE_INLINE(pmcr_el0)

24
sys/dev/tprof/tprof_armv8.c
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@ -1,4 +1,4 @@
/* $NetBSD: tprof_armv8.c,v 1.4 2018/07/17 00:42:48 christos Exp $ */
/* $NetBSD: tprof_armv8.c,v 1.5 2020/03/30 11:38:29 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.4 2018/07/17 00:42:48 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.5 2020/03/30 11:38:29 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -86,12 +86,7 @@ static void
armv8_pmu_start_cpu(void *arg1, void *arg2)
{
const uint32_t counter_mask = __BIT(armv8_pmu_counter);
uint64_t pmcr, pmevtyper;
/* Enable performance monitor */
pmcr = reg_pmcr_el0_read();
pmcr |= PMCR_E;
reg_pmcr_el0_write(pmcr);
uint64_t pmevtyper;
/* Disable event counter */
reg_pmcntenclr_el0_write(counter_mask);
@ -122,18 +117,12 @@ static void
armv8_pmu_stop_cpu(void *arg1, void *arg2)
{
const uint32_t counter_mask = __BIT(armv8_pmu_counter);
uint32_t pmcr;
/* Disable overflow interrupts */
reg_pmintenclr_el1_write(counter_mask);
/* Disable event counter */
reg_pmcntenclr_el0_write(counter_mask);
/* Disable performance monitor */
pmcr = reg_pmcr_el0_read();
pmcr &= ~PMCR_E;
reg_pmcr_el0_write(pmcr);
}
static uint64_t
@ -226,11 +215,8 @@ armv8_pmu_init(void)
/* Disable interrupts */
reg_pmintenclr_el1_write(~0U);
/* Disable counters */
reg_pmcntenclr_el0_write(~0U);
/* Disable performance monitor */
reg_pmcr_el0_write(0);
/* Disable event counters */
reg_pmcntenclr_el0_write(PMCNTEN_P);
return tprof_backend_register("tprof_armv8", &tprof_armv8_pmu_ops,
TPROF_BACKEND_VERSION);