Check and set PCI power management register. clcs now works when
warm boot from Windows.
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@ -1,4 +1,4 @@
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/* $NetBSD: cs4280.c,v 1.14 2001/02/07 14:41:10 tacha Exp $ */
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/* $NetBSD: cs4280.c,v 1.15 2001/02/13 04:11:11 tacha Exp $ */
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/*
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* Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
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@ -208,10 +208,11 @@ cs4280_attach(parent, self, aux)
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pci_chipset_tag_t pc = pa->pa_pc;
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char const *intrstr;
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pci_intr_handle_t ih;
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pcireg_t csr;
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pcireg_t reg;
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char devinfo[256];
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mixer_ctrl_t ctl;
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u_int32_t mem;
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int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg;
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
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printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
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@ -232,10 +233,25 @@ cs4280_attach(parent, self, aux)
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sc->sc_dmatag = pa->pa_dmat;
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/* Check and set Power State */
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if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT,
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&pci_pwrmgmt_cap_reg, 0)) {
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pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4;
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reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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pci_pwrmgmt_csr_reg);
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DPRINTF(("%s: Power State is %d\n",
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sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK));
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if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) {
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pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg,
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(reg & ~PCI_PMCSR_STATE_MASK) |
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PCI_PMCSR_STATE_D0);
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}
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}
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/* Enable the device (set bus master flag) */
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csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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csr | PCI_COMMAND_MASTER_ENABLE);
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reg | PCI_COMMAND_MASTER_ENABLE);
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/* LATENCY_TIMER setting */
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mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
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