Compute CRC for all segments of a multi-buffer packet.
Add interrupt mitigation for transmit and receive. Use separate transmit lock. Fix some error paths.
This commit is contained in:
mlelstv
parent
e1035e4cdb
commit
089deafcbb
@ -1,4 +1,4 @@
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/* $NetBSD: bcmgenet.c,v 1.7 2020/06/27 13:34:20 jmcneill Exp $ */
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/* $NetBSD: bcmgenet.c,v 1.8 2021/03/08 13:14:44 mlelstv Exp $ */
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/*-
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* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
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@ -34,7 +34,7 @@
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#include "opt_ddb.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bcmgenet.c,v 1.7 2020/06/27 13:34:20 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bcmgenet.c,v 1.8 2021/03/08 13:14:44 mlelstv Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -72,20 +72,24 @@ CTASSERT(MCLBYTES == 2048);
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#define CALLOUT_FLAGS 0
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#endif
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#define TX_SKIP(n, o) (((n) + (o)) & (GENET_DMA_DESC_COUNT - 1))
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#define TX_NEXT(n) TX_SKIP(n, 1)
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#define RX_NEXT(n) (((n) + 1) & (GENET_DMA_DESC_COUNT - 1))
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#define TX_MAX_SEGS 128
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#define TX_DESC_COUNT GENET_DMA_DESC_COUNT
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#define RX_DESC_COUNT GENET_DMA_DESC_COUNT
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#define TX_DESC_COUNT 256 /* GENET_DMA_DESC_COUNT */
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#define RX_DESC_COUNT 256 /* GENET_DMA_DESC_COUNT */
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#define MII_BUSY_RETRY 1000
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#define GENET_MAX_MDF_FILTER 17
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#define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT)
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#define TX_NEXT(n) TX_SKIP(n, 1)
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#define RX_NEXT(n) (((n) + 1) % RX_DESC_COUNT)
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#define GENET_LOCK(sc) mutex_enter(&(sc)->sc_lock)
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#define GENET_UNLOCK(sc) mutex_exit(&(sc)->sc_lock)
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#define GENET_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock))
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#define GENET_TXLOCK(sc) mutex_enter(&(sc)->sc_txlock)
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#define GENET_TXUNLOCK(sc) mutex_exit(&(sc)->sc_txlock)
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#define GENET_ASSERT_TXLOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_txlock))
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#define RD4(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define WR4(sc, reg, val) \
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@ -190,7 +194,6 @@ genet_setup_txdesc(struct genet_softc *sc, int index, int flags,
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uint32_t status;
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status = flags | __SHIFTIN(len, GENET_TX_DESC_STATUS_BUFLEN);
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++sc->sc_tx.queued;
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WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
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WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
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@ -203,49 +206,58 @@ genet_setup_txbuf(struct genet_softc *sc, int index, struct mbuf *m)
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bus_dma_segment_t *segs;
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int error, nsegs, cur, i;
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uint32_t flags;
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bool nospace;
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/* at least one descriptor free ? */
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if (sc->sc_tx.queued >= TX_DESC_COUNT - 1)
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return -1;
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error = bus_dmamap_load_mbuf(sc->sc_tx.buf_tag,
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sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
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if (error == EFBIG) {
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device_printf(sc->sc_dev,
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"TX packet needs too many DMA segments, dropping...\n");
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m_freem(m);
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return -2;
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}
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if (error != 0) {
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device_printf(sc->sc_dev,
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"TX packet cannot be mapped, retried...\n");
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return 0;
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}
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if (error != 0)
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return 0;
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segs = sc->sc_tx.buf_map[index].map->dm_segs;
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nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs;
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if (sc->sc_tx.queued >= GENET_DMA_DESC_COUNT - nsegs) {
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nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs;
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if (nospace) {
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bus_dmamap_unload(sc->sc_tx.buf_tag,
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sc->sc_tx.buf_map[index].map);
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/* XXX coalesce and retry ? */
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return -1;
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}
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bus_dmamap_sync(sc->sc_tx.buf_tag, sc->sc_tx.buf_map[index].map,
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0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE);
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/* stored in same index as loaded map */
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sc->sc_tx.buf_map[index].mbuf = m;
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flags = GENET_TX_DESC_STATUS_SOP |
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GENET_TX_DESC_STATUS_CRC |
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GENET_TX_DESC_STATUS_QTAG;
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for (cur = index, i = 0; i < nsegs; i++) {
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sc->sc_tx.buf_map[cur].mbuf = (i == 0 ? m : NULL);
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if (i == nsegs - 1)
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flags |= GENET_TX_DESC_STATUS_EOP;
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genet_setup_txdesc(sc, cur, flags, segs[i].ds_addr,
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segs[i].ds_len);
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if (i == 0) {
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if (i == 0)
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flags &= ~GENET_TX_DESC_STATUS_SOP;
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flags &= ~GENET_TX_DESC_STATUS_CRC;
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}
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cur = TX_NEXT(cur);
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}
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bus_dmamap_sync(sc->sc_tx.buf_tag, sc->sc_tx.buf_map[index].map,
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0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE);
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return nsegs;
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}
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@ -425,6 +437,43 @@ genet_reset(struct genet_softc *sc)
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return 0;
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}
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static void
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genet_set_rxthresh(struct genet_softc *sc, int qid, int usecs, int count)
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{
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int ticks;
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uint32_t val;
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/* convert to 125MHz/1024 ticks */
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ticks = howmany(usecs * 125, 1024);
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if (count < 1)
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count = 1;
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if (count > GENET_INTR_THRESHOLD_MASK)
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count = GENET_INTR_THRESHOLD_MASK;
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if (ticks < 0)
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ticks = 0;
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if (ticks > GENET_DMA_RING_TIMEOUT_MASK)
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ticks = GENET_DMA_RING_TIMEOUT_MASK;
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WR4(sc, GENET_RX_DMA_MBUF_DONE_THRES(qid), count);
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val = RD4(sc, GENET_RX_DMA_RING_TIMEOUT(qid));
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val &= ~GENET_DMA_RING_TIMEOUT_MASK;
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val |= ticks;
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WR4(sc, GENET_RX_DMA_RING_TIMEOUT(qid), val);
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}
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static void
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genet_set_txthresh(struct genet_softc *sc, int qid, int count)
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{
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if (count < 1)
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count = 1;
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if (count > GENET_INTR_THRESHOLD_MASK)
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count = GENET_INTR_THRESHOLD_MASK;
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WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), count);
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}
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static void
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genet_init_rings(struct genet_softc *sc, int qid)
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{
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@ -449,11 +498,13 @@ genet_init_rings(struct genet_softc *sc, int qid)
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WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
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TX_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1);
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WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
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WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), 1);
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WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
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WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
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WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
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/* interrupt after 10 packets or when ring empty */
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genet_set_txthresh(sc, qid, 10);
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WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
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/* Enable transmit DMA */
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@ -486,6 +537,12 @@ genet_init_rings(struct genet_softc *sc, int qid)
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WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
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WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
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/*
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* interrupt on first packet,
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* mitigation timeout timeout 57 us (~84 minimal packets at 1Gbit/s)
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*/
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genet_set_rxthresh(sc, qid, 57, 10);
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WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
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/* Enable receive DMA */
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@ -504,6 +561,7 @@ genet_init_locked(struct genet_softc *sc)
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const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
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GENET_ASSERT_LOCKED(sc);
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GENET_ASSERT_TXLOCKED(sc);
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if ((ifp->if_flags & IFF_RUNNING) != 0)
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return 0;
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@ -555,7 +613,9 @@ genet_init(struct ifnet *ifp)
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int error;
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GENET_LOCK(sc);
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GENET_TXLOCK(sc);
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error = genet_init_locked(sc);
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GENET_TXUNLOCK(sc);
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GENET_UNLOCK(sc);
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return error;
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@ -627,10 +687,33 @@ genet_rxintr(struct genet_softc *sc, int qid)
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DPRINTF("RX pidx=%08x total=%d\n", pidx, total);
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index = sc->sc_rx.cidx & (RX_DESC_COUNT - 1);
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index = sc->sc_rx.cidx % RX_DESC_COUNT;
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for (n = 0; n < total; n++) {
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status = RD4(sc, GENET_RX_DESC_STATUS(index));
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if (status & GENET_RX_DESC_STATUS_ALL_ERRS) {
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if (status & GENET_RX_DESC_STATUS_OVRUN_ERR)
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device_printf(sc->sc_dev, "overrun\n");
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if (status & GENET_RX_DESC_STATUS_CRC_ERR)
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device_printf(sc->sc_dev, "CRC error\n");
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if (status & GENET_RX_DESC_STATUS_RX_ERR)
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device_printf(sc->sc_dev, "receive error\n");
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if (status & GENET_RX_DESC_STATUS_FRAME_ERR)
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device_printf(sc->sc_dev, "frame error\n");
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if (status & GENET_RX_DESC_STATUS_LEN_ERR)
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device_printf(sc->sc_dev, "length error\n");
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if_statinc(ifp, if_ierrors);
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goto next;
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}
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if (status & GENET_RX_DESC_STATUS_OWN)
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device_printf(sc->sc_dev, "OWN %d of %d\n",n,total);
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len = __SHIFTOUT(status, GENET_RX_DESC_STATUS_BUFLEN);
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if (len < ETHER_ALIGN) {
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if_statinc(ifp, if_ierrors);
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goto next;
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}
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m = sc->sc_rx.buf_map[index].mbuf;
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@ -638,29 +721,34 @@ genet_rxintr(struct genet_softc *sc, int qid)
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if_statinc(ifp, if_ierrors);
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goto next;
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}
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error = genet_setup_rxbuf(sc, index, m0);
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if (error != 0) {
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if_statinc(ifp, if_ierrors);
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goto next;
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}
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/* unload map before it gets loaded in setup_rxbuf */
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bus_dmamap_sync(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map,
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0, sc->sc_rx.buf_map[index].map->dm_mapsize,
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BUS_DMASYNC_POSTREAD);
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bus_dmamap_unload(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map);
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sc->sc_rx.buf_map[index].mbuf = NULL;
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error = genet_setup_rxbuf(sc, index, m0);
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if (error != 0) {
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m_freem(m0);
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if_statinc(ifp, if_ierrors);
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/* XXX mbuf is unloaded but load failed */
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m_freem(m);
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device_printf(sc->sc_dev,
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"cannot load RX mbuf. panic?\n");
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goto next;
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}
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DPRINTF("RX [#%d] index=%02x status=%08x len=%d adj_len=%d\n",
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n, index, status, len, len - ETHER_ALIGN);
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if (len > ETHER_ALIGN) {
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m_adj(m, ETHER_ALIGN);
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m_set_rcvif(m, ifp);
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m->m_len = m->m_pkthdr.len = len;
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m_adj(m, ETHER_ALIGN);
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m_set_rcvif(m, ifp);
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m->m_len = m->m_pkthdr.len = len - ETHER_ALIGN;
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m->m_nextpkt = NULL;
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if_percpuq_enqueue(ifp->if_percpuq, m);
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}
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if_percpuq_enqueue(ifp->if_percpuq, m);
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next:
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index = RX_NEXT(index);
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@ -675,34 +763,28 @@ genet_txintr(struct genet_softc *sc, int qid)
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{
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struct ifnet *ifp = &sc->sc_ec.ec_if;
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struct genet_bufmap *bmap;
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uint32_t cidx, total;
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int i;
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GENET_ASSERT_LOCKED(sc);
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int cidx, i, pkts = 0;
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cidx = RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)) & 0xffff;
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total = (cidx - sc->sc_tx.cidx) & 0xffff;
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for (i = sc->sc_tx.next; sc->sc_tx.queued > 0 && total > 0; i = TX_NEXT(i), total--) {
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/* XXX check for errors */
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i = sc->sc_tx.cidx % TX_DESC_COUNT;
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while (sc->sc_tx.cidx != cidx) {
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bmap = &sc->sc_tx.buf_map[i];
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if (bmap->mbuf != NULL) {
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/* XXX first segment already unloads */
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bus_dmamap_sync(sc->sc_tx.buf_tag, bmap->map,
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0, bmap->map->dm_mapsize,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->sc_tx.buf_tag, bmap->map);
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m_freem(bmap->mbuf);
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bmap->mbuf = NULL;
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++pkts;
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}
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--sc->sc_tx.queued;
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ifp->if_flags &= ~IFF_OACTIVE;
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if_statinc(ifp, if_opackets);
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i = TX_NEXT(i);
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sc->sc_tx.cidx = (sc->sc_tx.cidx + 1) & 0xffff;
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}
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sc->sc_tx.next = i;
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sc->sc_tx.cidx = cidx;
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if_statadd(ifp, if_opackets, pkts);
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}
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static void
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@ -712,16 +794,19 @@ genet_start_locked(struct genet_softc *sc)
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struct mbuf *m;
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int nsegs, index, cnt;
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GENET_ASSERT_LOCKED(sc);
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GENET_ASSERT_TXLOCKED(sc);
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if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
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return;
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const int qid = GENET_DMA_DEFAULT_QUEUE;
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index = sc->sc_tx.pidx & (TX_DESC_COUNT - 1);
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index = sc->sc_tx.pidx % TX_DESC_COUNT;
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cnt = 0;
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sc->sc_tx.queued = (RD4(sc, GENET_TX_DMA_PROD_INDEX(qid))
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- RD4(sc, GENET_TX_DMA_CONS_INDEX(qid))) & 0xffff;
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for (;;) {
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IFQ_POLL(&ifp->if_snd, m);
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if (m == NULL)
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@ -729,15 +814,21 @@ genet_start_locked(struct genet_softc *sc)
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nsegs = genet_setup_txbuf(sc, index, m);
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if (nsegs <= 0) {
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if (nsegs == -1)
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if (nsegs == -1) {
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ifp->if_flags |= IFF_OACTIVE;
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}
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else if (nsegs == -2) {
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IFQ_DEQUEUE(&ifp->if_snd, m);
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m_freem(m);
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}
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break;
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}
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IFQ_DEQUEUE(&ifp->if_snd, m);
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bpf_mtap(ifp, m, BPF_D_OUT);
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index = TX_SKIP(index, nsegs);
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sc->sc_tx.queued += nsegs;
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sc->sc_tx.pidx = (sc->sc_tx.pidx + nsegs) & 0xffff;
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cnt++;
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}
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@ -751,9 +842,9 @@ genet_start(struct ifnet *ifp)
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{
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struct genet_softc *sc = ifp->if_softc;
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GENET_LOCK(sc);
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GENET_TXLOCK(sc);
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genet_start_locked(sc);
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GENET_UNLOCK(sc);
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GENET_TXUNLOCK(sc);
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}
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int
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@ -762,22 +853,25 @@ genet_intr(void *arg)
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struct genet_softc *sc = arg;
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struct ifnet *ifp = &sc->sc_ec.ec_if;
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uint32_t val;
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GENET_LOCK(sc);
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bool dotx = false;
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val = RD4(sc, GENET_INTRL2_CPU_STAT);
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val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);
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WR4(sc, GENET_INTRL2_CPU_CLEAR, val);
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if (val & GENET_IRQ_RXDMA_DONE)
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if (val & GENET_IRQ_RXDMA_DONE) {
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||||
GENET_LOCK(sc);
|
||||
genet_rxintr(sc, GENET_DMA_DEFAULT_QUEUE);
|
||||
GENET_UNLOCK(sc);
|
||||
}
|
||||
|
||||
if (val & GENET_IRQ_TXDMA_DONE) {
|
||||
genet_txintr(sc, GENET_DMA_DEFAULT_QUEUE);
|
||||
if_schedule_deferred_start(ifp);
|
||||
dotx = true;
|
||||
}
|
||||
|
||||
GENET_UNLOCK(sc);
|
||||
if (dotx)
|
||||
if_schedule_deferred_start(ifp);
|
||||
|
||||
return 1;
|
||||
}
|
||||
@ -948,6 +1042,7 @@ genet_attach(struct genet_softc *sc)
|
||||
aprint_normal(": GENETv%d.%d\n", maj, min);
|
||||
|
||||
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET);
|
||||
mutex_init(&sc->sc_txlock, MUTEX_DEFAULT, IPL_NET);
|
||||
callout_init(&sc->sc_stat_ch, CALLOUT_FLAGS);
|
||||
callout_setfunc(&sc->sc_stat_ch, genet_tick, sc);
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: bcmgenetreg.h,v 1.3 2020/04/25 10:21:41 jmcneill Exp $ */
|
||||
/* $NetBSD: bcmgenetreg.h,v 1.4 2021/03/08 13:14:44 mlelstv Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
|
||||
@ -110,6 +110,7 @@
|
||||
#define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18)
|
||||
#define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c)
|
||||
#define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20)
|
||||
#define GENET_RX_DMA_MBUF_DONE_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x24)
|
||||
#define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28)
|
||||
#define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16)
|
||||
#define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0)
|
||||
@ -162,11 +163,18 @@
|
||||
#define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
|
||||
#define GENET_RX_DMA_CTRL_EN __BIT(0)
|
||||
#define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c)
|
||||
#define GENET_RX_DMA_RING_TIMEOUT(qid) (GENET_RX_BASE + 0x1040 + 0x2c + 4 * (qid))
|
||||
|
||||
#define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00)
|
||||
#define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04)
|
||||
#define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
|
||||
#define GENET_TX_DMA_CTRL_EN __BIT(0)
|
||||
#define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c)
|
||||
#define GENET_TX_DMA_RING_TIMEOUT(qid) (GENET_TX_BASE + 0x1040 + 0x2c + 4 * (qid))
|
||||
|
||||
/* GENET_RX_DMA_MBUF_DONE_THRES, GENET_TX_DMA_MBUF_DONE_THRES */
|
||||
#define GENET_INTR_THRESHOLD_MASK __BITS(0,8)
|
||||
/* GENET_RX_DMA_RING_TIMEOUT, GENET_TX_DMA_RING_TIMEOUT */
|
||||
#define GENET_DMA_RING_TIMEOUT_MASK __BITS(0,15)
|
||||
|
||||
#endif /* !_BCMGENETREG_H */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: bcmgenetvar.h,v 1.2 2020/05/25 19:49:28 jmcneill Exp $ */
|
||||
/* $NetBSD: bcmgenetvar.h,v 1.3 2021/03/08 13:14:44 mlelstv Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
|
||||
@ -66,6 +66,7 @@ struct genet_softc {
|
||||
struct mii_data sc_mii;
|
||||
callout_t sc_stat_ch;
|
||||
kmutex_t sc_lock;
|
||||
kmutex_t sc_txlock;
|
||||
|
||||
struct genet_ring sc_tx;
|
||||
struct genet_ring sc_rx;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user