Tweak register bit names, in preparation for supporting younger siblings
of this chip.
This commit is contained in:
thorpej
parent
c48d8a0ff1
commit
08733279a9
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@ -1,4 +1,4 @@
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/* $NetBSD: tsl256x.c,v 1.8 2020/01/15 05:56:57 thorpej Exp $ */
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/* $NetBSD: tsl256x.c,v 1.9 2021/01/04 21:59:48 thorpej Exp $ */
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/*-
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* Copyright (c) 2018 Jason R. Thorpe
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tsl256x.c,v 1.8 2020/01/15 05:56:57 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tsl256x.c,v 1.9 2021/01/04 21:59:48 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -127,7 +127,7 @@ tsllux_match(device_t parent, cfdata_t match, void *aux)
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if (iic_acquire_bus(ia->ia_tag, 0) != 0)
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return (0);
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error = iic_smbus_read_byte(ia->ia_tag, ia->ia_addr,
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TSL256x_REG_ID | COMMAND_CMD, &id_reg, 0);
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TSL256x_REG_ID | COMMAND6x_CMD, &id_reg, 0);
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iic_release_bus(ia->ia_tag, 0);
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if (error)
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@ -165,15 +165,15 @@ tsllux_attach(device_t parent, device_t self, void *aux)
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have_i2c = true;
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/* Power on the device and clear any pending interrupts. */
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if (tsllux_write1(sc, TSL256x_REG_CONTROL | COMMAND_CLEAR,
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CONTROL_POWER_ON)) {
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if (tsllux_write1(sc, TSL256x_REG_CONTROL | COMMAND6x_CLEAR,
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CONTROL6x_POWER_ON)) {
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aprint_error_dev(self, ": unable to power on device\n");
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goto out;
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}
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sc->sc_poweron = 1;
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/* Make sure interrupts are disabled. */
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if (tsllux_write1(sc, TSL256x_REG_INTERRUPT | COMMAND_CLEAR, 0)) {
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if (tsllux_write1(sc, TSL256x_REG_INTERRUPT | COMMAND6x_CLEAR, 0)) {
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aprint_error_dev(self, ": unable to disable interrupts\n");
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goto out;
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}
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@ -184,8 +184,8 @@ tsllux_attach(device_t parent, device_t self, void *aux)
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/* Inititalize timing to reasonable defaults. */
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sc->sc_auto_gain = true;
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sc->sc_gain = TIMING_GAIN_16X;
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if (tsllux_set_integration_time(sc, TIMING_INTEG_101ms)) {
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sc->sc_gain = TIMING6x_GAIN_16X;
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if (tsllux_set_integration_time(sc, TIMING6x_INTEG_101ms)) {
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aprint_error_dev(self, ": unable to set integration time\n");
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goto out;
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}
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@ -289,11 +289,11 @@ tsllux_sysctl_gain(SYSCTLFN_ARGS)
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mutex_enter(&sc->sc_lock);
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switch (sc->sc_gain) {
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case TIMING_GAIN_1X:
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case TIMING6x_GAIN_1X:
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val = 1;
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break;
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case TIMING_GAIN_16X:
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case TIMING6x_GAIN_16X:
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val = 16;
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break;
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@ -310,11 +310,11 @@ tsllux_sysctl_gain(SYSCTLFN_ARGS)
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switch (val) {
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case 1:
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new_gain = TIMING_GAIN_1X;
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new_gain = TIMING6x_GAIN_1X;
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break;
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case 16:
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new_gain = TIMING_GAIN_16X;
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new_gain = TIMING6x_GAIN_16X;
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break;
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default:
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@ -349,15 +349,15 @@ tsllux_sysctl_itime(SYSCTLFN_ARGS)
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mutex_enter(&sc->sc_lock);
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switch (sc->sc_itime) {
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case TIMING_INTEG_13_7ms:
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case TIMING6x_INTEG_13_7ms:
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val = 13;
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break;
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case TIMING_INTEG_101ms:
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case TIMING6x_INTEG_101ms:
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val = 101;
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break;
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case TIMING_INTEG_402ms:
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case TIMING6x_INTEG_402ms:
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default:
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val = 402;
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break;
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@ -372,15 +372,15 @@ tsllux_sysctl_itime(SYSCTLFN_ARGS)
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switch (val) {
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case 13:
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case 14:
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new_itime = TIMING_INTEG_13_7ms;
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new_itime = TIMING6x_INTEG_13_7ms;
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break;
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case 101:
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new_itime = TIMING_INTEG_101ms;
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new_itime = TIMING6x_INTEG_101ms;
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break;
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case 402:
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new_itime = TIMING_INTEG_402ms;
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new_itime = TIMING6x_INTEG_402ms;
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break;
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default:
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@ -478,26 +478,26 @@ tsllux_sensors_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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/*
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* Allow pending interrupts to be cleared as part of another operation.
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*/
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#define REGMASK (COMMAND_REGMASK | COMMAND_CLEAR)
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#define REGMASK6x (COMMAND6x_REGMASK | COMMAND6x_CLEAR)
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static int
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tsllux_read1(struct tsllux_softc *sc, uint8_t reg, uint8_t *valp)
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{
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reg = (reg & REGMASK) | COMMAND_CMD;
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reg = (reg & REGMASK6x) | COMMAND6x_CMD;
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return (iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, valp, 0));
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}
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static int
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tsllux_read2(struct tsllux_softc *sc, uint8_t reg, uint16_t *valp)
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{
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reg = (reg & REGMASK) | COMMAND_CMD | COMMAND_WORD;
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reg = (reg & REGMASK6x) | COMMAND6x_CMD | COMMAND6x_WORD;
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return (iic_smbus_read_word(sc->sc_i2c, sc->sc_addr, reg, valp, 0));
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}
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static int
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tsllux_write1(struct tsllux_softc *sc, uint8_t reg, uint8_t val)
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{
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reg = (reg & REGMASK) | COMMAND_CMD;
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reg = (reg & REGMASK6x) | COMMAND6x_CMD;
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return (iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0));
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}
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@ -505,7 +505,7 @@ tsllux_write1(struct tsllux_softc *sc, uint8_t reg, uint8_t val)
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static int
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tsllux_write2(struct tsllux_softc *sc, uint8_t reg, uint16_t val)
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{
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reg = (reg & REGMASK) | COMMAND_CMD | COMMAND_WORD;
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reg = (reg & REGMASK6x) | COMMAND6x_CMD | COMMAND6x_WORD;
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return (iic_smbus_write_word(sc->sc_i2c, sc->sc_addr, reg, val, 0));
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}
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#endif
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@ -521,7 +521,7 @@ tsllux_poweron(struct tsllux_softc *sc)
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uint8_t val;
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error = tsllux_write1(sc, TSL256x_REG_CONTROL,
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CONTROL_POWER_ON);
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CONTROL6x_POWER_ON);
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if (error)
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return (error);
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@ -529,7 +529,7 @@ tsllux_poweron(struct tsllux_softc *sc)
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if (error)
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return (error);
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if (val != CONTROL_POWER_ON) {
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if (val != CONTROL6x_POWER_ON) {
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aprint_error_dev(sc->sc_dev,
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"failed to power on sensor\n");
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return (EIO);
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@ -543,7 +543,7 @@ tsllux_poweroff(struct tsllux_softc *sc)
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{
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if (sc->sc_poweron && --sc->sc_poweron == 0)
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return (tsllux_write1(sc, TSL256x_REG_CONTROL,
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CONTROL_POWER_OFF));
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CONTROL6x_POWER_OFF));
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return (0);
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}
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@ -553,9 +553,9 @@ tsllux_set_integration_time(struct tsllux_softc *sc, uint8_t time)
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int error;
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switch (time) {
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case TIMING_INTEG_13_7ms:
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case TIMING_INTEG_101ms:
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case TIMING_INTEG_402ms:
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case TIMING6x_INTEG_13_7ms:
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case TIMING6x_INTEG_101ms:
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case TIMING6x_INTEG_402ms:
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break;
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default:
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@ -595,8 +595,8 @@ tsllux_set_gain(struct tsllux_softc *sc, uint8_t gain)
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int error;
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switch (gain) {
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case TIMING_GAIN_1X:
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case TIMING_GAIN_16X:
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case TIMING6x_GAIN_1X:
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case TIMING6x_GAIN_16X:
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break;
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default:
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@ -630,17 +630,17 @@ tsllux_wait_for_adcs(struct tsllux_softc *sc)
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int ms;
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switch (sc->sc_itime) {
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case TIMING_INTEG_13_7ms:
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case TIMING6x_INTEG_13_7ms:
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/* Wait 15ms for 13.7ms integration */
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ms = 15;
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break;
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case TIMING_INTEG_101ms:
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case TIMING6x_INTEG_101ms:
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/* Wait 120ms for 101ms integration */
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ms = 120;
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break;
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case TIMING_INTEG_402ms:
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case TIMING6x_INTEG_402ms:
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default:
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/* Wait 450ms for 402ms integration */
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ms = 450;
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@ -757,17 +757,17 @@ tsllux_get_sensor_data(struct tsllux_softc *sc, uint16_t *broadband,
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/* Set the hi / lo threshold based on current integration time. */
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switch (sc->sc_itime) {
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case TIMING_INTEG_13_7ms:
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case TIMING6x_INTEG_13_7ms:
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hi = TSL2561_AGC_THI_13MS;
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lo = TSL2561_AGC_TLO_13MS;
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break;
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case TIMING_INTEG_101ms:
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case TIMING6x_INTEG_101ms:
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hi = TSL2561_AGC_THI_101MS;
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lo = TSL2561_AGC_TLO_101MS;
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break;
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case TIMING_INTEG_402ms:
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case TIMING6x_INTEG_402ms:
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default:
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hi = TSL2561_AGC_THI_402MS;
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lo = TSL2561_AGC_TLO_402MS;
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@ -779,19 +779,19 @@ tsllux_get_sensor_data(struct tsllux_softc *sc, uint16_t *broadband,
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goto out;
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if (did_adjust_gain == false) {
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if (adc0 < lo && sc->sc_gain == TIMING_GAIN_1X) {
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if (adc0 < lo && sc->sc_gain == TIMING6x_GAIN_1X) {
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/* Increase the gain and try again. */
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if ((error =
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tsllux_set_gain0(sc,
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TIMING_GAIN_16X)) != 0)
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TIMING6x_GAIN_16X)) != 0)
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goto out;
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did_adjust_gain = true;
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} else if (adc0 > hi &&
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sc->sc_gain == TIMING_GAIN_16X) {
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sc->sc_gain == TIMING6x_GAIN_16X) {
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/* Decrease the gain and try again. */
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if ((error =
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tsllux_set_gain0(sc,
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TIMING_GAIN_1X)) != 0)
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TIMING6x_GAIN_1X)) != 0)
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goto out;
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did_adjust_gain = true;
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} else {
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@ -955,15 +955,15 @@ tsllux_get_lux(struct tsllux_softc *sc, uint32_t *luxp,
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* just return a "max brightness" value.
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*/
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switch (sc->sc_itime) {
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case TIMING_INTEG_13_7ms:
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case TIMING6x_INTEG_13_7ms:
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clip_threshold = TSL2561_CLIPPING_13MS;
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break;
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case TIMING_INTEG_101ms:
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case TIMING6x_INTEG_101ms:
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clip_threshold = TSL2561_CLIPPING_101MS;
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break;
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case TIMING_INTEG_402ms:
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case TIMING6x_INTEG_402ms:
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default:
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clip_threshold = TSL2561_CLIPPING_402MS;
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break;
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@ -976,21 +976,21 @@ tsllux_get_lux(struct tsllux_softc *sc, uint32_t *luxp,
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/* Get correct scale factor based on integration time. */
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switch (sc->sc_itime) {
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case TIMING_INTEG_13_7ms:
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case TIMING6x_INTEG_13_7ms:
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scale = TSL2561_LUX_CHSCALE_TINT0;
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break;
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case TIMING_INTEG_101ms:
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case TIMING6x_INTEG_101ms:
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scale = TSL2561_LUX_CHSCALE_TINT1;
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break;
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case TIMING_INTEG_402ms:
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case TIMING6x_INTEG_402ms:
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default:
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scale = (1 << TSL2561_LUX_CHSCALE);
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}
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/* Scale for gain. */
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if (sc->sc_gain == TIMING_GAIN_1X)
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if (sc->sc_gain == TIMING6x_GAIN_1X)
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scale <<= 4;
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/* Scale the channel values. */
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@ -1,4 +1,4 @@
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/* $NetBSD: tsl256xreg.h,v 1.1 2018/05/27 05:31:20 thorpej Exp $ */
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/* $NetBSD: tsl256xreg.h,v 1.2 2021/01/04 21:59:48 thorpej Exp $ */
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/*-
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* Copyright (c) 2018 Jason R. Thorpe
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@ -53,28 +53,28 @@
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*/
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/* COMMAND - Specifies register address and other parameters */
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#define COMMAND_REGMASK 0x0f /* register address mask */
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#define COMMAND_BLOCK 0x10 /* transaction uses block read/write */
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#define COMMAND_WORD 0x20 /* transaction uses word read/write */
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#define COMMAND_CLEAR 0x40 /* clear pending interrupt */
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#define COMMAND_CMD 0x80 /* Select command register; MBO */
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#define COMMAND6x_REGMASK 0x0f /* register address mask */
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#define COMMAND6x_BLOCK 0x10 /* transaction uses block read/write */
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#define COMMAND6x_WORD 0x20 /* transaction uses word read/write */
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#define COMMAND6x_CLEAR 0x40 /* clear pending interrupt */
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#define COMMAND6x_CMD 0x80 /* Select command register; MBO */
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/* CONTROL - Control of basic functions */
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#define TSL256x_REG_CONTROL 0x0
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#define CONTROL_POWER_OFF 0x00
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#define CONTROL_POWER_ON 0x03
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#define CONTROL6x_POWER_OFF 0x00
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#define CONTROL6x_POWER_ON 0x03
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/* TIMING - Integration time / gain control */
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#define TSL256x_REG_TIMING 0x1
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#define TIMING_INTEG_13_7ms 0x00 /* 13.7ms integration time */
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#define TIMING_INTEG_101ms 0x01 /* 101ms integration time */
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#define TIMING_INTEG_402ms 0x02 /* 402ms integration time */
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#define TIMING_INTEG_MANUAL 0x03 /* use manual timing */
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#define TIMING_MANUAL 0x08 /* manual timing; 1 starts, 0 stops */
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#define TIMING_GAIN_1X 0x00
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#define TIMING_GAIN_16X 0x10
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#define TIMING6x_INTEG_13_7ms 0x00 /* 13.7ms integration time */
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#define TIMING6x_INTEG_101ms 0x01 /* 101ms integration time */
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#define TIMING6x_INTEG_402ms 0x02 /* 402ms integration time */
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#define TIMING6x_INTEG_MANUAL 0x03 /* use manual timing */
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#define TIMING6x_MANUAL 0x08 /* manual timing; 1 starts, 0 stops */
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#define TIMING6x_GAIN_1X 0x00
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#define TIMING6x_GAIN_16X 0x10
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/* THRESHLOWLOW - Low byte of low interrupt threshold */
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@ -95,10 +95,10 @@
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/* INTERRUPT - Interrupt control */
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#define TSL256x_REG_INTERRUPT 0x6
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#define INTERRUPT_LEVEL 0x01 /* Level-triggered interrupt */
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#define INTERRUPT_SMB_ALERT 0x02 /* SMB Alert compliant interrupt */
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#define INTERRUPT_TEST 0x03 /* interrupt test */
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#define INTERRUPT_PERSIST(x) ((x) << 4)
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#define INTERRUPT6x_LEVEL 0x01 /* Level-triggered interrupt */
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#define INTERRUPT6x_SMB_ALERT 0x02 /* SMB Alert compliant interrupt */
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#define INTERRUPT6x_TEST 0x03 /* interrupt test */
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#define INTERRUPT6x_PERSIST(x) ((x) << 4)
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/*
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* Interrupt persist settings:
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* 0 - Every ADC cycle generates an interrupt
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@ -118,10 +118,10 @@
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/* ID - Part number / Rev ID */
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#define TSL256x_REG_ID 0xa
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#define ID_GET_PARTNO(x) (((x) & 0xf0) >> 4)
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#define ID_PARTNO_TSL2560 0x0
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#define ID_PARTNO_TSL2561 0x1
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#define ID_GET_REVNO(x) ((x) & 0x0f)
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#define ID6x_GET_PARTNO(x) (((x) & 0xf0) >> 4)
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#define ID6x_PARTNO_TSL2560 0x0
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#define ID6x_PARTNO_TSL2561 0x1
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#define ID6x_GET_REVNO(x) ((x) & 0x0f)
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/* 0xb - Reserved */
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