diff --git a/sys/dev/pci/if_sip.c b/sys/dev/pci/if_sip.c index 7681fac0f5aa..bdf8336d6b22 100644 --- a/sys/dev/pci/if_sip.c +++ b/sys/dev/pci/if_sip.c @@ -1,4 +1,4 @@ -/* $NetBSD: if_sip.c,v 1.45 2002/02/09 21:04:02 thorpej Exp $ */ +/* $NetBSD: if_sip.c,v 1.46 2002/02/28 19:10:16 thorpej Exp $ */ /*- * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. @@ -82,7 +82,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.45 2002/02/09 21:04:02 thorpej Exp $"); +__KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.46 2002/02/28 19:10:16 thorpej Exp $"); #include "bpfilter.h" @@ -145,6 +145,12 @@ __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.45 2002/02/09 21:04:02 thorpej Exp $"); #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) +#if defined(DP83020) +#define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO +#else +#define TX_DMAMAP_SIZE MCLBYTES +#endif + /* * Receive descriptor list size. We have one Rx buffer per incoming * packet, so this logic is a little simpler. @@ -588,6 +594,17 @@ SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) sc->sc_model = sip; + /* + * XXX Work-around broken PXE firmware on some boards. + * + * The DP83815 shares an address decoder with the MEM BAR + * and the ROM BAR. Make sure the ROM BAR is disabled, + * so that memory mapped access works. + */ + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, + pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & + ~PCI_MAPREG_ROM_ENABLE); + /* * Map the device. */ @@ -711,7 +728,7 @@ SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) * Create the transmit buffer DMA maps. */ for (i = 0; i < SIP_TXQUEUELEN; i++) { - if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, + if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, SIP_NTXSEGS, MCLBYTES, 0, 0, &sc->sc_txsoft[i].txs_dmamap)) != 0) { printf("%s: unable to create tx DMA map %d, " @@ -870,6 +887,40 @@ SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) if_attach(ifp); ether_ifattach(ifp, enaddr); + /* + * The number of bytes that must be available in + * the Tx FIFO before the bus master can DMA more + * data into the FIFO. + */ + sc->sc_tx_fill_thresh = 64 / 32; + + /* + * Start at a drain threshold of 512 bytes. We will + * increase it if a DMA underrun occurs. + * + * XXX The minimum value of this variable should be + * tuned. We may be able to improve performance + * by starting with a lower value. That, however, + * may trash the first few outgoing packets if the + * PCI bus is saturated. + */ + sc->sc_tx_drain_thresh = 512 / 32; + + /* + * Initialize the Rx FIFO drain threshold. We want to start + * dumping the packet into memory very quickly, especially + * at Gigabot speeds (the value we use is very aggressive). + * This is in units of 8 bytes. + * + * We should never set this value lower than 2; 14 bytes are + * required to filter the packet. + */ +#if 0 + sc->sc_rx_drain_thresh = 4; +#else + sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; +#endif + #ifdef SIP_EVENT_COUNTERS /* * Attach event counters. @@ -2076,31 +2127,6 @@ SIP_DECL(init)(struct ifnet *ifp) */ bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); - /* - * Initialize the transmit fill and drain thresholds if - * we have never done so. - */ - if (sc->sc_tx_fill_thresh == 0) { - /* - * XXX This value should be tuned. We may be able to - * improve performance by increasing it. - */ - sc->sc_tx_fill_thresh = 64/32; - } - if (sc->sc_tx_drain_thresh == 0) { - /* - * Start at a drain threshold of 512 bytes. We will - * increase it if a DMA underrun occurs. - * - * XXX The minimum value of this variable should be - * tuned. We may be able to improve performance - * by starting with a lower value. That, however, - * may trash the first few outgoing packets if the - * PCI bus is saturated. - */ - sc->sc_tx_drain_thresh = 512 / 32; - } - /* * Initialize the prototype TXCFG register. */