Lots and lots of fixes to the cpu identification code, and dealing with
L2 and L3 cache initialization. Mostly to get the L2 enabled on the pegasos, but since I had the manual, I fixed a few other things I saw while I was there.
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu_subr.c,v 1.35 2007/11/17 08:30:35 kefren Exp $ */
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/* $NetBSD: cpu_subr.c,v 1.36 2007/12/27 05:40:49 garbled Exp $ */
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/*-
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* Copyright (c) 2001 Matt Thomas.
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.35 2007/11/17 08:30:35 kefren Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.36 2007/12/27 05:40:49 garbled Exp $");
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#include "opt_ppcparam.h"
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#include "opt_multiprocessor.h"
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@ -83,6 +83,8 @@ static const struct fmttab cpu_7450_l2cr_formats[] = {
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{ L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
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{ L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
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{ L2CR_L2E, ~0, " 256KB L2 cache" },
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{ L2CR_L2PE, 0, " no parity" },
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{ L2CR_L2PE, ~0, " parity enabled" },
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{ 0, 0, NULL }
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};
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@ -92,6 +94,8 @@ static const struct fmttab cpu_7448_l2cr_formats[] = {
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{ L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
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{ L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
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{ L2CR_L2E, ~0, " 1MB L2 cache" },
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{ L2CR_L2PE, 0, " no parity" },
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{ L2CR_L2PE, ~0, " parity enabled" },
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{ 0, 0, NULL }
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};
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@ -101,6 +105,8 @@ static const struct fmttab cpu_7457_l2cr_formats[] = {
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{ L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
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{ L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
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{ L2CR_L2E, ~0, " 512KB L2 cache" },
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{ L2CR_L2PE, 0, " no parity" },
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{ L2CR_L2PE, ~0, " parity enabled" },
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{ 0, 0, NULL }
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};
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@ -540,14 +546,23 @@ cpu_setup(self, ci)
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cpu_probe_speed(ci);
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aprint_normal("%u.%02u MHz",
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ci->ci_khz / 1000, (ci->ci_khz / 10) % 100);
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if (vers == IBM750FX || vers == MPC750 ||
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vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) {
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if (MPC745X_P(vers)) {
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cpu_config_l3cr(vers);
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} else {
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cpu_config_l2cr(pvr);
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}
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switch (vers) {
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case IBM750FX:
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case MPC750:
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case MPC7400:
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case MPC7410:
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cpu_config_l3cr(vers);
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break;
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case MPC7450: /* 7441 does not have L3! */
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case MPC7455: /* 7445 does not have L3! */
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case MPC7457: /* 7447 does not have L3! */
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/* do something special XXX */
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case MPC7447A:
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case MPC7448:
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cpu_config_l2cr(pvr);
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break;
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default:
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break;
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}
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aprint_normal("\n");
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break;
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@ -612,6 +627,16 @@ cpu_setup(self, ci)
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NULL, self->dv_xname, "IPIs");
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}
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/*
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* According to a document labeled "PVR Register Settings":
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** For integrated microprocessors the PVR register inside the device
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** will identify the version of the microprocessor core. You must also
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** read the Device ID, PCI register 02, to identify the part and the
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** Revision ID, PCI register 08, to identify the revision of the
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** integrated microprocessor.
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* This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014
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*/
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void
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cpu_identify(char *str, size_t len)
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{
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@ -630,8 +655,12 @@ cpu_identify(char *str, size_t len)
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minor = (pvr >> 0) & 0xff;
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major = minor <= 4 ? 1 : 2;
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break;
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case MPCG2: /*XXX see note above */
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major = (pvr >> 4) & 0xf;
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minor = (pvr >> 0) & 0xf;
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break;
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default:
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major = (pvr >> 4) & 0xf;
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major = (pvr >> 8) & 0xf;
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minor = (pvr >> 0) & 0xf;
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}
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@ -708,7 +737,7 @@ cpu_enable_l2cr(register_t l2cr)
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mtspr(SPR_L2CR, l2cr | L2CR_L2I);
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do {
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x = mfspr(SPR_L2CR);
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} while (x & L2CR_L2IP);
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} while (x & L2CR_L2I);
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/* Enable L2 cache. */
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l2cr |= L2CR_L2E;
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@ -768,6 +797,7 @@ void
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cpu_config_l2cr(int pvr)
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{
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register_t l2cr;
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u_int vers = (pvr >> 16) & 0xffff;
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l2cr = mfspr(SPR_L2CR);
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@ -792,14 +822,33 @@ cpu_config_l2cr(int pvr)
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aprint_normal(" L2 cache present but not enabled ");
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return;
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}
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aprint_normal(",");
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if ((pvr >> 16) == IBM750FX ||
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(pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ ||
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(pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) {
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switch (vers) {
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case IBM750FX:
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cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr);
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} else {
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break;
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case MPC750:
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if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ ||
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(pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */)
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cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr);
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else
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cpu_fmttab_print(cpu_l2cr_formats, l2cr);
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break;
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case MPC7447A:
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case MPC7457:
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cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr);
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return;
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case MPC7448:
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cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr);
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return;
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case MPC7450:
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case MPC7455:
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cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr);
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break;
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default:
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cpu_fmttab_print(cpu_l2cr_formats, l2cr);
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break;
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}
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}
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