Sort definitions. No functional change.
- CPUID_FEAT_BLACKLIST is for Fn00000001 %edx, so move it. - Sort CPUID definitions with initial EAX value.
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msaitoh
parent
b688898b59
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07c34455c2
@ -1,4 +1,4 @@
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/* $NetBSD: specialreg.h,v 1.69 2013/10/04 17:21:43 msaitoh Exp $ */
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/* $NetBSD: specialreg.h,v 1.70 2013/10/04 17:53:19 msaitoh Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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@ -137,6 +137,75 @@
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"\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
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"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"
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/* Blacklists of CPUID flags - used to mask certain features */
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#ifdef XEN
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/* Not on Xen */
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#define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
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#else
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#define CPUID_FEAT_BLACKLIST 0
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#endif /* XEN */
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/*
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* CPUID "features" bits in Fn00000001 %ecx
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*/
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#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
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#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
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#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
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#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
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#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
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#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
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#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
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#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
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#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
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#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
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#define CPUID2_CID 0x00000400 /* Context ID */
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/* bit 11 unused 0x00000800 */
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#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
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#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
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#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
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#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
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/* bit 16 unused 0x00010000 */
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#define CPUID2_PCID 0x00020000 /* Process Context ID */
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#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
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#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
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#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
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#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
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#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
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#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
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#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
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#define CPUID2_AES 0x02000000 /* AES instructions */
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#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
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#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
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#define CPUID2_AVX 0x10000000 /* AVX instructions */
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#define CPUID2_F16C 0x20000000 /* half precision conversion */
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#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
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#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
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#define CPUID2_FLAGS1 "\20" \
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"\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
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"\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
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"\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "B11" \
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"\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
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"\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
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"\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
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"\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
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"\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ"
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#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
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#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
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#define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
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/*
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* The Extended family bits should only be inspected when CPUID2FAMILY()
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* returns 15. They are use to encode family value 16 to 270 (add 15).
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* The Extended model hits are the high 4 bits of the model.
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* They are only valid for family >= 15 or family 6 (intel, but all amd
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* family 6 are documented to return zero bits for them).
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*/
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#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
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#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
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/*
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* Intel Digital Thermal Sensor and
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* Power Management, Fn0000_0006 - %eax.
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@ -197,6 +266,40 @@
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"\32" "PT" "\33" "AVX512PF""\34" "AVX512ER"\
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"\35" "AVX512CD""\36" "SHA"
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/*
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* CPUID Processor extended state Enumeration Fn0000000d %eax
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*
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* Extended Control Register XCR0
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*/
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#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
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#define XCR0_SSE 0x00000002 /* SSE state */
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#define XCR0_AVX 0x00000004 /* AVX state (ymmn registers) */
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#define XCR0_FLAGS1 "\20" \
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"\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "B03"
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/*
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* CPUID Processor extended state Enumeration Fn0000000d
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*
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* %ecx == 0: supported features info:
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* %edx:%eax bits valid for XCR0
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* %ebx Save area size for features enabled in XCR0
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* %ecx Maximim save area size for all cpu features
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*
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* %ecx == 1: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
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*
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* %ecx >= 2: Save area details for XCR0 bit n
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* %eax: size of save area for this feature
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* %ebx: offset of save area for this feature
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* %ecx, %edx: reserved
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* All of %eax, %ebx, %ecx and %edx zero for unsupported features.
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*/
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#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
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#define CPUID_PES1_FLAGS "\20" \
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"\1" "XSAVEOPT"
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/* Intel Fn80000001 extended features - %edx */
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#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
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#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
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@ -267,24 +370,6 @@
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"\31" "B24" "\32" "B25" "\33" "B26" "\34" "B27" \
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"\35" "B28" "\36" "B29" "\37" "B30" "\40" "B31"
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/* AMD Fn8000000a %edx features (SVM features) */
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#define CPUID_AMD_SVM_NP 0x00000001
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#define CPUID_AMD_SVM_LbrVirt 0x00000002
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#define CPUID_AMD_SVM_SVML 0x00000004
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#define CPUID_AMD_SVM_NRIPS 0x00000008
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#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
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#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
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#define CPUID_AMD_SVM_FlushByASID 0x00000040
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#define CPUID_AMD_SVM_DecodeAssist 0x00000080
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#define CPUID_AMD_SVM_PauseFilter 0x00000400
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#define CPUID_AMD_SVM_FLAGS "\20" \
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"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
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"\5" "TSCRate" "\6" "VMCBCleanBits" \
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"\7" "FlushByASID" "\10" "DecodeAssist" \
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"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
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"\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \
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"\21" "B19"
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/*
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* AMD Advanced Power Management
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* CPUID Fn8000_0007 %edx
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@ -307,6 +392,24 @@
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"\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \
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"\15" "B12"
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/* AMD Fn8000000a %edx features (SVM features) */
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#define CPUID_AMD_SVM_NP 0x00000001
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#define CPUID_AMD_SVM_LbrVirt 0x00000002
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#define CPUID_AMD_SVM_SVML 0x00000004
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#define CPUID_AMD_SVM_NRIPS 0x00000008
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#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
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#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
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#define CPUID_AMD_SVM_FlushByASID 0x00000040
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#define CPUID_AMD_SVM_DecodeAssist 0x00000080
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#define CPUID_AMD_SVM_PauseFilter 0x00000400
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#define CPUID_AMD_SVM_FLAGS "\20" \
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"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
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"\5" "TSCRate" "\6" "VMCBCleanBits" \
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"\7" "FlushByASID" "\10" "DecodeAssist" \
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"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
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"\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \
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"\21" "B19"
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/*
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* Centaur Extended Feature flags
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*/
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@ -325,109 +428,6 @@
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"\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \
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"\15" "RSA"
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/*
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* CPUID "features" bits in Fn00000001 %ecx
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*/
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#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
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#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
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#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
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#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
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#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
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#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
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#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
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#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
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#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
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#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
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#define CPUID2_CID 0x00000400 /* Context ID */
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/* bit 11 unused 0x00000800 */
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#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
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#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
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#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
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#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
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/* bit 16 unused 0x00010000 */
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#define CPUID2_PCID 0x00020000 /* Process Context ID */
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#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
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#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
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#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
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#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
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#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
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#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
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#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
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#define CPUID2_AES 0x02000000 /* AES instructions */
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#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
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#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
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#define CPUID2_AVX 0x10000000 /* AVX instructions */
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#define CPUID2_F16C 0x20000000 /* half precision conversion */
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#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
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#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
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#define CPUID2_FLAGS1 "\20" \
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"\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
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"\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
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"\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "B11" \
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"\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
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"\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
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"\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
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"\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
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"\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ"
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#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
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#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
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#define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
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/*
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* The Extended family bits should only be inspected when CPUID2FAMILY()
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* returns 15. They are use to encode family value 16 to 270 (add 15).
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* The Extended model hits are the high 4 bits of the model.
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* They are only valid for family >= 15 or family 6 (intel, but all amd
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* family 6 are documented to return zero bits for them).
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*/
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#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
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#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
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/* Blacklists of CPUID flags - used to mask certain features */
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#ifdef XEN
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/* Not on Xen */
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#define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
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#else
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#define CPUID_FEAT_BLACKLIST 0
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#endif /* XEN */
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/*
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* CPUID Processor extended state Enumeration Fn0000000d %eax
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*
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* Extended Control Register XCR0
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*/
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#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
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#define XCR0_SSE 0x00000002 /* SSE state */
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#define XCR0_AVX 0x00000004 /* AVX state (ymmn registers) */
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#define XCR0_FLAGS1 "\20" \
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"\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "B03"
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/*
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* CPUID Processor extended state Enumeration Fn0000000d
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*
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* %ecx == 0: supported features info:
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* %edx:%eax bits valid for XCR0
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* %ebx Save area size for features enabled in XCR0
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* %ecx Maximim save area size for all cpu features
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*
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* %ecx == 1: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
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*
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* %ecx >= 2: Save area details for XCR0 bit n
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* %eax: size of save area for this feature
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* %ebx: offset of save area for this feature
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* %ecx, %edx: reserved
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* All of %eax, %ebx, %ecx and %edx zero for unsupported features.
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*/
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#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
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#define CPUID_PES1_FLAGS "\20" \
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"\1" "XSAVEOPT"
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/*
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* Model-specific registers for the i386 family
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*/
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