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make REGVAL macros use volatile pointers

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This commit is contained in:
cgd 1997-06-03 21:54:02 +00:00
parent ba43d7fec5
commit 079e0c6bff
4 changed files with 10 additions and 10 deletions
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4
sys/arch/alpha/pci/apecsreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: apecsreg.h,v 1.5 1997/04/07 01:59:51 cgd Exp $ */
/* $NetBSD: apecsreg.h,v 1.6 1997/06/03 21:54:02 cgd Exp $ */
/*
* Copyright (c) 1995 Carnegie-Mellon University.
@ -34,7 +34,7 @@
* Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38.
*/
#define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r))
#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
/*
* Base addresses

6
sys/arch/alpha/pci/ciareg.h
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@ -1,4 +1,4 @@
/* $NetBSD: ciareg.h,v 1.8 1997/04/07 01:59:54 cgd Exp $ */
/* $NetBSD: ciareg.h,v 1.9 1997/06/03 21:54:04 cgd Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
@ -30,10 +30,10 @@
/*
* 21171 Chipset registers and constants.
*
* Taken from XXX
* Taken from EC-QE18B-TE.
*/
#define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r))
#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
/*
* Base addresses

4
sys/arch/alpha/pci/dwlpxreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: dwlpxreg.h,v 1.4 1997/04/16 22:20:52 mjacob Exp $ */
/* $NetBSD: dwlpxreg.h,v 1.5 1997/06/03 21:54:05 cgd Exp $ */
/*
* Copyright (c) 1997 by Matthew Jacob
@ -42,7 +42,7 @@
* Order Number EK-T8030-TM. A01''
*/
#define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r))
#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
/*
* There are (potentially) 4 I/O hoses, and there are three

6
sys/arch/alpha/pci/lcareg.h
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@ -1,4 +1,4 @@
/* $NetBSD: lcareg.h,v 1.5 1997/04/07 01:59:58 cgd Exp $ */
/* $NetBSD: lcareg.h,v 1.6 1997/06/03 21:54:06 cgd Exp $ */
/*
* Copyright (c) 1995 Carnegie-Mellon University.
@ -31,8 +31,8 @@
* 21066 chip registers
*/
#define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r))
#define REGVAL64(r) (*(int64_t *)ALPHA_PHYS_TO_K0SEG(r))
#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
/*
* Base addresses