improve register descriptions
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nisimura
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@ -1,4 +1,4 @@
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/* $NetBSD: dm9000reg.h,v 1.4 2020/03/31 02:32:25 nisimura Exp $ */
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/* $NetBSD: dm9000reg.h,v 1.5 2020/10/08 11:29:04 nisimura Exp $ */
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/*
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* Copyright (c) 2009 Paul Fleischer
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@ -47,77 +47,92 @@
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#define DM9000_IOSIZE 4
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#define DM9000_NCR 0x00
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#define DM9000_NCR 0x00 /* "network" control */
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#define DM9000_NCR_RST (1<<0) /* reset chip, self clear */
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#define DM9000_NCR_LBK_MASK (0x06)
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#define DM9000_NCR_LBK_MASK (0x06) /* loopback test selection */
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#define DM9000_NCR_LBK_SHIFT (1)
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#define DM9000_NCR_LBK_MAC_INTERNAL (1<<DM9000_NCR_LBK_SHIFT)
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#define DM9000_NCR_LBK_NORMAL (0<<DM9000_NCR_LBK_SHIFT)
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#define DM9000_NCR_LBK_INT_PHY (2<<DM9000_NCR_LBK_SHIFT)
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#define DM9000_NCR_FDX (1<<3) /* activate PAUSE flow control */
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#define DM9000_NCR_FCOL (1<<4)
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#define DM9000_NCR_WAKEEN (1<<6)
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#define DM9000_NCR_EXY_PHY (1<<7)
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#define DM9000_NSR 0x01
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#define DM9000_NCR_LBK_NORMAL (0<<1) /* normal operation */
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#define DM9000_NCR_LBK_MAC_INTERNAL (1<<1) /* MAC loopback */
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#define DM9000_NCR_LBK_INT_PHY (2<<1) /* PHY loopback */
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#define DM9000_NCR_FDX (1<<3) /* use full-duplex, RO when int PHY */
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#define DM9000_NCR_FCOL (1<<4) /* force coll. mode. test only */
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#define DM9000_NCR_WAKEEN (1<<6) /* wakeup event enable */
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#define DM9000_NCR_EXY_PHY (1<<7) /* select ext. PHY, immune SW reset */
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#define DM9000_NSR 0x01 /* "network" status */
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#define DM9000_NSR_RXOV (1<<1) /* receive overflow deteced */
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#define DM9000_NSR_TX1END (1<<2) /* transmit 1 completed */
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#define DM9000_NSR_TX2END (1<<3) /* transmit 2 completed */
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#define DM9000_NSR_WAKEST (1<<5)
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#define DM9000_NSR_LINKST (1<<6) /* link up detected */
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#define DM9000_NSR_TX1END (1<<2) /* transmit 1 completed, W1C */
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#define DM9000_NSR_TX2END (1<<3) /* transmit 2 completed, W1C */
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#define DM9000_NSR_WAKEST (1<<5) /* wakeup event, W1C */
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#define DM9000_NSR_LINKST (1<<6) /* link is up */
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#define DM9000_NSR_SPEED (1<<7) /* 1: 100Mbps, 0: 10Mbps */
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#define DM9000_TCR 0x02
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#define DM9000_TCR 0x02 /* Tx control */
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#define DM9000_TCR_TXREQ (1<<0) /* request to start Tx, self clear */
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#define DM9000_TCR_CRC_DIS1 (1<<1)
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#define DM9000_TCR_PAD_DIS1 (1<<2)
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#define DM9000_TCR_CRC_DIS2 (1<<3)
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#define DM9000_TCR_PAD_DIS2 (1<<4)
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#define DM9000_TCR_EXCECM (1<<5)
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#define DM9000_TCR_TJDIS (1<<6)
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#define DM9000_TCR_CRC_DIS1 (1<<1) /* disable PAD op on Tx1 */
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#define DM9000_TCR_PAD_DIS1 (1<<2) /* disbale CRC append on Tx1 */
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#define DM9000_TCR_CRC_DIS2 (1<<3) /* disable PAD op on Tx2 */
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#define DM9000_TCR_PAD_DIS2 (1<<4) /* disbale CRC append on Tx2 */
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#define DM9000_TCR_EXCECM (1<<5) /* allow infinate colli. retries */
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#define DM9000_TCR_TJDIS (1<<6) /* disable xmit jabber, otherwise on */
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#define DM9000_TSR1 0x03 /* transmit completion status 1 */
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#define DM9000_TSR2 0x04 /* transmit completion status 2 */
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#define DM9000_RCR 0x05
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#define DM9000_TSR_EC (1<<2) /* aborted after 16 collision */
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#define DM9000_TSR_COL (1<<3) /* collision detected while xmit */
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#define DM9000_TSR_LCOL (1<<4) /* out of window "late" collision */
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#define DM9000_TSR_NC (1<<5) /* no carrier signal found */
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#define DM9000_TSR_CLOSS (1<<6) /* loss of carrier */
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#define DM9000_TSR_TJTO (1<<7) /* Tx jabber time out */
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#define DM9000_RCR 0x05 /* Rx control */
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#define DM9000_RCR_RXEN (1<<0) /* activate Rx */
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#define DM9000_RCR_PRMSC (1<<1) /* enable promisc mode */
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#define DM9000_RCR_RUNT (1<<2) /* allow to receive runt frame */
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#define DM9000_RCR_RUNT (1<<2) /* accept damaged runt frame */
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#define DM9000_RCR_ALL (1<<3) /* accept all multicast */
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#define DM9000_RCR_DIS_CRC (1<<4) /* drop bad CRC frame */
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#define DM9000_RCR_DIS_LONG (1<<5) /* drop too long frame (>1522) */
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#define DM9000_RCR_WTDIS (1<<6) /* disable Rx watchdog timer */
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#define DM9000_RSR 0x06
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#define DM9000_RCR_DIS_LONG (1<<5) /* drop too long frame >1522 */
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#define DM9000_RCR_WTDIS (1<<6) /* disable >2048 Rx detect timer */
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#define DM9000_RSR 0x06 /* Rx status */
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#define DM9000_RSR_FOE (1<<0) /* Rx FIFO overflow detected */
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#define DM9000_RSR_CE (1<<1)
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#define DM9000_RSR_AE (1<<2)
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#define DM9000_RSR_PLE (1<<3)
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#define DM9000_RSR_RWTO (1<<4)
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#define DM9000_RSR_LCS (1<<5)
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#define DM9000_RSR_CE (1<<1) /* CRC error found */
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#define DM9000_RSR_AE (1<<2) /* tail not ended in byte boundary */
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#define DM9000_RSR_PLE (1<<3) /* physical layer error */
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#define DM9000_RSR_RWTO (1<<4) /* >2048 condition detected */
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#define DM9000_RSR_LCS (1<<5) /* late colli. detected */
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#define DM9000_RSR_MF (1<<6) /* mcast/bcast frame received */
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#define DM9000_RSR_RF (1<<7) /* runt frame received (<64 bytes) */
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#define DM9000_ROCR 0x07
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#define DM9000_BPTR 0x08
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#define DM9000_FCTR 0x09
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#define DM9000_FCR 0x0A
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#define DM9000_RSR_RF (1<<7) /* damaged runt frame received <64 */
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#define DM9000_ROCR 0x07 /* receive overflow counter */
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/* 7: OVF detected, 6:0 statistic couner */
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#define DM9000_BPTR 0x08 /* back pressure threshold */
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/* 7:4 back pressure high watermark (3 def), 3:0 jam pattern time (7 def) */
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#define DM9000_FCTR 0x09 /* flow control threshold */
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/* 7:4 Rx FIFO high w.m. (3 def), low w.m. (8 def) */
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#define DM9000_FCR 0x0A /* Rx flow control */
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#define DM9000_FCR_FLCE (1<<0) /* flow control enable */
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#define DM9000_FCR_RXPCS (1<<1) /* Rx PAUSE current status */
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#define DM9000_FCR_RXPS (1<<2) /* Rx PAUSE status, read to clear */
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#define DM9000_FCR_BKPM (1<<3)
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#define DM9000_FCR_BKPA (1<<4)
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#define DM9000_FCR_TXPEN (1<<5) /* force PAUSE/unPAUSE */
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#define DM9000_FCR_TXPF (1<<6) /* Tx PAUSE packet (when full */
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#define DM9000_FCR_RXPS (1<<2) /* Rx PAUSE status, latched R2C */
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#define DM9000_FCR_BKPM (1<<3) /* HDX back pressure for my frames */
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#define DM9000_FCR_BKPA (1<<4) /* HDX back pressure for any frames */
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#define DM9000_FCR_TXPEN (1<<5) /* activate auto PAUSE operation */
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#define DM9000_FCR_TXPF (1<<6) /* Tx PAUSE packet (when full) */
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#define DM9000_FCR_TXP0 (1<<7) /* Tx PAUSE packet (when empty) */
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#define DM9000_EPCR 0x0B
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#define DM9000_EPCR 0x0B /* EEPROM / PHY control */
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#define DM9000_EPCR_ERRE (1<<0) /* operation in progress, busy bit */
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#define DM9000_EPCR_ERPRW (1<<1) /* instruct to write */
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#define DM9000_EPCR_ERPRR (1<<2) /* instruct to read */
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#define DM9000_EPCR_EPOS_EEPROM (0<<3) /* 1: PHY op, 0: EEPROM op */
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#define DM9000_EPCR_EPOS_PHY (1<<3)
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#define DM9000_EPCR_WEP (1<<4)
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#define DM9000_EPCR_REEP (1<<5)
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#define DM9000_EPAR 0x0C /* 7:6 (!!) PHY id, 5:0 reg num */
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#define DM9000_EPAR_EROA_MASK 0x3F /* bits 0-5 */
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#define DM9000_EPCR_ERPRW (1<<1) /* instruct to write, not SC */
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#define DM9000_EPCR_ERPRR (1<<2) /* instruct to read, not SC */
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#define DM9000_EPCR_EPOS_EEPROM (0<<3) /* EEPROM operation */
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#define DM9000_EPCR_EPOS_PHY (1<<3) /* PHY operation */
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#define DM9000_EPCR_WEP (1<<4) /* EEPROM write enable */
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#define DM9000_EPCR_REEP (1<<5) /* reload EEPROM contents, not SC */
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#define DM9000_EPAR 0x0C /* EEPROM / PHY address */
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#define DM9000_EPAR_EROA_MASK 0x3F /* 7:6 (!!) PHY id, 5:0 addr/reg */
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#define DM9000_EPAR_INT_PHY 0x40 /* EPAR[7:6] = 01 for internal PHY */
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#define DM9000_EPDRL 0x0D /* data 7:0 */
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#define DM9000_EPDRH 0x0E /* data 15:8 */
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#define DM9000_WCR 0x0F
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#define DM9000_EPDRL 0x0D /* EEPROM / PHY data 7:0 */
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#define DM9000_EPDRH 0x0E /* EEPROM / PHY data 15:8 */
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#define DM9000_WCR 0x0F /* wakeup control and status */
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#define DM9000_MAGIC (1<<0) /* magic frame arrived */
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#define DM9000_SAMPLE (1<<1) /* sample frame arrived */
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#define DM9000_LINK (1<<2) /* link change / status change found */
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#define DM9000_MAGICEN (1<<3) /* enable magic frame event detect */
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#define DM9000_SMAPLEEN (1<<4) /* enable sample frame event detect */
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#define DM9000_LINKEN (1<<5) /* enable link change event detect */
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#define DM9000_PAB0 0x10 /* my station address 7:0 */
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#define DM9000_PAB1 0x11
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@ -135,46 +150,53 @@
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#define DM9000_MAB6 0x1C
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#define DM9000_MAB7 0x1D /* 63:56, needs 0x80 to catch bcast */
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#define DM9000_GPCR 0x1E
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#define DM9000_GPCR_GPIO0_OUT (1<<0)
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#define DM9000_GPR 0x1F
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#define DM9000_GPCR 0x1E /* GPIO control */
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#define DM9000_GPCR_GPIO0_OUT (1<<0) /* bit-0 to control PHY */
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/* 3:0 select pin I/O direction (0001 def) */
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#define DM9000_GPR 0x1F /* GPIO value to read / write */
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#define DM9000_GPR_PHY_PWROFF (1<<0) /* power down internal PHY */
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#define DM9000_TRPAL 0x22
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#define DM9000_TRPAH 0x23
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#define DM9000_RWPAL 0x24
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#define DM9000_RWPAH 0x25
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#define DM9000_TRPAL 0x22 /* Tx SRAM read pointer 7:0 */
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#define DM9000_TRPAH 0x23 /* Tx SRAM read pointer 15:8 */
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#define DM9000_RWPAL 0x24 /* Rx SRAM read pointer 7:0 */
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#define DM9000_RWPAH 0x25 /* Rx SRAM read pointer 15:8 */
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/* VID 0x0a46, PID 0x9000 */
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#define DM9000_VID0 0x28 /* vender ID 7:0 */
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#define DM9000_VID1 0x29 /* vender ID 15:8 */
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#define DM9000_PID0 0x2A /* product ID 7:0 */
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#define DM9000_PID1 0x2B /* product ID 15:8 */
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#define DM9000_CHIPR 0x2C /* chip revision */
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#define DM9000_CHIPR 0x2C
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#define DM9000_SMCR 0x2F
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#define DM9000_SMCR 0x2F /* "serial mode" control */
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#define DM9000_FB0 (1<<0) /* force shortest back-off time */
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#define DM9000_FB1 (1<<1) /* force longeset back-off time */
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#define DM9000_FLC (1<<2) /* force late collsion */
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#define DM9000_SM_EN (1<<7) /* serial mode enable */
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#define DM9000_MRCMDX 0xF0 /* "no increment" read byte */
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#define DM9000_MRCMD 0xF2 /* "auto increment" read byte */
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#define DM9000_MRRL 0xF4
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#define DM9000_MRRH 0xF5
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#define DM9000_MRRL 0xF4 /* memory read address 7:0 */
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#define DM9000_MRRH 0xF5 /* memory read address 15:8 */
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#define DM9000_MWCMDX 0xF6 /* "no increment" write byte */
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#define DM9000_MWCMD 0xF8 /* "auto increment" write byte */
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#define DM9000_MWRL 0xFA
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#define DM9000_MWRH 0xFB
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#define DM9000_MWRL 0xFA /* memory write address 7:0 */
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#define DM9000_MWRH 0xFB /* memory write address 15:8 */
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#define DM9000_TXPLL 0xFC /* frame len 7:0 to transmit */
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#define DM9000_TXPLH 0xFD /* frame len 15:8 to transmit */
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#define DM9000_ISR 0xFE /* interrupt status report */
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#define DM9000_IOMODE_MASK 0xC0
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#define DM9000_IOMODE_SHIFT 6
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#define DM9000_ISR_PRS (1<<0) /* receive completed */
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#define DM9000_ISR_PTS (1<<1) /* transmit completed */
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#define DM9000_ISR_ROS (1<<2)
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#define DM9000_ISR_ROOS (1<<3)
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/* 7:6 I/O size (hard wired) 10b: 8-bit, 00b: 16-bit, 01b: 32-bit */
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#define DM9000_ISR_PRS (1<<0) /* receive completed, W1C */
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#define DM9000_ISR_PTS (1<<1) /* transmit completed, W1C */
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#define DM9000_ISR_ROS (1<<2) /* Rx overflow latch, W1C */
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#define DM9000_ISR_ROOS (1<<3) /* Rx overflow cntr overflowed, W1C */
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#define DM9000_ISR_UNDERRUN (1<<4) /* Tx underrun detected */
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#define DM9000_ISR_LNKCHNG (1<<5) /* link status change detected */
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#define DM9000_IMR 0xFF
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#define DM9000_IMR_PRM (1<<0)
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#define DM9000_IMR_PTM (1<<1)
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#define DM9000_IMR_ROM (1<<2)
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#define DM9000_IMR_ROOM (1<<3)
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#define DM9000_IMR 0xFF /* interrupt mask */
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#define DM9000_IMR_PRM (1<<0) /* enable receive event report */
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#define DM9000_IMR_PTM (1<<1) /* enable xmit done event report */
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#define DM9000_IMR_ROM (1<<2) /* enable Rx overflow event report */
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#define DM9000_IMR_ROOM (1<<3) /* enable Rx overflow cntr ov report */
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#define DM9000_IMR_PAR (1<<7) /* use 3/13K SRAM w/ auto wrap */
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#endif
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