There are aarch64 Cortex cpus that do not trap on some floating point
exceptions - so apply the arm handling for aarch64 as well.
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@ -1,4 +1,4 @@
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/* $NetBSD: t_fpsetmask.c,v 1.17 2018/12/16 02:18:01 sevan Exp $ */
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/* $NetBSD: t_fpsetmask.c,v 1.18 2019/01/23 17:36:01 martin Exp $ */
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/*-
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* Copyright (c) 1995 The NetBSD Foundation, Inc.
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@ -58,7 +58,7 @@ ATF_TC_BODY(no_test, tc)
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#include <ieeefp.h>
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#if __arm__ && !__SOFTFP__
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#if (__arm__ && !__SOFTFP__) || __aarch64__
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/*
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* Some NEON fpus do not implement IEEE exception handling,
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* skip these tests if running on them and compiled for
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@ -1,4 +1,4 @@
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/* $NetBSD: t_siginfo.c,v 1.32 2018/01/17 00:16:43 maya Exp $ */
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/* $NetBSD: t_siginfo.c,v 1.33 2019/01/23 17:36:01 martin Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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@ -309,7 +309,7 @@ ATF_TC_BODY(sigfpe_flt, tc)
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if (isQEMU())
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atf_tc_skip("Test does not run correctly under QEMU");
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#if defined(__arm__) && !__SOFTFP__
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#if (__arm__ && !__SOFTFP__) || __aarch64__
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/*
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* Some NEON fpus do not implement IEEE exception handling,
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* skip these tests if running on them and compiled for
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@ -1,4 +1,4 @@
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/* $NetBSD: t_fenv.c,v 1.3 2015/12/22 14:20:59 christos Exp $ */
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/* $NetBSD: t_fenv.c,v 1.4 2019/01/23 17:36:01 martin Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__RCSID("$NetBSD: t_fenv.c,v 1.3 2015/12/22 14:20:59 christos Exp $");
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__RCSID("$NetBSD: t_fenv.c,v 1.4 2019/01/23 17:36:01 martin Exp $");
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#include <atf-c.h>
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@ -40,7 +40,7 @@ __RCSID("$NetBSD: t_fenv.c,v 1.3 2015/12/22 14:20:59 christos Exp $");
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#include <stdlib.h>
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#if __arm__ && !__SOFTFP__
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#if (__arm__ && !__SOFTFP__) || __aarch64__
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/*
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* Some NEON fpus do not implement IEEE exception handling,
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* skip these tests if running on them and compiled for
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