diff --git a/sys/arch/evbarm/iq80321/i80321_mainbus.c b/sys/arch/evbarm/iq80321/i80321_mainbus.c
index 3e88c44727f9..ed9604443501 100644
--- a/sys/arch/evbarm/iq80321/i80321_mainbus.c
+++ b/sys/arch/evbarm/iq80321/i80321_mainbus.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: i80321_mainbus.c,v 1.10 2003/07/15 00:25:04 lukem Exp $	*/
+/*	$NetBSD: i80321_mainbus.c,v 1.11 2003/09/12 04:39:59 briggs Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.10 2003/07/15 00:25:04 lukem Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.11 2003/09/12 04:39:59 briggs Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -94,6 +94,7 @@ void
 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 {
 	struct i80321_softc *sc = (void *) self;
+	pcireg_t b0u, b0l, b1u, b1l;
 	paddr_t memstart;
 	psize_t memsize;
 
@@ -117,14 +118,33 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 		panic("%s: unable to subregion MCU registers",
 		    sc->sc_dev.dv_xname);
 
+	if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
+	    VERDE_ATU_SIZE, &sc->sc_atu_sh))
+		panic("%s: unable to subregion ATU registers",
+		    sc->sc_dev.dv_xname);
+
 	/*
 	 * We have mapped the the PCI I/O windows in the early
 	 * bootstrap phase.
 	 */
 	sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
 
-	/* Some boards are always considered "host". */
-	sc->sc_is_host = 1;		/* XXX */
+	/*
+	 * Check the configuration of the ATU to see if another BIOS
+	 * has configured us.  If a PC BIOS didn't configured us, then
+	 * BAR0 is 00000000.0000000c and BAR1 is 00000000.8000000c.  If
+	 * a BIOS has configured us, at least one of those should be
+	 * different.
+	 */
+	b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0);
+	b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4);
+	b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8);
+	b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc);
+
+	if ((b0u != b1u) || (b0l != 0x0000000c) || (b1l != 0x8000000cU))
+		sc->sc_is_host = 0;
+	else
+		sc->sc_is_host = 1;
 
 	aprint_naive(": i80321 I/O Processor\n");
 	aprint_normal(": i80321 I/O Processor, acting as PCI %s\n",
@@ -139,9 +159,9 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 	 *
 	 *	1	Reserve space for private devices
 	 *
-	 *	2	Unused.
+	 *	2	RAM access
 	 *
-	 *	3	RAM access
+	 *	3	Unused.
 	 *
 	 * This chunk needs to be customized for each IOP321 application.
 	 */
@@ -158,26 +178,32 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
 		    PCI_MAPREG_MEM_TYPE_64BIT;
 		sc->sc_iwin[1].iwin_base_hi = 0;
-		sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
-		sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
 	} else {
-		panic("i80321: iwin[1] slave");
+		sc->sc_iwin[1].iwin_base_lo = 0;
+		sc->sc_iwin[1].iwin_base_hi = 0;
 	}
+	sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
+	sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
 
 	if (sc->sc_is_host) {
 		sc->sc_iwin[2].iwin_base_lo = memstart |
 		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
 		    PCI_MAPREG_MEM_TYPE_64BIT;
 		sc->sc_iwin[2].iwin_base_hi = 0;
-		sc->sc_iwin[2].iwin_xlate = memstart;
-		sc->sc_iwin[2].iwin_size = memsize;
 	} else {
-		panic("i80321: iwin[2] slave");
+		sc->sc_iwin[2].iwin_base_lo = 0;
+		sc->sc_iwin[2].iwin_base_hi = 0;
 	}
+	sc->sc_iwin[2].iwin_xlate = memstart;
+	sc->sc_iwin[2].iwin_size = memsize;
 
-	sc->sc_iwin[3].iwin_base_lo = 0 |
-	    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
-	    PCI_MAPREG_MEM_TYPE_64BIT;
+	if (sc->sc_is_host) {
+		sc->sc_iwin[3].iwin_base_lo = 0 |
+		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+		    PCI_MAPREG_MEM_TYPE_64BIT;
+	} else {
+		sc->sc_iwin[3].iwin_base_lo = 0;
+	}
 	sc->sc_iwin[3].iwin_base_hi = 0;
 	sc->sc_iwin[3].iwin_xlate = 0;
 	sc->sc_iwin[3].iwin_size = 0;