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Add Cirrus register definitions, per PR 6172.

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This commit is contained in:
mycroft 2004-07-06 14:04:51 +00:00
parent c01807532a
commit 06cb75fa32
1 changed files with 20 additions and 5 deletions
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25
sys/dev/ic/i82365reg.h
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@ -1,4 +1,4 @@
/* $NetBSD: i82365reg.h,v 1.8 2003/09/12 22:09:04 mycroft Exp $ */
/* $NetBSD: i82365reg.h,v 1.9 2004/07/06 14:04:51 mycroft Exp $ */
/*
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
@ -99,7 +99,7 @@
#define PCIC_PWRCTL_VPP1_VCC 0x01
#define PCIC_PWRCTL_VPP1_OFF 0x00
#define PCIC_CSC 0x04 /* RW */
#define PCIC_CSC 0x04 /* RO */
#define PCIC_CSC_ZERO 0xE0
#define PCIC_CSC_GPI 0x10
#define PCIC_CSC_CD 0x08 /* Card Detect Change */
@ -331,8 +331,16 @@
#define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02
#define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01
#define PCIC_CIRRUS_MISC_CTL_2 0x1E
#define PCIC_CIRRUS_MISC_CTL_1 0x16 /* RW */
#define PCIC_CIRRUS_MISC_CTL_1_SPKR_ENABLE 0x10
#define PCIC_CIRRUS_FIFO_CTL 0x17 /* RW */
#define PCIC_CIRRUS_FIFO_CTL_EMPTY 0x80 /* I/O read */
#define PCIC_CIRRUS_FIFO_CTL_FLUSH 0x80 /* I/O write */
#define PCIC_CIRRUS_MISC_CTL_2 0x1E /* RW */
#define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04
#define PCIC_CIRRUS_MISC_CTL_2_LP_DYNAMIC_MODE 0x02
#define PCIC_CIRRUS_CHIP_INFO 0x1F
#define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0
@ -341,8 +349,15 @@
#define PCIC_CIRRUS_EXTENDED_INDEX 0x2E
#define PCIC_CIRRUS_EXTENDED_DATA 0x2F
#define PCIC_CIRRUS_EXT_CONTROL_1 0x03
#define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
#define PCIC_CIRRUS_EXT_CONTROL_1 0x03
#define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
#define PCIC_CIRRUS_PROD_ID 0x35 /* RO */
#define PCIC_CIRRUS_PROD_ID_FAM_MASK 0xF0
#define PCIC_CIRRUS_PROD_ID_FAM_PD6729 0x20
#define PCIC_CIRRUS_PROD_ID_PROD_MASK 0x0F
#define PCIC_CIRRUS_PROD_ID_PROD_PD6729 0x00
#define PCIC_RICOH_REG_CHIP_ID 0x3A
#define PCIC_RICOH_CHIP_ID_5C296 0x32