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make Mhz consistently MHz -- from Igor Sobrado, PR misc/19812

This commit is contained in:
perry 2003-03-31 18:31:11 +00:00
parent 0150c80b00
commit 05ed3a9ec7
1 changed files with 11 additions and 11 deletions
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22
share/man/man4/man4.sparc/intro.4
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@ -27,7 +27,7 @@
.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $NetBSD: intro.4,v 1.15 2002/11/09 07:54:28 grant Exp $
.\" $NetBSD: intro.4,v 1.16 2003/03/31 18:31:11 perry Exp $
.\"
.Dd February 2, 2002
.Dt INTRO 4 sparc
@ -144,11 +144,11 @@ SPARCstation IPX (40 MHz).
.It sun4m
desktop SPARC systems with Mbus for CPUs, and Sbus:
.br
SPARC Classic (50 Mhz microSPARC I)
SPARC Classic (50 MHz microSPARC I)
.br
SPARC LX (50 MHz microSPARC I)
.br
SPARCstation 4 (70 Mhz microSPARC II)
SPARCstation 4 (70 MHz microSPARC II)
.br
SPARCstation 5 (70, 85, 110 MHz microSPARC II)
.br
@ -177,21 +177,21 @@ The sun4m architecture with Mbus modules for the CPUs is supported
with the following modules with only one CPU:
.Bl -tag -width speaker
.It SM41
40 Mhz SuperSPARC I with 1MB SuperCACHE
40 MHz SuperSPARC I with 1MB SuperCACHE
.It SM51
50 Mhz SuperSPARC I with 1MB SuperCACHE
50 MHz SuperSPARC I with 1MB SuperCACHE
.It SM61
60 Mhz SuperSPARC I with 1MB SuperCACHE
60 MHz SuperSPARC I with 1MB SuperCACHE
.It SM71
75 Mhz SuperSPARC II with 1MB SuperCACHE
75 MHz SuperSPARC II with 1MB SuperCACHE
.It SM81
85 Mhz SuperSPARC II with 1MB SuperCACHE
85 MHz SuperSPARC II with 1MB SuperCACHE
.It HS11
100 Mhz Ross Technology HyperSPARC
100 MHz Ross Technology HyperSPARC
.It HS21
125 Mhz Ross Technology HyperSPARC
125 MHz Ross Technology HyperSPARC
.It M151
150 Mhz Ross Technology HyperSPARC
150 MHz Ross Technology HyperSPARC
.El
.Pp
This list is not exhaustive;