add VR4181 BCU register definitions.
add routines for VR4181.
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sato
parent
09fc203c72
commit
05c9ce0788
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@ -1,4 +1,4 @@
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/* $NetBSD: bcu_vrip.c,v 1.7 2001/04/18 11:07:26 sato Exp $ */
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/* $NetBSD: bcu_vrip.c,v 1.8 2001/04/21 14:44:40 sato Exp $ */
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/*-
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* Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
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@ -120,7 +120,7 @@ vrbcu_dump_regs()
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{
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struct vrbcu_softc *sc = the_bcu_sc;
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int cpuclock = 0, tclock = 0, vtclock = 0, cpuid;
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#if !defined(ONLY_VR4181) && !defined(ONLY_VR4102) && defined VRGROUP_4111_4122
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#if !defined(ONLY_VR4102)
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int spdreg;
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#endif
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#ifdef VRBCUDEBUG
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@ -128,7 +128,7 @@ vrbcu_dump_regs()
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#endif /* VRBCUDEBUG */
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cpuid = vrbcu_vrip_getcpuid();
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#if !defined(ONLY_VR4181) && !defined(ONLY_VR4102) && defined VRGROUP_4111_4122
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#if !defined(ONLY_VR4181) && !defined(ONLY_VR4102)
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if (cpuid != BCUREVID_FIXRID_4181
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&& cpuid <= BCUREVID_RID_4122
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&& cpuid >= BCUREVID_RID_4111) {
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@ -138,11 +138,38 @@ vrbcu_dump_regs()
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#endif /* VRBCUDEBUG */
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}
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#endif
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#if defined VR4181
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if (cpuid == BCUREVID_FIXRID_4181){
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spdreg = vrbcu_read(sc, BCU81CLKSPEED_REG_W);
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#ifdef VRBCUDEBUG
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printf("vrbcu: CLKSPEED %x: \n", spdreg);
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#endif /* VRBCUDEBUG */
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}
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#endif
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cpuclock = vrbcu_vrip_getcpuclock();
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switch (cpuid) {
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#if defined VR4181
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case BCUREVID_FIXRID_4181:
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switch ((spdreg&BCU81CLKSPEED_DIVTMASK)>>BCU81CLKSPEED_DIVTSHFT){
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case BCU81CLKSPEED_DIVT1:
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vtclock = tclock = cpuclock;
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break;
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case BCU81CLKSPEED_DIVT2:
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vtclock = tclock = cpuclock/2;
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break;
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case BCU81CLKSPEED_DIVT3:
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vtclock = tclock = cpuclock/3;
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break;
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case BCU81CLKSPEED_DIVT4:
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vtclock = tclock = cpuclock/4;
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break;
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default:
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vtclock = tclock = 0;
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}
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break;
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#endif /* VR4181 */
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case BCUREVID_RID_4101:
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case BCUREVID_RID_4102:
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vtclock = tclock = cpuclock/2;
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@ -262,14 +289,16 @@ vrbcu_vrip_getcpuid(void)
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return vr_cpuid;
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if (vr_cpuid == -1) {
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revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W));
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if (VRIP_BCU_ADDR == VR4181_BCU_ADDR)
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revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCU81REVID_REG_W));
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else
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revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W));
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vr_cpuid = *revreg;
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vr_cpuid = (vr_cpuid&BCUREVID_RIDMASK)>>BCUREVID_RIDSHFT;
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#if !defined(VR4101) && defined(VR4181)
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if (vr_cpuid == BCUREVID_RID_4181) /* conflict vr4101 */
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if (VRIP_BCU_ADDR == VR4181_BCU_ADDR
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&& vr_cpuid == BCUREVID_RID_4181) /* conflict vr4101 */
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vr_cpuid = BCUREVID_FIXRID_4181;
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#endif /* !defined(VR4101) && defined(VR4181) */
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}
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return vr_cpuid;
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}
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@ -330,12 +359,13 @@ vrbcu_vrip_getcpuclock(void)
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cpuid = vrbcu_vrip_getcpuid();
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if (cpuid != BCUREVID_FIXRID_4181 && cpuid >= BCUREVID_RID_4111) {
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clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUCLKSPEED_REG_W)) & BCUCLKSPEED_CLKSPMASK;
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} else if (cpuid == BCUREVID_FIXRID_4181) {
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clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCU81CLKSPEED_REG_W)) & BCUCLKSPEED_CLKSPMASK;
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}
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switch (cpuid) {
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case BCUREVID_FIXRID_4181:
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/* assume 66MHz */
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cpuclock = 66000000;
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cpuclock = CLKX / clksp * 64;
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/* branch delay is 1 clock; 2 clock/loop */
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cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ;
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break;
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@ -1,4 +1,4 @@
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/* $NetBSD: bcureg.h,v 1.5 2001/04/16 09:17:05 sato Exp $ */
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/* $NetBSD: bcureg.h,v 1.6 2001/04/21 14:44:40 sato Exp $ */
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/*-
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* Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
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@ -51,6 +51,10 @@
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#define BCUCNT1_DRAM64M (1<<14) /* DRAM SIZE 64Mbit*/
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#define BCUCNT1_DRAM32M (0<<14) /* DRAM SIZE 32Mbit*/
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#define BCUCNT1_ROMSMASK (0x3<<14) /* ROM SIZE (=4181) */
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#define BCUCNT1_ROMS64M (0x2<<14) /* ROM SIZE 64Mbit */
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#define BCUCNT1_ROMS32M (0x1<<14) /* ROM SIZE 32Mbit */
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#define BCUCNT1_ISAMLCD (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff(>= 4102) */
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#define BCUCNT1_ISA (1<<13) /* ISA memory space */
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#define BCUCNT1_LCD (0<<13) /* LCD space*/
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@ -88,7 +92,7 @@
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#define BCUCNT1_ROMWENEN (1<<5) /* Enable */
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#define BCUCNT1_ROMWENDS (0<<5) /* Prohibit */
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#define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0 (<= 4122,>= 4102) */
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#define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0 (<= 4122,>= 4102, =4181) */
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#define BCUCNT1_ROMWEN0EN (1<<4) /* Enable */
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#define BCUCNT1_ROMWEN0DS (0<<4) /* Prohibit */
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@ -109,12 +113,17 @@
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#define BCUCNT1_BUSHERREN (1<<1) /* Enable */
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#define BCUCNT1_BUSHERRDS (0<<1) /* Prohibit */
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#define BCUCNT1_RTYPE (0x3<<1) /* ROM type (=4181) */
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#define BCUCNT1_RTOROM (0<<1) /* Odinary ROM */
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#define BCUCNT1_RTFLASH (1<<1) /* flash ROM */
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#define BCUCNT1_RTPAGEROM (2<<1) /* Page ROM */
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#define BCUCNT1_RSTOUT (1) /* RSTOUT control bit */
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#define BCUCNT1_RSTOUTH (1) /* RSTOUT high level*/
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#define BCUCNT1_RSTOUTL (0) /* RSTOUT low level*/
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#define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 (<= 4121,>= 4102) */
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#define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 (<= 4121,>= 4102, =4181) */
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#define BCUCNT2_GMODE (1) /* LCD access control */
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#define BCUCNT2_GMODENOM (1) /* not invert LCD */
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@ -304,7 +313,7 @@
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#define BCUIO1SPEED_CSRW_2VT (0x1) /* 2VTClock */
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#define BCUIO1SPEED_CSRW_1VT (0x0) /* 1VTClock */
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#define BCUSPEED_REG_W 0x00A /* BCU Access Cycle Change Register */
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#define BCUSPEED_REG_W 0x00A /* BCU Access Cycle Change Register (4121>=4102)*/
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#define BCUSPD_WPROM (0x3<<12) /* Page ROM access speed */
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#define BCUSPD_WPROMRFU (0x3<<12) /* RFU */
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@ -352,18 +361,49 @@
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#define BCUSPD_WROMA9T (0x0<<0) /* 9TClock */
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#define BCUERRST_REG_W 0x00C /* BCU BUS ERROR Status Register */
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#define BCUERRST_REG_W 0x00C /* BCU BUS ERROR Status Register (4121>=4102)*/
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#define BCUERRST_BUSERRMASK (1) /* Bus error, clear to 0 when 1 is written */
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#define BCUERRST_BUSERR (1) /* Bus error */
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#define BCUERRST_BUSNORM (0) /* Normal */
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#define BCU81SPEED_REG_W 0x00C /* BCU Access Cycle Change Register (=4181)*/
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#define BCURFCNT_REG_W 0x00E /* BCU Refresh Control Register */
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#define BCU81SPD_WPROM (0x7<<12) /* Page ROM access speed */
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#define BCU81SPD_WPROM8T (0x7<<12) /* 8TClock */
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#define BCU81SPD_WPROM7T (0x6<<12) /* 7TClock */
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#define BCU81SPD_WPROM6T (0x5<<12) /* 6TClock */
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#define BCU81SPD_WPROM5T (0x4<<12) /* 5TClock */
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#define BCU81SPD_WPROM4T (0x3<<12) /* 4TClock */
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#define BCU81SPD_WPROM3T (0x2<<12) /* 3TClock */
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#define BCU81SPD_WPROM2T (0x1<<12) /* 2TClock */
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#define BCU81SPD_WPROM1T (0x0<<12) /* 1TClock */
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#define BCU81SPD_WROMA (0xf<<0) /* System Bus Access Speed */
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#define BCU81SPD_WROMA16T (0xf<<0) /* 16TClock */
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#define BCU81SPD_WROMA15T (0xe<<0) /* 15TClock */
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#define BCU81SPD_WROMA14T (0xd<<0) /* 14TClock */
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#define BCU81SPD_WROMA13T (0xc<<0) /* 13TClock */
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#define BCU81SPD_WROMA12T (0xb<<0) /* 12TClock */
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#define BCU81SPD_WROMA11T (0xa<<0) /* 11TClock */
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#define BCU81SPD_WROMA10T (0x9<<0) /* 10TClock */
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#define BCU81SPD_WROMA9T (0x8<<0) /* 9TClock */
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#define BCU81SPD_WROMA8T (0x7<<0) /* 8TClock */
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#define BCU81SPD_WROMA7T (0x6<<0) /* 7TClock */
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#define BCU81SPD_WROMA6T (0x5<<0) /* 6TClock */
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#define BCU81SPD_WROMA5T (0x4<<0) /* 5TClock */
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#define BCU81SPD_WROMA4T (0x3<<0) /* 4TClock */
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#define BCU81SPD_WROMA3T (0x2<<0) /* 3TClock */
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#define BCU81SPD_WROMA2T (0x1<<0) /* 2TClock */
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#define BCU81SPD_WROMA1T (0x0<<0) /* 1TClock */
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#define BCURFCNT_REG_W 0x00E /* BCU Refresh Control Register(4121>=4102) */
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#define BCU81RFCNT_REG_W 0x00E /* BCU Refresh Control Register(=4181) */
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#define BCURFCNT_MASK 0x3fff /* refresh interval MASK */
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#define BCUREVID_REG_W 0x010 /* BCU Revision ID Register */
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#define BCUREVID_REG_W 0x010 /* BCU Revision ID Register (4122>=4101)*/
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#define BCU81REVID_REG_W 0x010 /* BCU Revision ID Register (=4181)*/
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#define BCUREVID_RIDMASK (0xf<<12) /* Revision ID */
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#define BCUREVID_RIDSHFT (12) /* Revision ID */
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@ -389,6 +429,7 @@
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#define BCUCLKSPEED_REG_W 0x014 /* Clock Speed Register (>= 4102) */
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#define BCU81CLKSPEED_REG_W 0x014 /* Clock Speed Register (= 4181) */
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#define BCUCLKSPEED_DIVT2B (1<<15) /* (= 4102, 4111) */
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#define BCUCLKSPEED_DIVT3B (1<<14) /* (= 4111) */
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@ -406,6 +447,13 @@
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#define BCUCLKSPEED_TDIV2 0x0
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#define BCUCLKSPEED_TDIVSHFT (12)
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#define BCU81CLKSPEED_DIVTMASK (0x7<<12) /* (=4181) */
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#define BCU81CLKSPEED_DIVT1 0x7
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#define BCU81CLKSPEED_DIVT2 0x3
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#define BCU81CLKSPEED_DIVT3 0x5
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#define BCU81CLKSPEED_DIVT4 0x6
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#define BCU81CLKSPEED_DIVTSHFT (12)
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#define BCUCLKSPEED_DIVVTMASK (0xf<<8) /* (= 4121) */
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#define BCUCLKSPEED_DIVVT1 0x1
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#define BCUCLKSPEED_DIVVT2 0x2
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