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Use symbolic constants for SR and CCR init values. 

Same object code is generated.
This commit is contained in:
uwe 2020-07-12 03:52:51 +00:00
parent d0c1a9d713
commit 05baf22b48
1 changed files with 5 additions and 4 deletions
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9
sys/arch/evbsh3/evbsh3/locore.S
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@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.12 2020/07/12 01:52:22 uwe Exp $ */ /* $NetBSD: locore.S,v 1.13 2020/07/12 03:52:51 uwe Exp $ */
/*- /*-
* Copyright (c) 1990 The Regents of the University of California. * Copyright (c) 1990 The Regents of the University of California.
@ -81,6 +81,7 @@
#endif #endif
#include <sh3/asm.h> #include <sh3/asm.h>
#include <sh3/psl.h>
#include <sh3/exception.h> #include <sh3/exception.h>
#include <sh3/locore.h> #include <sh3/locore.h>
#include <sh3/mmu_sh3.h> #include <sh3/mmu_sh3.h>
@ -111,7 +112,7 @@ ALTENTRY(kernel_text)
bra start1 bra start1
nop nop
.align 2 .align 2
SR_init: .long 0x500000F0 SR_init: .long PSL_MD | PSL_BL | PSL_IMASK
REG_SYMBOL(MMUCR) REG_SYMBOL(MMUCR)
start1: start1:
@ -230,8 +231,8 @@ XLinitSH3: .long _C_LABEL(initSH3)
XLmain: .long _C_LABEL(main) XLmain: .long _C_LABEL(main)
XLtoP2: .long 0x20000000 XLtoP2: .long 0x20000000
REG_SYMBOL(CCR) REG_SYMBOL(CCR)
#ifdef SH4 #ifdef SH4 /* invalidate and enable instruction and operand caches */
XL_CCRVAL: .long 0x0909 /* Operand cache ON */ XL_CCRVAL: .long SH4_CCR_ICI | SH4_CCR_ICE | SH4_CCR_OCI | SH4_CCR_OCE
#endif /* SH4 */ #endif /* SH4 */
load_and_reset: load_and_reset: