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Add work-in-progress framebuffer console driver for the VIA UniChrome

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integrated graphics family.
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jmcneill 2006-08-02 01:44:09 +00:00
parent 4adcd9d67f
commit 051b75db82
5 changed files with 3487 additions and 0 deletions
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sys/dev/pci/unichromeconfig.h Normal file
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/* $NetBSD: unichromeconfig.h,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */
/*
* Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DEV_PCI_UNICHROMECONFIG_H
#define _DEV_PCI_UNICHROMECONFIG_H
static struct pll_map pll_value[] = {
{CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
{CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
{CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
{CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
{CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
{CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
{CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
{CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
{CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
{CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
{CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
{CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
{CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
{CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
{CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
{CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
{CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
{CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
{CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
{CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
{CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
{CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M, CX700_108_000M},
{CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M, CX700_125_104M},
{CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M, CX700_133_308M},
{CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M, CX700_135_000M},
{CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M, CX700_157_500M},
{CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M, CX700_162_000M},
{CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M, CX700_202_500M},
{CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M, CX700_234_000M},
{CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M, CX700_297_500M},
{CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
{CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M, CX700_172_798M}
};
#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
static struct fifo_depth_select display_fifo_depth_reg= {
// IGA1 FIFO Depth_Select
{IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17,0,7}}},
// IGA2 FIFO Depth_Select
{IGA2_FIFO_DEPTH_SELECT_REG_NUM, {{CR68,4,7}, {CR94,7,7}, {CR95,7,7}}}
};
static struct fifo_threshold_select fifo_threshold_select_reg= {
// IGA1 FIFO Threshold Select
{IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16,0,5},{SR16,7,7}}},
// IGA2 FIFO Threshold Select
{IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68,0,3}, {CR95,4,6}}}
};
static struct fifo_high_threshold_select fifo_high_threshold_select_reg= {
// IGA1 FIFO High Threshold Select
{IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18,0,5},{SR18,7,7}}},
// IGA2 FIFO High Threshold Select
{IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92,0,3}, {CR95,0,2}}}
};
static struct display_queue_expire_num display_queue_expire_num_reg= {
// IGA1 Display Queue Expire Num
{IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22,0,4}}},
// IGA2 Display Queue Expire Num
{IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94,0,6}}}
};
// Definition Offset Registers
static struct offset offset_reg = {
// IGA1 Offset Register
{IGA1_OFFSET_REG_NUM, {{CR13,0,7},{CR35,5,7}}},
// IGA2 Offset Register
{IGA2_OFFSET_REG_NUM, {{CR66,0,7},{CR67,0,1}}}
};
// Definition Fetch Count Registers
static struct fetch_count fetch_count_reg = {
// IGA1 Fetch Count Register
{IGA1_FETCH_COUNT_REG_NUM, {{SR1C,0,7},{SR1D,0,1}}},
// IGA2 Fetch Count Register
{IGA2_FETCH_COUNT_REG_NUM, {{CR65,0,7},{CR67,2,3}}}
};
// Definition Starting Address Registers
/*static static struct starting_addr starting_addr_reg = {
// IGA1 Starting Address Register
{IGA1_STARTING_ADDR_REG_NUM, {{CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}}},
// IGA2 Starting Address Register
{IGA2_STARTING_ADDR_REG_NUM, {{CR62,1,7},{CR63,0,7},{CR64,0,7}}}
};*/
#define IGA1_STARTING_ADDR_REG_NUM 4 // location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}
#define IGA2_STARTING_ADDR_REG_NUM 3 // location: {CR62,1,7},{CR63,0,7},{CR64,0,7}
static struct iga1_crtc_timing iga1_crtc_reg = {
// IGA1 Horizontal Total
{IGA1_HOR_TOTAL_REG_NUM, {{CR00,0,7}, {CR36,3,3}}},
// IGA1 Horizontal Addressable Video
{IGA1_HOR_ADDR_REG_NUM, {{CR01,0,7}}},
// IGA1 Horizontal Blank Start
{IGA1_HOR_BLANK_START_REG_NUM, {{CR02,0,7}}},
// IGA1 Horizontal Blank End
{IGA1_HOR_BLANK_END_REG_NUM, {{CR03,0,4}, {CR05,7,7}, {CR33,5,5}}},
// IGA1 Horizontal Sync Start
{IGA1_HOR_SYNC_START_REG_NUM, {{CR04,0,7}, {CR33,4,4}}},
// IGA1 Horizontal Sync End
{IGA1_HOR_SYNC_END_REG_NUM, {{CR05,0,4}}},
// IGA1 Vertical Total
{IGA1_VER_TOTAL_REG_NUM, {{CR06,0,7}, {CR07,0,0}, {CR07,5,5}, {CR35,0,0}}},
// IGA1 Vertical Addressable Video
{IGA1_VER_ADDR_REG_NUM, {{CR12,0,7}, {CR07,1,1}, {CR07,6,6}, {CR35,2,2}}},
// IGA1 Vertical Blank Start
{IGA1_VER_BLANK_START_REG_NUM, {{CR15,0,7}, {CR07,3,3}, {CR09,5,5}, {CR35,3,3}}},
// IGA1 Vertical Blank End
{IGA1_VER_BLANK_END_REG_NUM, {{CR16,0,7}}},
// IGA1 Vertical Sync Start
{IGA1_VER_SYNC_START_REG_NUM, {{CR10,0,7}, {CR07,2,2}, {CR07,7,7}, {CR35,1,1}}},
// IGA1 Vertical Sync End
{IGA1_VER_SYNC_END_REG_NUM, {{CR11,0,3}}}
};
#if notyet
static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
// IGA2 Shadow Horizontal Total
{IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D,0,7}, {CR71,3,3}}},
// IGA2 Shadow Horizontal Blank End
{IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E,0,7}}},
// IGA2 Shadow Vertical Total
{IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F,0,7}, {CR71,0,2}}},
// IGA2 Shadow Vertical Addressable Video
{IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70,0,7}, {CR71,4,6}}},
// IGA2 Shadow Vertical Blank Start
{IGA2_SHADOW_VER_BLANK_START_REG_NUM, {{CR72,0,7}, {CR74,4,6}}},
// IGA2 Shadow Vertical Blank End
{IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73,0,7}, {CR74,0,2}}},
// IGA2 Shadow Vertical Sync Start
{IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75,0,7}, {CR76,4,6}}},
// IGA2 Shadow Vertical Sync End
{IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76,0,3}}}
};
static struct iga2_crtc_timing iga2_crtc_reg = {
// IGA2 Horizontal Total
{IGA2_HOR_TOTAL_REG_NUM, {{CR50,0,7}, {CR55,0,3}}},
// IGA2 Horizontal Addressable Video
{IGA2_HOR_ADDR_REG_NUM, {{CR51,0,7}, {CR55,4,6}}},
// IGA2 Horizontal Blank Start
{IGA2_HOR_BLANK_START_REG_NUM, {{CR52,0,7}, {CR54,0,2}}},
// IGA2 Horizontal Blank End
{IGA2_HOR_BLANK_END_REG_NUM, {{CR53,0,7}, {CR54,3,5}, {CR5D,6,6}}},
// IGA2 Horizontal Sync Start
{IGA2_HOR_SYNC_START_REG_NUM, {{CR56,0,7}, {CR54,6,7}, {CR5C,7,7}}},
// IGA2 Horizontal Sync End
{IGA2_HOR_SYNC_END_REG_NUM, {{CR57,0,7}, {CR5C,6,6}}},
// IGA2 Vertical Total
{IGA2_VER_TOTAL_REG_NUM, {{CR58,0,7}, {CR5D,0,2}}},
// IGA2 Vertical Addressable Video
{IGA2_VER_ADDR_REG_NUM, {{CR59,0,7}, {CR5D,3,5}}},
// IGA2 Vertical Blank Start
{IGA2_VER_BLANK_START_REG_NUM, {{CR5A,0,7}, {CR5C,0,2}}},
// IGA2 Vertical Blank End
{IGA2_VER_BLANK_END_REG_NUM, {{CR5B,0,7}, {CR5C,3,5}}},
// IGA2 Vertical Sync Start
{IGA2_VER_SYNC_START_REG_NUM, {{CR5E,0,7}, {CR5F,5,7}}},
// IGA2 Vertical Sync End
{IGA2_VER_SYNC_END_REG_NUM, {{CR5F,0,4}}}
};
/*static static struct _lcd_pwd_seq_timer lcd_pwd_seq_timer = {
// LCD Power Sequence TD0
{LCD_POWER_SEQ_TD0_REG_NUM, {{CR8B,0,7}, {CR8F,0,3}}},
// LCD Power Sequence TD1
{LCD_POWER_SEQ_TD1_REG_NUM, {{CR8C,0,7}, {CR8F,4,7}}},
// LCD Power Sequence TD2
{LCD_POWER_SEQ_TD2_REG_NUM, {{CR8D,0,7}, {CR90,0,3}}},
// LCD Power Sequence TD3
{LCD_POWER_SEQ_TD3_REG_NUM, {{CR8E,0,7}, {CR90,4,7}}}
};*/
static struct _lcd_scaling_factor lcd_scaling_factor = {
// LCD Horizontal Scaling Factor Register
{LCD_HOR_SCALING_FACTOR_REG_NUM, {{CR9F,0,1}, {CR77,0,7}, {CR79,4,5}}},
// LCD Vertical Scaling Factor Register
{LCD_VER_SCALING_FACTOR_REG_NUM, {{CR79,3,3}, {CR78,0,7}, {CR79,6,7}}}
};
static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
/* LCD Horizontal Scaling Factor Register */
{LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77,0,7}, {CR79,4,5}}},
/* LCD Vertical Scaling Factor Register */
{LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78,0,7}, {CR79,6,7}}}
};
static struct rgbLUT palLUT_table[]= {
// {R,G,B}
// Index 0x00~0x03
{0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, 0x2A, 0x2A},
// Index 0x04~0x07
{0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, 0x2A, 0x2A},
// Index 0x08~0x0B
{0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, 0x3F, 0x3F},
// Index 0x0C~0x0F
{0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, 0x3F, 0x3F},
// Index 0x10~0x13
{0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, 0x0B, 0x0B},
// Index 0x14~0x17
{0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, 0x18, 0x18},
// Index 0x18~0x1B
{0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, 0x28, 0x28},
// Index 0x1C~0x1F
{0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, 0x3F, 0x3F},
// Index 0x20~0x23
{0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, 0x00, 0x3F},
// Index 0x24~0x27
{0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, 0x00, 0x10},
// Index 0x28~0x2B
{0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, 0x2F, 0x00},
// Index 0x2C~0x2F
{0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, 0x3F, 0x00},
// Index 0x30~0x33
{0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, 0x3F, 0x2F},
// Index 0x34~0x37
{0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, 0x10, 0x3F},
// Index 0x38~0x3B
{0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, 0x1F, 0x3F},
// Index 0x3C~0x3F
{0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, 0x1F, 0x27},
// Index 0x40~0x43
{0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, 0x3F, 0x1F},
// Index 0x44~0x47
{0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, 0x3F, 0x1F},
// Index 0x48~0x4B
{0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, 0x3F, 0x37},
// Index 0x4C~0x4F
{0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, 0x27, 0x3F},
// Index 0x50~0x53
{0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, 0x2D, 0x3F},
// Index 0x54~0x57
{0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, 0x2D, 0x31},
// Index 0x58~0x5B
{0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, 0x3A, 0x2D},
// Index 0x5C~0x5F
{0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, 0x3F, 0x2D},
// Index 0x60~0x63
{0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, 0x3F, 0x3A},
// Index 0x64~0x67
{0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, 0x31, 0x3F},
// Index 0x68~0x6B
{0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, 0x00, 0x1C},
// Index 0x6C~0x6F
{0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, 0x00, 0x07},
// Index 0x70~0x73
{0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, 0x15, 0x00},
// Index 0x74~0x77
{0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, 0x1C, 0x00},
// Index 0x78~0x7B
{0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, 0x1C, 0x15},
// Index 0x7C~0x7F
{0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, 0x07, 0x1C},
// Index 0x80~0x83
{0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, 0x0E, 0x1C},
// Index 0x84~0x87
{0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, 0x0E, 0x11},
// Index 0x88~0x8B
{0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, 0x18, 0x0E},
// Index 0x8C~0x8F
{0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, 0x1C, 0x0E},
// Index 0x90~0x93
{0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, 0x1C, 0x18},
// Index 0x94~0x97
{0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, 0x11, 0x1C},
// Index 0x98~0x9B
{0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, 0x14, 0x1C},
// Index 0x9C~0x9F
{0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, 0x14, 0x16},
// Index 0xA0~0xA3
{0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, 0x1A, 0x14},
// Index 0xA4~0xA7
{0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, 0x1C, 0x14},
// Index 0xA8~0xAB
{0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, 0x1C, 0x1A},
// Index 0xAC~0xAF
{0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, 0x16, 0x1C},
// Index 0xB0~0xB3
{0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, 0x00, 0x10},
// Index 0xB4~0xB7
{0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, 0x00, 0x04},
// Index 0xB8~0xBB
{0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, 0x0C, 0x00},
// Index 0xBC~0xBF
{0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, 0x10, 0x00},
// Index 0xC0~0xC3
{0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, 0x10, 0x0C},
// Index 0xC4~0xC7
{0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, 0x04, 0x10},
// Index 0xC8~0xCB
{0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, 0x08, 0x10},
// Index 0xCC~0xCF
{0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, 0x08, 0x0A},
// Index 0xD0~0xD3
{0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, 0x0E, 0x08},
// Index 0xD4~0xD7
{0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, 0x10, 0x08},
// Index 0xD8~0xDB
{0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, 0x10, 0x0E},
// Index 0xDC~0xDF
{0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, 0x0A, 0x10},
// Index 0xE0~0xE3
{0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, 0x0B, 0x10},
// Index 0xE4~0xE7
{0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, 0x0B, 0x0C},
// Index 0xE8~0xEB
{0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, 0x0F, 0x0B},
// Index 0xEC~0xEF
{0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, 0x10, 0x0B},
// Index 0xF0~0xF3
{0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, 0x10, 0x0F},
// Index 0xF4~0xF7
{0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, 0x0C, 0x10},
// Index 0xF8~0xFB
{0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00},
// Index 0xFC~0xFF
{0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}
};
static uint16_t red256[] = {
0x0 ,0x0 ,0x0 ,0x0 ,0xa800,0xa800,0xa800,0xa800,0x5400,0x5400,0x5400,0x5400,0xfc00,0xfc00,0xfc00,0xfc00,
0x0 ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00,
0x0 ,0x4000,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,
0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,
0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,
0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,
0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0x0 ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,
0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,
0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,
0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,
0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,
0x0 ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,
0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,
0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,
0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0
};
static uint16_t green256[] = {
0x0 ,0x0 ,0xa800,0xa800,0x0 ,0x0 ,0x5400,0xa800,0x5400,0x5400,0xfc00,0xfc00,0x5400,0x5400,0xfc00,0xfc00,
0x0 ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00,
0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,
0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,
0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,
0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,
0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,
0x0 ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,
0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,
0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,
0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,
0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,
0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,
0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,
0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0
};
static uint16_t blue256[] = {
0x0 ,0xa800,0x0 ,0xa800,0x0 ,0xa800,0x0 ,0xa800,0x5400,0xfc00,0x5400,0xfc00,0x5400,0xfc00,0x5400,0xfc00,
0x0 ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00,
0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,
0x0 ,0x4000,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,
0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,
0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,
0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,
0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,
0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,
0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,
0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,
0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,
0x0 ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,
0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,
0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,
0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0
};
#endif
#endif /* _DEV_PCI_UNICHROMECONFIG_H */

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sys/dev/pci/unichromefb.c Normal file
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@ -0,0 +1,964 @@
/* $NetBSD: unichromefb.c,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */
/*-
* Copyright (c) 2006 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Jared D. McNeill.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: unichromefb.c,v 1.1 2006/08/02 01:44:09 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <machine/bus.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
#include <dev/wscons/wsdisplayvar.h>
#include <dev/wscons/wsconsio.h>
#include <dev/wsfont/wsfont.h>
#include <dev/rasops/rasops.h>
#include <dev/wscons/wsdisplay_vconsvar.h>
#include <dev/pci/unichromereg.h>
#include <dev/pci/unichromemode.h>
#include <dev/pci/unichromehw.h>
#include <dev/pci/unichromeconfig.h>
/* XXX */
#define UNICHROMEFB_DEPTH 32
struct unichromefb_softc {
struct device sc_dev;
struct vcons_data sc_vd;
void * sc_fbbase;
unsigned int sc_fbaddr;
unsigned int sc_fbsize;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
bus_space_tag_t sc_memt;
bus_space_handle_t sc_memh;
int sc_width;
int sc_height;
int sc_depth;
int sc_stride;
int sc_wsmode;
};
static int unichromefb_match(struct device *, struct cfdata *, void *);
static void unichromefb_attach(struct device *, struct device *, void *);
/* XXX */
int unichromefb_cnattach(void);
struct wsscreen_descr unichromefb_stdscreen = {
"fb",
0, 0,
NULL,
8, 16,
};
static int unichromefb_ioctl(void *, void *, u_long, caddr_t, int,
struct lwp *);
static paddr_t unichromefb_mmap(void *, void *, off_t, int);
static void unichromefb_init_screen(void *, struct vcons_screen *,
int, long *);
/* hardware access */
static uint8_t uni_rd(struct unichromefb_softc *, int, uint8_t);
static void uni_wr(struct unichromefb_softc *, int, uint8_t, uint8_t);
static void uni_wr_mask(struct unichromefb_softc *, int, uint8_t,
uint8_t, uint8_t);
static void uni_wr_x(struct unichromefb_softc *, struct io_reg *, int);
#if notyet
static void uni_wr_dac(struct unichromefb_softc *, uint8_t, uint8_t,
uint8_t, uint8_t);
#endif
/* helpers */
static struct VideoModeTable * uni_getmode(int);
static void uni_setmode(struct unichromefb_softc *, int, int);
static void uni_crt_lock(struct unichromefb_softc *);
static void uni_crt_unlock(struct unichromefb_softc *);
static void uni_crt_enable(struct unichromefb_softc *);
static void uni_screen_enable(struct unichromefb_softc *);
static void uni_set_start(struct unichromefb_softc *);
static void uni_set_crtc(struct unichromefb_softc *,
struct crt_mode_table *, int, int, int);
static void uni_load_crtc(struct unichromefb_softc *, struct display_timing,
int);
static void uni_load_reg(struct unichromefb_softc *, int, int,
struct io_register *, int);
static void uni_fix_crtc(struct unichromefb_softc *);
static void uni_load_offset(struct unichromefb_softc *, int, int, int);
static void uni_load_fetchcnt(struct unichromefb_softc *, int, int, int);
static void uni_load_fifo(struct unichromefb_softc *, int, int, int);
static void uni_set_depth(struct unichromefb_softc *, int, int);
static uint32_t uni_get_clkval(struct unichromefb_softc *, int);
static void uni_set_vclk(struct unichromefb_softc *, uint32_t, int);
struct wsdisplay_accessops unichromefb_accessops = {
unichromefb_ioctl,
unichromefb_mmap,
NULL,
NULL,
NULL,
NULL,
};
static struct vcons_screen unichromefb_console_screen;
const struct wsscreen_descr *_unichromefb_scrlist[] = {
&unichromefb_stdscreen,
};
struct wsscreen_list unichromefb_screenlist = {
sizeof(_unichromefb_scrlist) / sizeof(struct wsscreen_descr *),
_unichromefb_scrlist
};
CFATTACH_DECL(unichromefb, sizeof(struct unichromefb_softc),
unichromefb_match, unichromefb_attach, NULL, NULL);
static int
unichromefb_match(struct device *parent, struct cfdata *match, void *opaque)
{
struct pci_attach_args *pa;
pa = (struct pci_attach_args *)opaque;
if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
return 0;
if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_VIATECH)
return 0;
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_VIATECH_VT3314_IG:
return 10; /* beat vga(4) */
}
return 0;
}
static void
unichromefb_attach(struct device *parent, struct device *self, void *opaque)
{
struct unichromefb_softc *sc;
struct pci_attach_args *pa;
struct rasops_info *ri;
struct wsemuldisplaydev_attach_args aa;
uint8_t val;
long defattr;
sc = (struct unichromefb_softc *)self;
pa = (struct pci_attach_args *)opaque;
/* XXX */
sc->sc_width = 640;
sc->sc_height = 480;
sc->sc_depth = UNICHROMEFB_DEPTH;
sc->sc_stride = sc->sc_width * (sc->sc_depth / 8);
sc->sc_wsmode = WSDISPLAYIO_MODE_EMUL;
sc->sc_iot = pa->pa_iot;
if (bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, &sc->sc_ioh)) {
aprint_error(": failed to map I/O registers\n");
return;
}
val = uni_rd(sc, VIASR, SR30);
sc->sc_fbaddr = val << 24;
sc->sc_fbsize = sc->sc_width * sc->sc_height * (sc->sc_depth / 8);
sc->sc_memt = pa->pa_memt;
if (bus_space_map(sc->sc_memt, sc->sc_fbaddr, sc->sc_fbsize,
BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) {
aprint_error(": failed to map aperture at 0x%08x/0x%x\n",
sc->sc_fbaddr, sc->sc_fbsize);
return;
}
sc->sc_fbbase = (caddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh);
/*memset(sc->sc_fbbase, 0, sc->sc_fbsize);*/
aprint_naive("\n");
aprint_normal(": VIA UniChrome frame buffer\n");
ri = &unichromefb_console_screen.scr_ri;
memset(ri, 0, sizeof(struct rasops_info));
vcons_init(&sc->sc_vd, sc, &unichromefb_stdscreen,
&unichromefb_accessops);
sc->sc_vd.init_screen = unichromefb_init_screen;
uni_setmode(sc, VIA_RES_640X480, sc->sc_depth);
aprint_normal("%s: fb %dx%dx%d @%p\n", sc->sc_dev.dv_xname,
sc->sc_width, sc->sc_height, sc->sc_depth, sc->sc_fbbase);
delay(5*1000*1000);
unichromefb_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
vcons_init_screen(&sc->sc_vd, &unichromefb_console_screen, 1, &defattr);
unichromefb_stdscreen.ncols = ri->ri_cols;
unichromefb_stdscreen.nrows = ri->ri_rows;
unichromefb_stdscreen.textops = &ri->ri_ops;
unichromefb_stdscreen.capabilities = ri->ri_caps;
unichromefb_stdscreen.modecookie = NULL;
wsdisplay_cnattach(&unichromefb_stdscreen, ri, 0, 0, defattr);
aa.console = 1; /* XXX */
aa.scrdata = &unichromefb_screenlist;
aa.accessops = &unichromefb_accessops;
aa.accesscookie = &sc->sc_vd;
config_found(self, &aa, wsemuldisplaydevprint);
return;
}
static int
unichromefb_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag,
struct lwp *l)
{
struct vcons_data *vd;
struct unichromefb_softc *sc;
struct wsdisplay_fbinfo *fb;
vd = (struct vcons_data *)v;
sc = (struct unichromefb_softc *)vd->cookie;
switch (cmd) {
case WSDISPLAYIO_GTYPE:
*(u_int *)data = WSDISPLAY_TYPE_PCIMISC;
return 0;
case WSDISPLAYIO_GINFO:
if (vd->active != NULL) {
fb = (struct wsdisplay_fbinfo *)data;
fb->width = sc->sc_width;
fb->height = sc->sc_height;
fb->depth = sc->sc_depth;
fb->cmsize = 256;
return 0;
} else
return ENODEV;
case WSDISPLAYIO_GVIDEO:
return ENODEV;
case WSDISPLAYIO_SVIDEO:
return ENODEV;
case WSDISPLAYIO_GETCMAP:
return EINVAL;
case WSDISPLAYIO_PUTCMAP:
return EINVAL;
case WSDISPLAYIO_LINEBYTES:
*(u_int *)data = sc->sc_stride;
return 0;
case WSDISPLAYIO_SMODE:
{
int new_mode = *(int *)data;
if (new_mode != sc->sc_wsmode) {
sc->sc_wsmode = new_mode;
if (new_mode == WSDISPLAYIO_MODE_EMUL)
vcons_redraw_screen(vd->active);
}
}
return 0;
case WSDISPLAYIO_SSPLASH:
return ENODEV;
case WSDISPLAYIO_SPROGRESS:
return ENODEV;
}
return EPASSTHROUGH;
}
static paddr_t
unichromefb_mmap(void *v, void *vs, off_t offset, int prot)
{
return -1;
}
static void
unichromefb_init_screen(void *c, struct vcons_screen *scr, int existing,
long *defattr)
{
struct unichromefb_softc *sc;
struct rasops_info *ri;
sc = (struct unichromefb_softc *)c;
ri = &scr->scr_ri;
ri->ri_flg = RI_CENTER;
ri->ri_depth = sc->sc_depth;
ri->ri_width = sc->sc_width;
ri->ri_height = sc->sc_height;
ri->ri_stride = sc->sc_stride;
ri->ri_bits = sc->sc_fbbase;
ri->ri_rnum = ri->ri_gnum = ri->ri_bnum = 8;
ri->ri_rpos = 16;
ri->ri_gpos = 8;
ri->ri_bpos = 0;
rasops_init(ri, sc->sc_height / 16, sc->sc_width / 8);
ri->ri_caps = WSSCREEN_WSCOLORS;
rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight,
sc->sc_width / ri->ri_font->fontwidth);
return;
}
/*
* hardware access
*/
static uint8_t
uni_rd(struct unichromefb_softc *sc, int off, uint8_t idx)
{
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx);
return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1);
}
static void
uni_wr(struct unichromefb_softc *sc, int off, uint8_t idx, uint8_t val)
{
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, val);
}
static void
uni_wr_mask(struct unichromefb_softc *sc, int off, uint8_t idx,
uint8_t val, uint8_t mask)
{
uint8_t tmp;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx);
tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1,
((val & mask) | (tmp & ~mask)));
}
#if notyet
static void
uni_wr_dac(struct unichromefb_softc *sc, uint8_t idx,
uint8_t r, uint8_t g, uint8_t b)
{
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_INDEX_WRITE, idx);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, r);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, g);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, b);
}
#endif
static void
uni_wr_x(struct unichromefb_softc *sc, struct io_reg *tbl, int num)
{
int i;
uint8_t tmp;
for (i = 0; i < num; i++) {
bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].port,
tbl[i].index);
tmp = bus_space_read_1(sc->sc_iot, sc->sc_iot,
tbl[i].port + 1);
tmp = (tmp & (~tbl[i].mask)) | tbl[i].value;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].index + 1,
tmp);
}
}
/*
* helpers
*/
static struct VideoModeTable *
uni_getmode(int mode)
{
int i;
for (i = 0; i < NUM_TOTAL_MODETABLE; i++)
if (CLE266Modes[i].ModeIndex == mode)
return &CLE266Modes[i];
return NULL;
}
static void
uni_setmode(struct unichromefb_softc *sc, int idx, int bpp)
{
struct VideoModeTable *vtbl;
struct crt_mode_table *crt;
int i;
/* XXX */
vtbl = uni_getmode(idx);
if (vtbl == NULL)
panic("%s: unsupported mode: %d\n", sc->sc_dev.dv_xname, idx);
crt = vtbl->crtc;
(void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0);
/* XXX assume CN900 for now */
uni_wr_x(sc, CN900_ModeXregs, NUM_TOTAL_CN900_ModeXregs);
/* Fill VPIT params */
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, VPIT.Misc);
/* Write sequencer */
for (i = 1; i <= StdSR; i++) {
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1,
VPIT.SR[i - 1]);
}
uni_set_start(sc);
uni_set_crtc(sc, crt, idx, bpp / 8, IGA1);
for (i = 0; i < StdGR; i++) {
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR, i);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR + 1,
VPIT.GR[i]);
}
for (i = 0; i < StdAR; i++) {
(void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, i);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR + 1,
VPIT.AR[i]);
}
(void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0x20);
uni_set_crtc(sc, crt, idx, bpp / 8, IGA1);
/* set crt output path */
uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6);
uni_crt_enable(sc);
uni_screen_enable(sc);
return;
}
static void
uni_crt_lock(struct unichromefb_softc *sc)
{
uni_wr_mask(sc, VIACR, CR11, BIT7, BIT7);
}
static void
uni_crt_unlock(struct unichromefb_softc *sc)
{
uni_wr_mask(sc, VIACR, CR11, 0, BIT7);
uni_wr_mask(sc, VIACR, CR47, 0, BIT0);
}
static void
uni_crt_enable(struct unichromefb_softc *sc)
{
uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4);
}
static void
uni_screen_enable(struct unichromefb_softc *sc)
{
uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
}
static void
uni_set_start(struct unichromefb_softc *sc)
{
uni_crt_unlock(sc);
uni_wr(sc, VIACR, CR0C, 0x00);
uni_wr(sc, VIACR, CR0D, 0x00);
uni_wr(sc, VIACR, CR34, 0x00);
uni_wr_mask(sc, VIACR, CR48, 0x00, BIT0 + BIT1);
uni_wr(sc, VIACR, CR62, 0x00);
uni_wr(sc, VIACR, CR63, 0x00);
uni_wr(sc, VIACR, CR64, 0x00);
uni_wr(sc, VIACR, CRA3, 0x00);
uni_crt_lock(sc);
}
static void
uni_set_crtc(struct unichromefb_softc *sc, struct crt_mode_table *ctbl,
int mode, int bpp_byte, int iga)
{
struct VideoModeTable *vtbl;
struct display_timing crtreg;
int i;
int index;
int haddr, vaddr;
uint8_t val;
uint32_t pll_d_n;
index = 0;
vtbl = uni_getmode(mode);
for (i = 0; i < vtbl->mode_array; i++) {
index = i;
if (ctbl[i].refresh_rate == 60)
break;
}
crtreg = ctbl[index].crtc;
haddr = crtreg.hor_addr;
vaddr = crtreg.ver_addr;
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc);
if (ctbl[index].h_sync_polarity == NEGATIVE) {
if (ctbl[index].v_sync_polarity == NEGATIVE)
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
(val & (~(BIT6+BIT7))) | (BIT6+BIT7));
else
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
(val & (~(BIT6+BIT7))) | (BIT6));
} else {
if (ctbl[index].v_sync_polarity == NEGATIVE)
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
(val & (~(BIT6+BIT7))) | (BIT7));
else
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
(val & (~(BIT6+BIT7))));
}
if (iga == IGA1) {
uni_crt_unlock(sc);
uni_wr(sc, VIACR, CR09, 0x00);
uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6);
uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7);
}
uni_load_crtc(sc, crtreg, iga);
uni_fix_crtc(sc);
uni_crt_lock(sc);
uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7);
uni_load_offset(sc, haddr, bpp_byte, iga);
uni_load_fetchcnt(sc, haddr, bpp_byte, iga);
uni_load_fifo(sc, iga, haddr, vaddr);
uni_set_depth(sc, bpp_byte, iga);
pll_d_n = uni_get_clkval(sc, ctbl[index].clk);
uni_set_vclk(sc, pll_d_n, iga);
}
static void
uni_load_crtc(struct unichromefb_softc *sc,
struct display_timing device_timing, int iga)
{
int regnum, val;
struct io_register *reg;
int i;
regnum = val = 0;
reg = NULL;
uni_crt_unlock(sc);
for (i = 0; i < 12; i++) {
switch (iga) {
case IGA1:
switch (i) {
case H_TOTAL_INDEX:
val = IGA1_HOR_TOTAL_FORMULA(
device_timing.hor_total);
regnum = iga1_crtc_reg.hor_total.reg_num;
reg = iga1_crtc_reg.hor_total.reg;
break;
case H_ADDR_INDEX:
val = IGA1_HOR_ADDR_FORMULA(
device_timing.hor_addr);
regnum = iga1_crtc_reg.hor_addr.reg_num;
reg = iga1_crtc_reg.hor_addr.reg;
break;
case H_BLANK_START_INDEX:
val = IGA1_HOR_BLANK_START_FORMULA(
device_timing.hor_blank_start);
regnum = iga1_crtc_reg.hor_blank_start.reg_num;
reg = iga1_crtc_reg.hor_blank_start.reg;
break;
case H_BLANK_END_INDEX:
val = IGA1_HOR_BLANK_END_FORMULA(
device_timing.hor_blank_start,
device_timing.hor_blank_end);
regnum = iga1_crtc_reg.hor_blank_end.reg_num;
reg = iga1_crtc_reg.hor_blank_end.reg;
break;
case H_SYNC_START_INDEX:
val = IGA1_HOR_SYNC_START_FORMULA(
device_timing.hor_sync_start);
regnum = iga1_crtc_reg.hor_sync_start.reg_num;
reg = iga1_crtc_reg.hor_sync_start.reg;
break;
case H_SYNC_END_INDEX:
val = IGA1_HOR_SYNC_END_FORMULA(
device_timing.hor_sync_start,
device_timing.hor_sync_end);
regnum = iga1_crtc_reg.hor_sync_end.reg_num;
reg = iga1_crtc_reg.hor_sync_end.reg;
break;
case V_TOTAL_INDEX:
val = IGA1_VER_TOTAL_FORMULA(
device_timing.ver_total);
regnum = iga1_crtc_reg.ver_total.reg_num;
reg = iga1_crtc_reg.ver_total.reg;
break;
case V_ADDR_INDEX:
val = IGA1_VER_ADDR_FORMULA(
device_timing.ver_addr);
regnum = iga1_crtc_reg.ver_addr.reg_num;
reg = iga1_crtc_reg.ver_addr.reg;
break;
case V_BLANK_START_INDEX:
val = IGA1_VER_BLANK_START_FORMULA(
device_timing.ver_blank_start);
regnum = iga1_crtc_reg.ver_blank_start.reg_num;
reg = iga1_crtc_reg.ver_blank_start.reg;
break;
case V_BLANK_END_INDEX:
val = IGA1_VER_BLANK_END_FORMULA(
device_timing.ver_blank_start,
device_timing.ver_blank_end);
regnum = iga1_crtc_reg.ver_blank_end.reg_num;
reg = iga1_crtc_reg.ver_blank_end.reg;
break;
case V_SYNC_START_INDEX:
val = IGA1_VER_SYNC_START_FORMULA(
device_timing.ver_sync_start);
regnum = iga1_crtc_reg.ver_sync_start.reg_num;
reg = iga1_crtc_reg.ver_sync_start.reg;
break;
case V_SYNC_END_INDEX:
val = IGA1_VER_SYNC_END_FORMULA(
device_timing.ver_sync_start,
device_timing.ver_sync_end);
regnum = iga1_crtc_reg.ver_sync_end.reg_num;
reg = iga1_crtc_reg.ver_sync_end.reg;
break;
}
break;
case IGA2:
printf("%s: %s: IGA2 not supported\n",
sc->sc_dev.dv_xname, __func__);
break;
}
uni_load_reg(sc, val, regnum, reg, VIACR);
}
uni_crt_lock(sc);
}
static void
uni_load_reg(struct unichromefb_softc *sc, int timing, int regnum,
struct io_register *reg, int type)
{
int regmask, bitnum, data;
int i, j;
int shift_next_reg;
int startidx, endidx, cridx;
uint16_t getbit;
bitnum = 0;
for (i = 0; i < regnum; i++) {
regmask = data = 0;
startidx = reg[i].start_bit;
endidx = reg[i].end_bit;
cridx = reg[i].io_addr;
shift_next_reg = bitnum;
for (j = startidx; j <= endidx; j++) {
regmask = regmask | (BIT0 << j);
getbit = (timing & (BIT0 << bitnum));
data = data | ((getbit >> shift_next_reg) << startidx);
++bitnum;
}
if (type == VIACR)
uni_wr_mask(sc, VIACR, cridx, data, regmask);
else
uni_wr_mask(sc, VIASR, cridx, data, regmask);
}
return;
}
static void
uni_fix_crtc(struct unichromefb_softc *sc)
{
uni_wr_mask(sc, VIACR, CR03, 0x80, BIT7);
uni_wr(sc, VIACR, CR18, 0xff);
uni_wr_mask(sc, VIACR, CR07, 0x10, BIT4);
uni_wr_mask(sc, VIACR, CR09, 0x40, BIT6);
uni_wr_mask(sc, VIACR, CR35, 0x10, BIT4);
uni_wr_mask(sc, VIACR, CR33, 0x06, BIT0+BIT1+BIT2);
uni_wr(sc, VIACR, CR17, 0xe3);
uni_wr(sc, VIACR, CR08, 0x00);
uni_wr(sc, VIACR, CR14, 0x00);
return;
}
static void
uni_load_offset(struct unichromefb_softc *sc, int haddr, int bpp, int iga)
{
switch (iga) {
case IGA1:
uni_load_reg(sc,
IGA1_OFFSET_FORMULA(haddr, bpp),
offset_reg.iga1_offset_reg.reg_num,
offset_reg.iga1_offset_reg.reg,
VIACR);
break;
default:
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
__func__);
break;
}
return;
}
static void
uni_load_fetchcnt(struct unichromefb_softc *sc, int haddr, int bpp, int iga)
{
switch (iga) {
case IGA1:
uni_load_reg(sc,
IGA1_FETCH_COUNT_FORMULA(haddr, bpp),
fetch_count_reg.iga1_fetch_count_reg.reg_num,
fetch_count_reg.iga1_fetch_count_reg.reg,
VIASR);
break;
default:
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
__func__);
break;
}
return;
}
static void
uni_load_fifo(struct unichromefb_softc *sc, int iga, int horact, int veract)
{
int val, regnum;
struct io_register *reg;
int iga1_fifo_max_depth, iga1_fifo_threshold;
int iga1_fifo_high_threshold, iga1_display_queue_expire_num;
reg = NULL;
iga1_fifo_max_depth = iga1_fifo_threshold = 0;
iga1_fifo_high_threshold = iga1_display_queue_expire_num = 0;
switch (iga) {
case IGA1:
/* XXX if (type == CN900) { */
iga1_fifo_max_depth = CN900_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = CN900_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold = CN900_IGA1_FIFO_HIGH_THRESHOLD;
if (horact > 1280 && veract > 1024)
iga1_display_queue_expire_num = 16;
else
iga1_display_queue_expire_num =
CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
/* XXX } */
/* set display FIFO depth select */
val = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
regnum =
display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
uni_load_reg(sc, val, regnum, reg, VIASR);
/* set display FIFO threshold select */
val = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
regnum = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg_num;
reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg;
uni_load_reg(sc, val, regnum, reg, VIASR);
/* set display FIFO high threshold select */
val = IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
regnum = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg_num;
reg = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg;
uni_load_reg(sc, val, regnum, reg, VIASR);
/* set display queue expire num */
val = IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga1_display_queue_expire_num);
regnum = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg_num;
reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg;
uni_load_reg(sc, val, regnum, reg, VIASR);
break;
default:
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
__func__);
break;
}
return;
}
static void
uni_set_depth(struct unichromefb_softc *sc, int bpp, int iga)
{
switch (iga) {
case IGA1:
switch (bpp) {
case MODE_32BPP:
uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe);
break;
case MODE_16BPP:
uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe);
break;
case MODE_8BPP:
uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe);
break;
default:
printf("%s: %s: mode (%d) unsupported\n",
sc->sc_dev.dv_xname, __func__, bpp);
}
break;
default:
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
__func__);
break;
}
}
static uint32_t
uni_get_clkval(struct unichromefb_softc *sc, int clk)
{
int i;
for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
if (clk == pll_value[i].clk) {
/* XXX only CN900 supported for now */
return pll_value[i].k800_pll;
}
}
aprint_error("%s: can't find matching PLL value\n",
sc->sc_dev.dv_xname);
return 0;
}
static void
uni_set_vclk(struct unichromefb_softc *sc, uint32_t clk, int iga)
{
uint8_t val;
/* hardware reset on */
uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7);
switch (iga) {
case IGA1:
/* XXX only CN900 is supported */
uni_wr(sc, VIASR, SR44, clk / 0x10000);
uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100);
uni_wr(sc, VIASR, SR46, clk % 0x100);
break;
default:
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
__func__);
break;
}
/* hardware reset off */
uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7);
/* reset pll */
switch (iga) {
case IGA1:
uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1);
uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1);
break;
}
/* good to go */
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc);
val |= (BIT2+BIT3);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, val);
return;
}
/* XXX */
int
unichromefb_cnattach(void)
{
return 0;
}

675
sys/dev/pci/unichromehw.h Normal file
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@ -0,0 +1,675 @@
/* $NetBSD: unichromehw.h,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */
/*
* Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DEV_PCI_UNICHROMEHW_H
#define _DEV_PCI_UNICHROMEHW_H
//***************************************************//
//* Definition IGA1 Design Method of CRTC Registers *//
//***************************************************//
#define IGA1_HOR_TOTAL_FORMULA(x) ((x)/8)-5
#define IGA1_HOR_ADDR_FORMULA(x) ((x)/8)-1
#define IGA1_HOR_BLANK_START_FORMULA(x) ((x)/8)-1
#define IGA1_HOR_BLANK_END_FORMULA(x,y) ((x+y)/8)-1
#define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8)-1
#define IGA1_HOR_SYNC_END_FORMULA(x,y) ((x+y)/8)-1
#define IGA1_VER_TOTAL_FORMULA(x) (x)-2
#define IGA1_VER_ADDR_FORMULA(x) (x)-1
#define IGA1_VER_BLANK_START_FORMULA(x) (x)-1
#define IGA1_VER_BLANK_END_FORMULA(x,y) (x+y)-1
#define IGA1_VER_SYNC_START_FORMULA(x) (x)-1
#define IGA1_VER_SYNC_END_FORMULA(x,y) (x+y)-1
//***************************************************//
//* Definition IGA2 Design Method of CRTC Registers *//
//***************************************************//
#define IGA2_HOR_TOTAL_FORMULA(x) (x)-1
#define IGA2_HOR_ADDR_FORMULA(x) (x)-1
#define IGA2_HOR_BLANK_START_FORMULA(x) (x)-1
#define IGA2_HOR_BLANK_END_FORMULA(x,y) (x+y)-1
#define IGA2_HOR_SYNC_START_FORMULA(x) (x)-1
#define IGA2_HOR_SYNC_END_FORMULA(x,y) (x+y)-1
#define IGA2_VER_TOTAL_FORMULA(x) (x)-1
#define IGA2_VER_ADDR_FORMULA(x) (x)-1
#define IGA2_VER_BLANK_START_FORMULA(x) (x)-1
#define IGA2_VER_BLANK_END_FORMULA(x,y) (x+y)-1
#define IGA2_VER_SYNC_START_FORMULA(x) (x)-1
#define IGA2_VER_SYNC_END_FORMULA(x,y) (x+y)-1
/**********************************************************/
/* Definition IGA2 Design Method of CRTC Shadow Registers */
/**********************************************************/
#define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) (x/8)-5
#define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x,y) ((x+y)/8)-1
#define IGA2_VER_TOTAL_SHADOW_FORMULA(x) (x)-2
#define IGA2_VER_ADDR_SHADOW_FORMULA(x) (x)-1
#define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) (x)-1
#define IGA2_VER_BLANK_END_SHADOW_FORMULA(x,y) (x+y)-1
#define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
#define IGA2_VER_SYNC_END_SHADOW_FORMULA(x,y) (x+y)
/* Define Register Number for IGA1 CRTC Timing */
#define IGA1_HOR_TOTAL_REG_NUM 2 // location: {CR00,0,7},{CR36,3,3}
#define IGA1_HOR_ADDR_REG_NUM 1 // location: {CR01,0,7}
#define IGA1_HOR_BLANK_START_REG_NUM 1 // location: {CR02,0,7}
#define IGA1_HOR_BLANK_END_REG_NUM 3 // location: {CR03,0,4},{CR05,7,7},{CR33,5,5}
#define IGA1_HOR_SYNC_START_REG_NUM 2 // location: {CR04,0,7},{CR33,4,4}
#define IGA1_HOR_SYNC_END_REG_NUM 1 // location: {CR05,0,4}
#define IGA1_VER_TOTAL_REG_NUM 4 // location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0}
#define IGA1_VER_ADDR_REG_NUM 4 // location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2}
#define IGA1_VER_BLANK_START_REG_NUM 4 // location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3}
#define IGA1_VER_BLANK_END_REG_NUM 1 // location: {CR16,0,7}
#define IGA1_VER_SYNC_START_REG_NUM 4 // location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1}
#define IGA1_VER_SYNC_END_REG_NUM 1 // location: {CR11,0,3}
/* Define Register Number for IGA2 Shadow CRTC Timing */
#define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2 // location: {CR6D,0,7},{CR71,3,3}
#define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1 // location: {CR6E,0,7}
#define IGA2_SHADOW_VER_TOTAL_REG_NUM 2 // location: {CR6F,0,7},{CR71,0,2}
#define IGA2_SHADOW_VER_ADDR_REG_NUM 2 // location: {CR70,0,7},{CR71,4,6}
#define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2 // location: {CR72,0,7},{CR74,4,6}
#define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2 // location: {CR73,0,7},{CR74,0,2}
#define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2 // location: {CR75,0,7},{CR76,4,6}
#define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1 // location: {CR76,0,3}
/* Define Register Number for IGA2 CRTC Timing */
#define IGA2_HOR_TOTAL_REG_NUM 2 // location: {CR50,0,7},{CR55,0,3}
#define IGA2_HOR_ADDR_REG_NUM 2 // location: {CR51,0,7},{CR55,4,6}
#define IGA2_HOR_BLANK_START_REG_NUM 2 // location: {CR52,0,7},{CR54,0,2}
#define IGA2_HOR_BLANK_END_REG_NUM 3 // location: {CR53,0,7},{CR54,3,5},{CR5D,6,6}
#define IGA2_HOR_SYNC_START_REG_NUM 3 // location: {CR56,0,7},{CR54,6,7},{CR5C,7,7}
#define IGA2_HOR_SYNC_END_REG_NUM 2 // location: {CR57,0,7},{CR5C,6,6}
#define IGA2_VER_TOTAL_REG_NUM 2 // location: {CR58,0,7},{CR5D,0,2}
#define IGA2_VER_ADDR_REG_NUM 2 // location: {CR59,0,7},{CR5D,3,5}
#define IGA2_VER_BLANK_START_REG_NUM 2 // location: {CR5A,0,7},{CR5C,0,2}
#define IGA2_VER_BLANK_END_REG_NUM 2 // location: {CR5E,0,7},{CR5C,3,5}
#define IGA2_VER_SYNC_START_REG_NUM 2 // location: {CR5E,0,7},{CR5F,5,7}
#define IGA2_VER_SYNC_END_REG_NUM 1 // location: {CR5F,0,4}
/* Define Offset and Fetch Count Register*/
#define IGA1_OFFSET_REG_NUM 2 // location: {CR13,0,7},{CR35,5,7}
#define IGA1_OFFSER_ALIGN_BYTE 8 // 8 bytes alignment.
#define IGA1_OFFSET_FORMULA(x,y) (x*y)/IGA1_OFFSER_ALIGN_BYTE // x: H resolution, y: color depth
#define IGA1_FETCH_COUNT_REG_NUM 2 // location: {SR1C,0,7},{SR1D,0,1}
#define IGA1_FETCH_COUNT_ALIGN_BYTE 16 // 16 bytes alignment.
#define IGA1_FETCH_COUNT_PATCH_VALUE 4 // x: H resolution, y: color depth
#define IGA1_FETCH_COUNT_FORMULA(x,y) ((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE)+ IGA1_FETCH_COUNT_PATCH_VALUE
#define IGA2_OFFSET_REG_NUM 2 // location: {CR66,0,7},{CR67,0,1}
#define IGA2_OFFSET_ALIGN_BYTE 8
#define IGA2_OFFSET_FORMULA(x,y) (x*y)/IGA2_OFFSET_ALIGN_BYTE // x: H resolution, y: color depth
#define IGA2_FETCH_COUNT_REG_NUM 2 // location: {CR65,0,7},{CR67,2,3}
#define IGA2_FETCH_COUNT_ALIGN_BYTE 16
#define IGA2_FETCH_COUNT_PATCH_VALUE 0
#define IGA2_FETCH_COUNT_FORMULA(x,y) ((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE)+ IGA2_FETCH_COUNT_PATCH_VALUE
// Staring Address
#define IGA1_STARTING_ADDR_REG_NUM 4 // location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}
#define IGA2_STARTING_ADDR_REG_NUM 3 // location: {CR62,1,7},{CR63,0,7},{CR64,0,7}
// Define Display OFFSET
// These value are by HW suggested value
#define K800_IGA1_FIFO_MAX_DEPTH 384 // location: {SR17,0,7}
#define K800_IGA1_FIFO_THRESHOLD 328 // location: {SR16,0,5},{SR16,7,7}
#define K800_IGA1_FIFO_HIGH_THRESHOLD 296 // location: {SR18,0,5},{SR18,7,7}
#define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 // location: {SR22,0,4}. (128/4) =64, K800 must be set zero,
// because HW only 5 bits
#define K800_IGA2_FIFO_MAX_DEPTH 384 // location: {CR68,4,7},{CR94,7,7},{CR95,7,7}
#define K800_IGA2_FIFO_THRESHOLD 328 // location: {CR68,0,3},{CR95,4,6}
#define K800_IGA2_FIFO_HIGH_THRESHOLD 296 // location: {CR92,0,3},{CR95,0,2}
#define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 // location: {CR94,0,6}
#define P880_IGA1_FIFO_MAX_DEPTH 192 // location: {SR17,0,7}
#define P880_IGA1_FIFO_THRESHOLD 128 // location: {SR16,0,5},{SR16,7,7}
#define P880_IGA1_FIFO_HIGH_THRESHOLD 64 // location: {SR18,0,5},{SR18,7,7}
#define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 // location: {SR22,0,4}. (128/4) =64, K800 must be set zero,
// because HW only 5 bits
#define P880_IGA2_FIFO_MAX_DEPTH 96 // location: {CR68,4,7},{CR94,7,7},{CR95,7,7}
#define P880_IGA2_FIFO_THRESHOLD 64 // location: {CR68,0,3},{CR95,4,6}
#define P880_IGA2_FIFO_HIGH_THRESHOLD 32 // location: {CR92,0,3},{CR95,0,2}
#define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 // location: {CR94,0,6}
/* VT3314 chipset*/
#define CN900_IGA1_FIFO_MAX_DEPTH 96 /* location: {SR17,0,7}*/
#define CN900_IGA1_FIFO_THRESHOLD 80 /* location: {SR16,0,5},{SR16,7,7}*/
#define CN900_IGA1_FIFO_HIGH_THRESHOLD 64 /* location: {SR18,0,5},{SR18,7,7}*/
#define CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, because HW only 5 bits*/
#define CN900_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/
#define CN900_IGA2_FIFO_THRESHOLD 80 /* location: {CR68,0,3},{CR95,4,6}*/
#define CN900_IGA2_FIFO_HIGH_THRESHOLD 32 /* location: {CR92,0,3},{CR95,0,2}*/
#define CN900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 /* location: {CR94,0,6}*/
/* For VT3324, these values are suggested by HW */
#define CX700_IGA1_FIFO_MAX_DEPTH 192 /* location: {SR17,0,7}*/
#define CX700_IGA1_FIFO_THRESHOLD 128 /* location: {SR16,0,5},{SR16,7,7}*/
#define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 /* location: {SR18,0,5},{SR18,7,7} */
#define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 /* location: {SR22,0,4} */
#define CX700_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/
#define CX700_IGA2_FIFO_THRESHOLD 64 /* location: {CR68,0,3},{CR95,4,6}*/
#define CX700_IGA2_FIFO_HIGH_THRESHOLD 32 /* location: {CR92,0,3},{CR95,0,2} */
#define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 /* location: {CR94,0,6}*/
#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
#define IGA1_FIFO_THRESHOLD_REG_NUM 2
#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
#define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
#define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3
#define IGA2_FIFO_THRESHOLD_REG_NUM 2
#define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2
#define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) (x/2)-1
#define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4)
#define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
#define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)/4)-1
#define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4)
#define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
#define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
/************************************************************************/
/* LCD Timing */
/************************************************************************/
#define LCD_POWER_SEQ_TD0 500000 // 500 ms = 500000 us
#define LCD_POWER_SEQ_TD1 50000 // 50 ms = 50000 us
#define LCD_POWER_SEQ_TD2 0 // 0 us
#define LCD_POWER_SEQ_TD3 210000 // 210 ms = 210000 us
#define CLE266_POWER_SEQ_UNIT 71 // 2^10 * (1/14.31818M) = 71.475 us (K400.revA)
#define K800_POWER_SEQ_UNIT 142 // 2^11 * (1/14.31818M) = 142.95 us (K400.revB)
#define P880_POWER_SEQ_UNIT 572 // 2^13 * (1/14.31818M) = 572.1 us
#define CLE266_POWER_SEQ_FORMULA(x) (x)/CLE266_POWER_SEQ_UNIT
#define K800_POWER_SEQ_FORMULA(x) (x)/K800_POWER_SEQ_UNIT
#define P880_POWER_SEQ_FORMULA(x) (x)/P880_POWER_SEQ_UNIT
#define LCD_POWER_SEQ_TD0_REG_NUM 2 // location: {CR8B,0,7},{CR8F,0,3}
#define LCD_POWER_SEQ_TD1_REG_NUM 2 // location: {CR8C,0,7},{CR8F,4,7}
#define LCD_POWER_SEQ_TD2_REG_NUM 2 // location: {CR8D,0,7},{CR90,0,3}
#define LCD_POWER_SEQ_TD3_REG_NUM 2 // location: {CR8E,0,7},{CR90,4,7}
// LCD Scaling factor
// x: indicate setting horizontal size
// y: indicate panel horizontal size
#define CLE266_LCD_HOR_SCF_FORMULA(x,y) (((x-1)*1024)/(y-1)) // Horizontal scaling factor 10 bits (2^10)
#define CLE266_LCD_VER_SCF_FORMULA(x,y) (((x-1)*1024)/(y-1)) // Vertical scaling factor 10 bits (2^10)
#define K800_LCD_HOR_SCF_FORMULA(x,y) (((x-1)*4096)/(y-1)) // Horizontal scaling factor 10 bits (2^12)
#define K800_LCD_VER_SCF_FORMULA(x,y) (((x-1)*2048)/(y-1)) // Vertical scaling factor 10 bits (2^11)
#define LCD_HOR_SCALING_FACTOR_REG_NUM 3 // location: {CR9F,0,1},{CR77,0,7},{CR79,4,5}
#define LCD_VER_SCALING_FACTOR_REG_NUM 3 // location: {CR79,3,3},{CR78,0,7},{CR79,6,7}
#define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2 /* location: {CR77,0,7},{CR79,4,5} */
#define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2 /* location: {CR78,0,7},{CR79,6,7} */
//************************************************//
//* Define IGA1 Display Timing *//
//************************************************//
struct io_register {
uint8_t io_addr;
uint8_t start_bit;
uint8_t end_bit;
};
/* IGA1 Horizontal Total */
struct iga1_hor_total
{
int reg_num;
struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
};
/* IGA1 Horizontal Addressable Video */
struct iga1_hor_addr {
int reg_num;
struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
};
/* IGA1 Horizontal Blank Start */
struct iga1_hor_blank_start {
int reg_num;
struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
};
/* IGA1 Horizontal Blank End */
struct iga1_hor_blank_end {
int reg_num;
struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
};
/* IGA1 Horizontal Sync Start */
struct iga1_hor_sync_start {
int reg_num;
struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
};
/* IGA1 Horizontal Sync End */
struct iga1_hor_sync_end {
int reg_num;
struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
};
/* IGA1 Vertical Total */
struct iga1_ver_total {
int reg_num;
struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
};
/* IGA1 Vertical Addressable Video */
struct iga1_ver_addr {
int reg_num;
struct io_register reg[IGA1_VER_ADDR_REG_NUM];
};
/* IGA1 Vertical Blank Start */
struct iga1_ver_blank_start {
int reg_num;
struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
};
/* IGA1 Vertical Blank End */
struct iga1_ver_blank_end {
int reg_num;
struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
};
/* IGA1 Vertical Sync Start */
struct iga1_ver_sync_start {
int reg_num;
struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
};
/* IGA1 Vertical Sync End */
struct iga1_ver_sync_end {
int reg_num;
struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
};
//************************************************//
// Define IGA2 Shadow Display Timing //
//************************************************//
/* IGA2 Shadow Horizontal Total */
struct iga2_shadow_hor_total
{
int reg_num;
struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
};
/* IGA2 Shadow Horizontal Blank End */
struct iga2_shadow_hor_blank_end {
int reg_num;
struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
};
/* IGA2 Shadow Vertical Total */
struct iga2_shadow_ver_total {
int reg_num;
struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
};
/* IGA2 Shadow Vertical Addressable Video */
struct iga2_shadow_ver_addr {
int reg_num;
struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
};
/* IGA2 Shadow Vertical Blank Start */
struct iga2_shadow_ver_blank_start {
int reg_num;
struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
};
/* IGA2 Shadow Vertical Blank End */
struct iga2_shadow_ver_blank_end {
int reg_num;
struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
};
/* IGA2 Shadow Vertical Sync Start */
struct iga2_shadow_ver_sync_start {
int reg_num;
struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
};
/* IGA2 Shadow Vertical Sync End */
struct iga2_shadow_ver_sync_end {
int reg_num;
struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
};
//************************************************//
// Define IGA2 Display Timing //
//************************************************//
/* IGA2 Horizontal Total */
struct iga2_hor_total {
int reg_num;
struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
};
/* IGA2 Horizontal Addressable Video */
struct iga2_hor_addr {
int reg_num;
struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
};
/* IGA2 Horizontal Blank Start */
struct iga2_hor_blank_start {
int reg_num;
struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
};
/* IGA2 Horizontal Blank End */
struct iga2_hor_blank_end {
int reg_num;
struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
};
/* IGA2 Horizontal Sync Start */
struct iga2_hor_sync_start {
int reg_num;
struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
};
/* IGA2 Horizontal Sync End */
struct iga2_hor_sync_end {
int reg_num;
struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
};
/* IGA2 Vertical Total */
struct iga2_ver_total {
int reg_num;
struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
};
/* IGA2 Vertical Addressable Video */
struct iga2_ver_addr {
int reg_num;
struct io_register reg[IGA2_VER_ADDR_REG_NUM];
};
/* IGA2 Vertical Blank Start */
struct iga2_ver_blank_start {
int reg_num;
struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
};
/* IGA2 Vertical Blank End */
struct iga2_ver_blank_end {
int reg_num;
struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
};
/* IGA2 Vertical Sync Start */
struct iga2_ver_sync_start {
int reg_num;
struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
};
/* IGA2 Vertical Sync End */
struct iga2_ver_sync_end {
int reg_num;
struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
};
/* IGA1 Offset Register */
struct iga1_offset {
int reg_num;
struct io_register reg[IGA1_OFFSET_REG_NUM];
};
/* IGA2 Offset Register */
struct iga2_offset {
int reg_num;
struct io_register reg[IGA2_OFFSET_REG_NUM];
};
struct offset{
struct iga1_offset iga1_offset_reg;
struct iga2_offset iga2_offset_reg;
};
/* IGA1 Fetch Count Register */
struct iga1_fetch_count {
int reg_num;
struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
};
/* IGA2 Fetch Count Register */
struct iga2_fetch_count {
int reg_num;
struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
};
struct fetch_count{
struct iga1_fetch_count iga1_fetch_count_reg;
struct iga2_fetch_count iga2_fetch_count_reg;
};
/* Starting Address Register */
struct iga1_starting_addr {
int reg_num;
struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
};
struct iga2_starting_addr {
int reg_num;
struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
};
struct starting_addr {
struct iga1_starting_addr iga1_starting_addr_reg;
struct iga2_starting_addr iga2_starting_addr_reg;
};
/* LCD Power Sequence Timer */
struct lcd_pwd_seq_td0{
int reg_num;
struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
};
struct lcd_pwd_seq_td1{
int reg_num;
struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
};
struct lcd_pwd_seq_td2{
int reg_num;
struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
};
struct lcd_pwd_seq_td3{
int reg_num;
struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
};
struct _lcd_pwd_seq_timer{
struct lcd_pwd_seq_td0 td0;
struct lcd_pwd_seq_td1 td1;
struct lcd_pwd_seq_td2 td2;
struct lcd_pwd_seq_td3 td3;
};
/* LCD Scaling Factor */
struct _lcd_hor_scaling_factor{
int reg_num;
struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
};
struct _lcd_ver_scaling_factor{
int reg_num;
struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
};
struct _lcd_scaling_factor{
struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
};
struct pll_map {
uint32_t clk;
uint32_t cle266_pll;
uint32_t k800_pll;
uint32_t cx700_pll;
};
struct rgbLUT {
uint8_t red;
uint8_t green;
uint8_t blue;
};
struct lcd_pwd_seq_timer {
uint16_t td0;
uint16_t td1;
uint16_t td2;
uint16_t td3;
};
// Display FIFO Relation Registers
struct iga1_fifo_depth_select {
int reg_num;
struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
};
struct iga1_fifo_threshold_select {
int reg_num;
struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
};
struct iga1_fifo_high_threshold_select {
int reg_num;
struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
};
struct iga1_display_queue_expire_num {
int reg_num;
struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
};
struct iga2_fifo_depth_select {
int reg_num;
struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
};
struct iga2_fifo_threshold_select {
int reg_num;
struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
};
struct iga2_fifo_high_threshold_select {
int reg_num;
struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
};
struct iga2_display_queue_expire_num {
int reg_num;
struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
};
struct fifo_depth_select {
struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
};
struct fifo_threshold_select {
struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
};
struct fifo_high_threshold_select {
struct iga1_fifo_high_threshold_select iga1_fifo_high_threshold_select_reg;
struct iga2_fifo_high_threshold_select iga2_fifo_high_threshold_select_reg;
};
struct display_queue_expire_num {
struct iga1_display_queue_expire_num iga1_display_queue_expire_num_reg;
struct iga2_display_queue_expire_num iga2_display_queue_expire_num_reg;
};
struct iga1_crtc_timing {
struct iga1_hor_total hor_total;
struct iga1_hor_addr hor_addr;
struct iga1_hor_blank_start hor_blank_start;
struct iga1_hor_blank_end hor_blank_end;
struct iga1_hor_sync_start hor_sync_start;
struct iga1_hor_sync_end hor_sync_end;
struct iga1_ver_total ver_total;
struct iga1_ver_addr ver_addr;
struct iga1_ver_blank_start ver_blank_start;
struct iga1_ver_blank_end ver_blank_end;
struct iga1_ver_sync_start ver_sync_start;
struct iga1_ver_sync_end ver_sync_end;
};
struct iga2_shadow_crtc_timing {
struct iga2_shadow_hor_total hor_total_shadow;
struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
struct iga2_shadow_ver_total ver_total_shadow;
struct iga2_shadow_ver_addr ver_addr_shadow;
struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
};
struct iga2_crtc_timing {
struct iga2_hor_total hor_total;
struct iga2_hor_addr hor_addr;
struct iga2_hor_blank_start hor_blank_start;
struct iga2_hor_blank_end hor_blank_end;
struct iga2_hor_sync_start hor_sync_start;
struct iga2_hor_sync_end hor_sync_end;
struct iga2_ver_total ver_total;
struct iga2_ver_addr ver_addr;
struct iga2_ver_blank_start ver_blank_start;
struct iga2_ver_blank_end ver_blank_end;
struct iga2_ver_sync_start ver_sync_start;
struct iga2_ver_sync_end ver_sync_end;
};
#endif /* _DEV_PCI_UNICHROMEHW_H */

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/* $NetBSD: unichromemode.h,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */
/*
* Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DEV_PCI_UNICHROMEMODE_H
#define _DEV_PCI_UNICHROMEMODE_H
#define ARRAY_SIZE(x) (sizeof((x)) / sizeof((x)[0]))
struct VPITTable {
unsigned char Misc;
unsigned char SR[StdSR];
unsigned char GR[StdGR];
unsigned char AR[StdAR];
};
struct VideoModeTable {
int ModeIndex;
struct crt_mode_table *crtc;
int mode_array;
};
struct patch_table {
int mode_index;
int table_length;
struct io_reg *io_reg_table;
};
struct res_map_refresh {
int hres;
int vres;
int pixclock;
int vmode_refresh;
};
struct res_map_refresh res_map_refresh_tbl[] = {
//hres, vres, vclock, vmode_refresh
{640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
{640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
{640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
{640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
{640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
{720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
{720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
{800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
{800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
{800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
{800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
{800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
{800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
{848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
{856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
{1024,512, RES_1024X512_60HZ_PIXCLOCK, 60},
{1024,768, RES_1024X768_60HZ_PIXCLOCK, 60},
{1024,768, RES_1024X768_75HZ_PIXCLOCK, 75},
{1024,768, RES_1024X768_85HZ_PIXCLOCK, 85},
{1024,768, RES_1024X768_100HZ_PIXCLOCK, 100},
{1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},
{1152,864, RES_1152X864_75HZ_PIXCLOCK, 75},
{1280,768, RES_1280X768_60HZ_PIXCLOCK, 60},
{1280,960, RES_1280X960_60HZ_PIXCLOCK, 60},
{1280,1024,RES_1280X1024_60HZ_PIXCLOCK, 60},
{1280,1024,RES_1280X1024_75HZ_PIXCLOCK, 75},
{1280,1024,RES_1280X768_85HZ_PIXCLOCK, 85},
{1440,1050,RES_1440X1050_60HZ_PIXCLOCK, 60},
{1600,1200,RES_1600X1200_60HZ_PIXCLOCK, 60},
{1600,1200,RES_1600X1200_75HZ_PIXCLOCK, 75},
{1280,720, RES_1280X720_60HZ_PIXCLOCK, 60},
{1920,1080,RES_1920X1080_60HZ_PIXCLOCK, 60},
{1400,1050,RES_1400X1050_60HZ_PIXCLOCK, 60},
{1366,768, RES_1366X768_60HZ_PIXCLOCK,60}
};
#define NUM_TOTAL_RES_MAP_REFRESH ARRAY_SIZE(res_map_refresh_tbl)
struct io_reg CN400_ModeXregs[] = {
{VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xF0, 0x00},
{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00}
};
#define NUM_TOTAL_CN400_ModeXregs ARRAY_SIZE(CN400_ModeXregs)
/* Video Mode Table for VT3314 chipset*/
/* Common Setting for Video Mode */
struct io_reg CN900_ModeXregs[] = {
{VIASR,SR10,0xFF,0x01},
{VIASR,SR15,0x02,0x02},
{VIASR,SR16,0xBF,0x08},
{VIASR,SR17,0xFF,0x1F},
{VIASR,SR18,0xFF,0x4E},
{VIASR,SR1A,0xFB,0x82},
{VIASR,SR1B,0xFF,0xF0},
{VIASR,SR1F,0xFF,0x00},
{VIASR,SR1E,0xFF,0xF1},
{VIASR,SR22,0xFF,0x1F},
{VIASR,SR2A,0x0F,0x0F},
{VIASR,SR2E,0xFF,0xFF},
{VIASR,SR3F,0xFF,0xFF},
{VIASR,SR40,0xFF,0x00},
{VIASR,CR30,0xFF,0x04},
{VIACR,CR32,0xFF,0x00},
{VIACR,CR33,0xFF,0x00},
{VIACR,CR34,0xFF,0x00},
{VIACR,CR35,0xFF,0x00},
{VIACR,CR36,0xFF,0x31},
{VIACR,CR41,0xFF,0x80},
{VIACR,CR42,0xFF,0x00},
{VIACR,CR5D,0x80,0x00}, /* Horizontal Retrace Start bit [11] should be 0*/
{VIACR,CR62,0xFF,0x00}, /* Secondary Display Starting Address*/
{VIACR,CR63,0xFF,0x00}, /* Secondary Display Starting Address*/
{VIACR,CR64,0xFF,0x00}, /* Secondary Display Starting Address*/
{VIACR,CR68,0xFF,0x67}, /* Default FIFO For IGA2 */
{VIACR,CR69,0xFF,0x00},
{VIACR,CR6A,0xFF,0x40},
{VIACR,CR6B,0xFF,0x00},
{VIACR,CR6C,0xFF,0x00},
{VIACR,CR77,0xFF,0x00}, /* LCD scaling Factor*/
{VIACR,CR78,0xFF,0x00}, /* LCD scaling Factor */
{VIACR,CR79,0xFF,0x00}, /* LCD scaling Factor*/
{VIACR,CR9F,0x03,0x00}, /* LCD scaling Factor */
{VIACR,CR7A,0xFF,0x01}, /* LCD Scaling Parameter 1*/
{VIACR,CR7B,0xFF,0x02}, /* LCD Scaling Parameter 2*/
{VIACR,CR7C,0xFF,0x03}, /* LCD Scaling Parameter 3 */
{VIACR,CR7D,0xFF,0x04}, /* LCD Scaling Parameter 4*/
{VIACR,CR7E,0xFF,0x07}, /* LCD Scaling Parameter 5*/
{VIACR,CR7F,0xFF,0x0A}, /* LCD Scaling Parameter 6*/
{VIACR,CR80,0xFF,0x0D}, /* LCD Scaling Parameter 7*/
{VIACR,CR81,0xFF,0x13}, /* LCD Scaling Parameter 8*/
{VIACR,CR82,0xFF,0x16}, /* LCD Scaling Parameter 9*/
{VIACR,CR83,0xFF,0x19}, /* LCD Scaling Parameter 10*/
{VIACR,CR84,0xFF,0x1C}, /* LCD Scaling Parameter 11*/
{VIACR,CR85,0xFF,0x1D}, /* LCD Scaling Parameter 12*/
{VIACR,CR86,0xFF,0x1E}, /* LCD Scaling Parameter 13*/
{VIACR,CR87,0xFF,0x1F}, /* LCD Scaling Parameter 14*/
{VIACR,CR88,0xFF,0x40}, /* LCD Panel Type */
{VIACR,CR89,0xFF,0x00}, /* LCD Timing Control 0 */
{VIACR,CR8A,0xFF,0x88}, /* LCD Timing Control 1*/
{VIACR,CR8B,0xFF,0x69}, /* LCD Power Sequence Control 0*/
{VIACR,CR8C,0xFF,0x57}, /* LCD Power Sequence Control 1*/
{VIACR,CR8D,0xFF,0x00}, /* LCD Power Sequence Control 2*/
{VIACR,CR8E,0xFF,0x7B}, /* LCD Power Sequence Control 3*/
{VIACR,CR8F,0xFF,0x03}, /* LCD Power Sequence Control 4*/
{VIACR,CR90,0xFF,0x30}, /* LCD Power Sequence Control 5*/
{VIACR,CR91,0xFF,0xA0}, /* 24/12 bit LVDS Data off*/
{VIACR,CR96,0xFF,0x00},
{VIACR,CR97,0xFF,0x00},
{VIACR,CR99,0xFF,0x00},
{VIACR,CR9B,0xFF,0x00},
{VIACR,CR9D,0xFF,0x80},
{VIACR,CR9E,0xFF,0x80}
};
#define NUM_TOTAL_CN900_ModeXregs ARRAY_SIZE(CN900_ModeXregs)
struct io_reg KM400_ModeXregs[] = {
{VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
{VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
{VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
{VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
{VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
{VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
{VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
{VIASR, SR1E, 0x0F, 0x01}, /* Power Management Control */
{VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
{VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
{VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
{VIASR, SR2A, 0xF0, 0x00}, /* Power Management Control 5 */
{VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
{VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00},
{VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
{VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x03}, /* TV on DVP0 ; DVP0 Clock Skew */
{VIACR, CR97, 0xFF, 0x03}, /* TV on DFP high ; DFPH Clock Skew */
{VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew */
{VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew */
};
#define NUM_TOTAL_KM400_ModeXregs ARRAY_SIZE(KM400_ModeXregs)
/* For VT3324: Common Setting for Video Mode */
struct io_reg CX700_ModeXregs[] = {
{VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xF0, 0x00},
{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CRD2, 0xFF, 0x03} /* LVDS0/LVDS1 Channel format. */
};
#define NUM_TOTAL_CX700_ModeXregs ARRAY_SIZE(CX700_ModeXregs)
/* Video Mode Table */
/* Common Setting for Video Mode */
struct io_reg CLE266_ModeXregs[] = {
{VIASR,SR1E,0xF0,0xF0},
{VIASR,SR2A,0x0F,0x0F},
{VIASR,SR15,0x02,0x02},
{VIASR,SR16,0xBF,0x08},
{VIASR,SR17,0xFF,0x1F},
{VIASR,SR18,0xFF,0x4E},
{VIASR,SR1A,0xFB,0x08},
{VIACR,CR32,0xFF,0x00},
// {VIACR,CR33,0xFF,0x08}, // for K800 prefetch mode
{VIACR,CR34,0xFF,0x00},
{VIACR,CR35,0xFF,0x00},
{VIACR,CR36,0x08,0x00},
{VIACR,CR6A,0xFF,0x80},
{VIACR,CR6A,0xFF,0xC0},
{VIACR,CR55,0x80,0x00},
{VIACR,CR5D,0x80,0x00},
{VIAGR,GR20,0xFF,0x00},
{VIAGR,GR21,0xFF,0x00},
{VIAGR,GR22,0xFF,0x00},
// LCD Parameters
{VIACR,CR7A,0xFF,0x01}, // LCD Parameter 1
{VIACR,CR7B,0xFF,0x02}, // LCD Parameter 2
{VIACR,CR7C,0xFF,0x03}, // LCD Parameter 3
{VIACR,CR7D,0xFF,0x04}, // LCD Parameter 4
{VIACR,CR7E,0xFF,0x07}, // LCD Parameter 5
{VIACR,CR7F,0xFF,0x0A}, // LCD Parameter 6
{VIACR,CR80,0xFF,0x0D}, // LCD Parameter 7
{VIACR,CR81,0xFF,0x13}, // LCD Parameter 8
{VIACR,CR82,0xFF,0x16}, // LCD Parameter 9
{VIACR,CR83,0xFF,0x19}, // LCD Parameter 10
{VIACR,CR84,0xFF,0x1C}, // LCD Parameter 11
{VIACR,CR85,0xFF,0x1D}, // LCD Parameter 12
{VIACR,CR86,0xFF,0x1E}, // LCD Parameter 13
{VIACR,CR87,0xFF,0x1F}, // LCD Parameter 14
};
#define NUM_TOTAL_CLE266_ModeXregs ARRAY_SIZE(CLE266_ModeXregs)
/* Mode:1024X768 */
struct io_reg PM1024x768[] = {
{VIASR,0x16,0xBF,0x0C},
{VIASR,0x18,0xFF,0x4C}
};
struct patch_table res_patch_table[]= {
{VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768}
};
#define NUM_TOTAL_PATCH_MODE ARRAY_SIZE(res_patch_table)
// struct VPITTable {
// unsigned char Misc;
// unsigned char SR[StdSR];
// unsigned char CR[StdCR];
// unsigned char GR[StdGR];
// unsigned char AR[StdAR];
// };
struct VPITTable VPIT = {
// Msic
0xC7,
// Sequencer
{0x01,0x0F,0x00,0x0E },
// Graphic Controller
{0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF},
// Attribute Controller
{0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
0x01,0x00,0x0F,0x00}
};
/********************/
/* Mode Table */
/********************/
// 640x480
struct crt_mode_table CRTM640x480[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60, CLK_25_175M ,M640X480_R60_HSP, M640X480_R60_VSP,\
{800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2}},
{REFRESH_75, CLK_31_500M ,M640X480_R75_HSP, M640X480_R75_VSP,\
{840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3}},
{REFRESH_85, CLK_36_000M ,M640X480_R85_HSP, M640X480_R85_VSP,\
{832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3}},
{REFRESH_100,CLK_43_163M ,M640X480_R100_HSP, M640X480_R100_VSP,\
{848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3}}, //GTF
{REFRESH_120,CLK_52_406M ,M640X480_R120_HSP, M640X480_R120_VSP,\
{848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3}} //GTF
};
//720x480 (GTF)
struct crt_mode_table CRTM720x480[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_26_880M ,M720X480_R60_HSP, M720X480_R60_VSP,\
{896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3}}
};
//720x576 (GTF)
struct crt_mode_table CRTM720x576[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_32_668M ,M720X576_R60_HSP, M720X576_R60_VSP,\
{912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3}}
};
//800x480 (GTF)
struct crt_mode_table CRTM800x480[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_29_581M ,M800X480_R60_HSP,M800X480_R60_VSP,\
{992, 800, 800, 192, 816, 80, 497, 480, 480, 17, 481, 3}}
};
// 800x600
struct crt_mode_table CRTM800x600[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60, CLK_40_000M ,M800X600_R60_HSP, M800X600_R60_VSP,\
{1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4}},
{REFRESH_75, CLK_49_500M ,M800X600_R75_HSP, M800X600_R75_VSP,\
{1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3}},
{REFRESH_85, CLK_56_250M ,M800X600_R85_HSP, M800X600_R85_VSP,\
{1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3}},
{REFRESH_100,CLK_68_179M ,M800X600_R100_HSP, M800X600_R100_VSP,\
{1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3}}, //GTF
{REFRESH_120,CLK_83_950M ,M800X600_R120_HSP, M800X600_R120_VSP,\
{1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3}} //GTF
};
//848x480 (GTF)
struct crt_mode_table CRTM848x480[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_31_490M ,M848X480_R60_HSP, M848X480_R60_VSP,\
{1056, 848, 848, 208, 864, 88, 497, 480, 480, 17, 481, 3}}
};
//856x480 (GTF) convert to 852x480
struct crt_mode_table CRTM852x480[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_31_728M ,M852X480_R60_HSP, M852X480_R60_VSP,\
{1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3}}
};
//1024x512 (GTF)
struct crt_mode_table CRTM1024x512[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_41_291M ,M1024X512_R60_HSP, M1024X512_R60_VSP,\
{1296, 1024,1024,272, 1056,104, 531, 512, 512, 19, 513, 3}}
};
//1024x576 (GTF)
/*static struct crt_mode_table CRTM1024x576[] = {
//r_rate,vclk, HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{ 60,CLK_46_996M ,{1312, 1024,1024,288, 1064,104, 597, 576, 576, 21, 577, 3}}
};*/
// 1024x768
struct crt_mode_table CRTM1024x768[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_65_000M ,M1024X768_R60_HSP, M1024X768_R60_VSP,\
{1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6}},
{REFRESH_75,CLK_78_750M ,M1024X768_R75_HSP, M1024X768_R75_VSP,\
{1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3}},
{REFRESH_85,CLK_94_500M ,M1024X768_R85_HSP, M1024X768_R85_VSP,\
{1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3}},
{REFRESH_100,CLK_133_308M,M1024X768_R100_HSP, M1024X768_R100_VSP,\
{1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3}} //GTF
};
// 1152x864
struct crt_mode_table CRTM1152x864[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_75,CLK_108_000M ,M1152X864_R75_HSP, M1152X864_R75_VSP,\
{1600, 1152,1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3}}
};
// 1280x720 (GTF)
struct crt_mode_table CRTM1280x720[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_74_481M ,M1280X720_R60_HSP, M1280X720_R60_VSP,\
{1664,1280, 1280, 384, 1336, 136, 746, 720, 720, 26, 721, 3}}
};
//1280x768 (GTF)
struct crt_mode_table CRTM1280x768[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_80_136M ,M1280X768_R60_HSP, M1280X768_R60_VSP,\
{1680,1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3}}
};
//1280x960
struct crt_mode_table CRTM1280x960[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_108_000M ,M1280X960_R60_HSP, M1280X960_R60_VSP,\
{1800,1280, 1280, 520, 1376, 112, 1000,960, 960, 40, 961, 3}}
};
// 1280x1024
struct crt_mode_table CRTM1280x1024[] = {
//r_rate,vclk,,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_108_000M ,M1280X1024_R60_HSP, M1280X1024_R60_VSP,\
{1688,1280, 1280, 408, 1328, 112, 1066,1024,1024,42, 1025,3}},
{REFRESH_75,CLK_135_000M ,M1280X1024_R75_HSP, M1280X1024_R75_VSP,\
{1688,1280, 1280, 408, 1296, 144, 1066,1024,1024,42, 1025,3}},
{REFRESH_85,CLK_157_500M ,M1280X1024_R85_HSP, M1280X1024_R85_VSP,\
{1728,1280, 1280, 448, 1344, 160, 1072,1024,1024,48, 1025,3}}
};
/* 1366x768 (GTF) */
struct crt_mode_table CRTM1366x768[] = {
// r_rate, vclk, hsp, vsp
// HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,\
{1800,1366, 1366, 432, 1440, 144, 795, 768, 768, 27, 769, 3}}
};
//1368x768 (GTF)
/*static struct crt_mode_table CRTM1368x768[] = {
//r_rate,vclk, HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{ 60,CLK_85_860M ,{1800,1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3}}
};*/
//1440x1050 (GTF)
struct crt_mode_table CRTM1440x1050[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60 ,CLK_125_104M ,M1440X1050_R60_HSP, M1440X1050_R60_VSP,\
{1936,1440, 1440, 496, 1536, 152, 1077,1040,1040,37, 1041,3}}
};
// 1600x1200
struct crt_mode_table CRTM1600x1200[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60 ,CLK_162_000M ,M1600X1200_R60_HSP, M1600X1200_R60_VSP,\
{2160,1600, 1600, 560, 1664, 192, 1250,1200,1200,50, 1201,3}},
{REFRESH_75 ,CLK_202_500M ,M1600X1200_R75_HSP, M1600X1200_R75_VSP,\
{2160,1600, 1600, 560, 1664, 192, 1250,1200,1200,50, 1201,3}}
};
// 1920x1080 (GTF)
struct crt_mode_table CRTM1920x1080[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_172_798M ,M1920X1080_R60_HSP, M1920X1080_R60_VSP,\
{2576,1920, 1920, 656, 2040, 208, 1118,1080,1080,38, 1081, 3}}
};
// 1920x1440
struct crt_mode_table CRTM1920x1440[] = {
//r_rate,vclk,hsp,vsp
//HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE
{REFRESH_60,CLK_234_000M ,M1920X1440_R60_HSP, M1920X1440_R60_VSP,\
{2600,1920, 1920, 680, 2048, 208, 1500,1440,1440,60, 1441,3}},
{REFRESH_75,CLK_297_500M ,M1920X1440_R75_HSP, M1920X1440_R75_VSP,\
{2640,1920, 1920, 720, 2064, 224, 1500,1440,1440,60, 1441,3}}
};
/* 1400x1050 (VESA) */
struct crt_mode_table CRTM1400x1050[] = {
/* r_rate, vclk, hsp, vsp */
/* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
{REFRESH_60,CLK_108_000M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
{1688,1400, 1400, 288, 1448, 112, 1066,1050, 1050, 16, 1051, 3}}
};
/* Video Mode Table */
// struct VideoModeTable {
// int ModeIndex;
// struct crt_mode_table *crtc;
// int mode_array;
// };
struct VideoModeTable CLE266Modes[] = {
/* Display : 640x480 */
{ VIA_RES_640X480, CRTM640x480, ARRAY_SIZE(CRTM640x480)},
/* Display : 720x480 (GTF)*/
{ VIA_RES_720X480, CRTM720x480, ARRAY_SIZE(CRTM720x480)},
/* Display : 720x576 (GTF)*/
{ VIA_RES_720X576, CRTM720x576, ARRAY_SIZE(CRTM720x576)},
/* Display : 800x600 */
{ VIA_RES_800X600, CRTM800x600, ARRAY_SIZE(CRTM800x600)},
/* Display : 800x480 (GTF)*/
{ VIA_RES_800X480, CRTM800x480, ARRAY_SIZE(CRTM800x480)},
/* Display : 848x480 (GTF)*/
{ VIA_RES_848X480, CRTM848x480, ARRAY_SIZE(CRTM848x480)},
/* Display : 852x480 (GTF)*/
{ VIA_RES_856X480, CRTM852x480, ARRAY_SIZE(CRTM852x480)},
/* Display : 1024x512 (GTF)*/
{ VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
/* Display : 1024x576 (GTF)*/
//{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
/* Display : 1024x768 */
{ VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
/* Display : 1152x864 */
{ VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
/* Display : 1280x768 (GTF)*/
{ VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
/* Display : 1280x800 (GTF)*/
//{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
/* Display : 1280x960 */
{ VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
/* Display : 1280x1024 */
{ VIA_RES_1280X1024, CRTM1280x1024,ARRAY_SIZE(CRTM1280x1024)},
/* Display : 1368x768 (GTF)*/
//{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)},
/* Display : 1366x768 (GTF)*/
{ VIA_RES_1366X768,CRTM1366x768,ARRAY_SIZE(CRTM1366x768)},
/* Display : 1440x1050 (GTF)*/
{ VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
/* Display : 1600x1200 */
{ VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
/* Display : 1920x1440 */
{ VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
/* Display : 1280x720 */
{ VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
/* Display : 1920x1080 */
{ VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
/* Display : 1400x1050 */
{ VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
};
#define NUM_TOTAL_MODETABLE ARRAY_SIZE(CLE266Modes)
#endif /* _DEV_PCI_UNICHROMEMODE_H */

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sys/dev/pci/unichromereg.h Normal file
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/* $NetBSD: unichromereg.h,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */
/*
* Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DEV_PCI_UNICHROMEREG_H
#define _DEV_PCI_UNICHROMEREG_H
/* Define Return Value */
#define FAIL -1
#define OK 1
/* S.T.Chen[2005.12.26]: Define Boolean Value */
#ifndef bool
typedef int bool;
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/* Define Bit Field */
#define BIT0 0x01
#define BIT1 0x02
#define BIT2 0x04
#define BIT3 0x08
#define BIT4 0x10
#define BIT5 0x20
#define BIT6 0x40
#define BIT7 0x80
/* Video Memory Size */
#define VIDEO_MEMORY_SIZE_16M 0x1000000
// Definition Mode Index
#define VIA_RES_640X480 0
#define VIA_RES_800X600 1
#define VIA_RES_1024X768 2
#define VIA_RES_1152X864 3
#define VIA_RES_1280X1024 4
#define VIA_RES_1600X1200 5
#define VIA_RES_1440X1050 6
#define VIA_RES_1280X768 7
#define VIA_RES_1280X960 8
#define VIA_RES_1920X1440 9
#define VIA_RES_848X480 10
#define VIA_RES_1400X1050 11
#define VIA_RES_720X480 12
#define VIA_RES_720X576 13
#define VIA_RES_1024X512 14
#define VIA_RES_856X480 15
#define VIA_RES_1024X576 16
#define VIA_RES_640X400 17
#define VIA_RES_1280X720 18
#define VIA_RES_1920X1080 19
#define VIA_RES_800X480 20
#define VIA_RES_1366X768 21
#define VIA_RES_INVALID 255
// standard VGA IO port
#define VIA_REGBASE 0x3C0
#define VIAAR 0x000
#define VIARMisc 0x00C
#define VIAWMisc 0x002
#define VIAStatus 0x01A
#define VIACR 0x014
#define VIASR 0x004
#define VIAGR 0x00E
#define StdCR 0x19
#define StdSR 0x04
#define StdGR 0x09
#define StdAR 0x14
#define PatchCR 11
/* Display path */
#define IGA1 1
#define IGA2 2
#define IGA1_IGA2 3
/* Define Color Depth */
#define MODE_8BPP 1
#define MODE_16BPP 2
#define MODE_32BPP 4
#define GR20 0x20
#define GR21 0x21
#define GR22 0x22
/* Sequencer Registers */
#define SR01 0x01
#define SR10 0x10
#define SR12 0x12
#define SR15 0x15
#define SR16 0x16
#define SR17 0x17
#define SR18 0x18
#define SR1B 0x1B
#define SR1A 0x1A
#define SR1C 0x1C
#define SR1D 0x1D
#define SR1E 0x1E
#define SR1F 0x1F
#define SR20 0x20
#define SR21 0x21
#define SR22 0x22
#define SR2A 0x2A
#define SR2D 0x2D
#define SR2E 0x2E
#define SR30 0x30
#define SR39 0x39
#define SR3D 0x3D
#define SR3E 0x3E
#define SR3F 0x3F
#define SR40 0x40
#define SR44 0x44
#define SR45 0x45
#define SR46 0x46
#define SR47 0x47
#define SR48 0x48
#define SR49 0x49
#define SR4A 0x4A
#define SR4B 0x4B
#define SR4C 0x4C
#define SR52 0x52
#define SR5E 0x5E
/* CRT Controller Registers */
#define CR00 0x00
#define CR01 0x01
#define CR02 0x02
#define CR03 0x03
#define CR04 0x04
#define CR05 0x05
#define CR06 0x06
#define CR07 0x07
#define CR08 0x08
#define CR09 0x09
#define CR0A 0x0A
#define CR0B 0x0B
#define CR0C 0x0C
#define CR0D 0x0D
#define CR0E 0x0E
#define CR0F 0x0F
#define CR10 0x10
#define CR11 0x11
#define CR12 0x12
#define CR13 0x13
#define CR14 0x14
#define CR15 0x15
#define CR16 0x16
#define CR17 0x17
#define CR18 0x18
/* Extend CRT Controller Registers */
#define CR30 0x30
#define CR31 0x31
#define CR32 0x32
#define CR33 0x33
#define CR34 0x34
#define CR35 0x35
#define CR36 0x36
#define CR37 0x37
#define CR38 0x38
#define CR39 0x39
#define CR3A 0x3A
#define CR3B 0x3B
#define CR3C 0x3C
#define CR3D 0x3D
#define CR3E 0x3E
#define CR3F 0x3F
#define CR40 0x40
#define CR41 0x41
#define CR42 0x42
#define CR43 0x43
#define CR44 0x44
#define CR45 0x45
#define CR46 0x46
#define CR47 0x47
#define CR48 0x48
#define CR49 0x49
#define CR4A 0x4A
#define CR4B 0x4B
#define CR4C 0x4C
#define CR4D 0x4D
#define CR4E 0x4E
#define CR4F 0x4F
#define CR50 0x50
#define CR51 0x51
#define CR52 0x52
#define CR53 0x53
#define CR54 0x54
#define CR55 0x55
#define CR56 0x56
#define CR57 0x57
#define CR58 0x58
#define CR59 0x59
#define CR5A 0x5A
#define CR5B 0x5B
#define CR5C 0x5C
#define CR5D 0x5D
#define CR5E 0x5E
#define CR5F 0x5F
#define CR60 0x60
#define CR61 0x61
#define CR62 0x62
#define CR63 0x63
#define CR64 0x64
#define CR65 0x65
#define CR66 0x66
#define CR67 0x67
#define CR68 0x68
#define CR69 0x69
#define CR6A 0x6A
#define CR6B 0x6B
#define CR6C 0x6C
#define CR6D 0x6D
#define CR6E 0x6E
#define CR6F 0x6F
#define CR70 0x70
#define CR71 0x71
#define CR72 0x72
#define CR73 0x73
#define CR74 0x74
#define CR75 0x75
#define CR76 0x76
#define CR77 0x77
#define CR78 0x78
#define CR79 0x79
#define CR7A 0x7A
#define CR7B 0x7B
#define CR7C 0x7C
#define CR7D 0x7D
#define CR7E 0x7E
#define CR7F 0x7F
#define CR80 0x80
#define CR81 0x81
#define CR82 0x82
#define CR83 0x83
#define CR84 0x84
#define CR85 0x85
#define CR86 0x86
#define CR87 0x87
#define CR88 0x88
#define CR89 0x89
#define CR8A 0x8A
#define CR8B 0x8B
#define CR8C 0x8C
#define CR8D 0x8D
#define CR8E 0x8E
#define CR8F 0x8F
#define CR90 0x90
#define CR91 0x91
#define CR92 0x92
#define CR93 0x93
#define CR94 0x94
#define CR95 0x95
#define CR96 0x96
#define CR97 0x97
#define CR98 0x98
#define CR99 0x99
#define CR9A 0x9A
#define CR9B 0x9B
#define CR9C 0x9C
#define CR9D 0x9D
#define CR9E 0x9E
#define CR9F 0x9F
#define CRA0 0xA0
#define CRA1 0xA1
#define CRA2 0xA2
#define CRA3 0xA3
#define CRD2 0xD2
#define CRD3 0xD3
#define CRD4 0xD4
/* LUT Table*/
#define LUT_DATA 0x09 /* DACDATA */
#define LUT_INDEX_READ 0x07 /* DACRX */
#define LUT_INDEX_WRITE 0x08 /* DACWX */
#define DACMASK 0x06
/* Definition Device */
#define DEVICE_CRT 0x01
#define DEVICE_TV 0x02
#define DEVICE_DVI 0x03
#define DEVICE_LCD 0x04
/* Device output interface */
#define INTERFACE_NONE 0x00
#define INTERFACE_ANALOG_RGB 0x01
#define INTERFACE_DVP0 0x02
#define INTERFACE_DVP1 0x03
#define INTERFACE_DFP_HIGH 0x04
#define INTERFACE_DFP_LOW 0x05
#define INTERFACE_DFP 0x06
#define INTERFACE_LVDS0 0x07
#define INTERFACE_LVDS1 0x08
#define INTERFACE_LVDS0LVDS1 0x09
#define INTERFACE_TMDS 0x0A
/* Definition Refresh Rate */
#define REFRESH_60 60
#define REFRESH_75 75
#define REFRESH_85 85
#define REFRESH_100 100
#define REFRESH_120 120
/* Definition Sync Polarity*/
#define NEGATIVE 1
#define POSITIVE 0
//640x480@60 Sync Polarity (VESA Mode)
#define M640X480_R60_HSP NEGATIVE
#define M640X480_R60_VSP NEGATIVE
//640x480@75 Sync Polarity (VESA Mode)
#define M640X480_R75_HSP NEGATIVE
#define M640X480_R75_VSP NEGATIVE
//640x480@85 Sync Polarity (VESA Mode)
#define M640X480_R85_HSP NEGATIVE
#define M640X480_R85_VSP NEGATIVE
//640x480@100 Sync Polarity (GTF Mode)
#define M640X480_R100_HSP NEGATIVE
#define M640X480_R100_VSP POSITIVE
//640x480@120 Sync Polarity (GTF Mode)
#define M640X480_R120_HSP NEGATIVE
#define M640X480_R120_VSP POSITIVE
//720x480@60 Sync Polarity (GTF Mode)
#define M720X480_R60_HSP NEGATIVE
#define M720X480_R60_VSP POSITIVE
//720x576@60 Sync Polarity (GTF Mode)
#define M720X576_R60_HSP NEGATIVE
#define M720X576_R60_VSP POSITIVE
//800x600@60 Sync Polarity (VESA Mode)
#define M800X600_R60_HSP POSITIVE
#define M800X600_R60_VSP POSITIVE
//800x600@75 Sync Polarity (VESA Mode)
#define M800X600_R75_HSP POSITIVE
#define M800X600_R75_VSP POSITIVE
//800x600@85 Sync Polarity (VESA Mode)
#define M800X600_R85_HSP POSITIVE
#define M800X600_R85_VSP POSITIVE
//800x600@100 Sync Polarity (GTF Mode)
#define M800X600_R100_HSP NEGATIVE
#define M800X600_R100_VSP POSITIVE
//800x600@120 Sync Polarity (GTF Mode)
#define M800X600_R120_HSP NEGATIVE
#define M800X600_R120_VSP POSITIVE
//800x480@60 Sync Polarity (GTF Mode)
#define M800X480_R60_HSP NEGATIVE
#define M800X480_R60_VSP POSITIVE
//848x480@60 Sync Polarity (GTF Mode)
#define M848X480_R60_HSP NEGATIVE
#define M848X480_R60_VSP POSITIVE
//852x480@60 Sync Polarity (GTF Mode)
#define M852X480_R60_HSP NEGATIVE
#define M852X480_R60_VSP POSITIVE
//1024x512@60 Sync Polarity (GTF Mode)
#define M1024X512_R60_HSP NEGATIVE
#define M1024X512_R60_VSP POSITIVE
//1024x768@60 Sync Polarity (VESA Mode)
#define M1024X768_R60_HSP NEGATIVE
#define M1024X768_R60_VSP NEGATIVE
//1024x768@75 Sync Polarity (VESA Mode)
#define M1024X768_R75_HSP POSITIVE
#define M1024X768_R75_VSP POSITIVE
//1024x768@85 Sync Polarity (VESA Mode)
#define M1024X768_R85_HSP POSITIVE
#define M1024X768_R85_VSP POSITIVE
//1024x768@100 Sync Polarity (GTF Mode)
#define M1024X768_R100_HSP NEGATIVE
#define M1024X768_R100_VSP POSITIVE
//1152x864@75 Sync Polarity (VESA Mode)
#define M1152X864_R75_HSP POSITIVE
#define M1152X864_R75_VSP POSITIVE
//1280x720@60 Sync Polarity (GTF Mode)
#define M1280X720_R60_HSP NEGATIVE
#define M1280X720_R60_VSP POSITIVE
//1280x768@60 Sync Polarity (GTF Mode)
#define M1280X768_R60_HSP NEGATIVE
#define M1280X768_R60_VSP POSITIVE
//1280x960@60 Sync Polarity (VESA Mode)
#define M1280X960_R60_HSP POSITIVE
#define M1280X960_R60_VSP POSITIVE
//1280x1024@60 Sync Polarity (VESA Mode)
#define M1280X1024_R60_HSP POSITIVE
#define M1280X1024_R60_VSP POSITIVE
/* 1368x768@60 Sync Polarity (VESA Mode) */
#define M1368X768_R60_HSP NEGATIVE
#define M1368X768_R60_VSP POSITIVE
//1280x1024@75 Sync Polarity (VESA Mode)
#define M1280X1024_R75_HSP POSITIVE
#define M1280X1024_R75_VSP POSITIVE
//1280x1024@85 Sync Polarity (VESA Mode)
#define M1280X1024_R85_HSP POSITIVE
#define M1280X1024_R85_VSP POSITIVE
//1440x1050@60 Sync Polarity (GTF Mode)
#define M1440X1050_R60_HSP NEGATIVE
#define M1440X1050_R60_VSP POSITIVE
//1600x1200@60 Sync Polarity (VESA Mode)
#define M1600X1200_R60_HSP POSITIVE
#define M1600X1200_R60_VSP POSITIVE
//1600x1200@75 Sync Polarity (VESA Mode)
#define M1600X1200_R75_HSP POSITIVE
#define M1600X1200_R75_VSP POSITIVE
//1920x1080@60 Sync Polarity (GTF Mode)
#define M1920X1080_R60_HSP NEGATIVE
#define M1920X1080_R60_VSP POSITIVE
//1920x1440@60 Sync Polarity (VESA Mode)
#define M1920X1440_R60_HSP NEGATIVE
#define M1920X1440_R60_VSP POSITIVE
//1920x1440@75 Sync Polarity (VESA Mode)
#define M1920X1440_R75_HSP NEGATIVE
#define M1920X1440_R75_VSP POSITIVE
/* 1400x1050@60 Sync Polarity (VESA Mode) */
#define M1400X1050_R60_HSP NEGATIVE
#define M1400X1050_R60_VSP NEGATIVE
/* define PLL index: */
#define CLK_25_175M 25175000
#define CLK_26_880M 26880000
#define CLK_29_581M 29581000
#define CLK_31_490M 31490000
#define CLK_31_500M 31500000
#define CLK_31_728M 31728000
#define CLK_32_668M 32688000
#define CLK_36_000M 36000000
#define CLK_40_000M 40000000
#define CLK_41_291M 41291000
#define CLK_43_163M 43163000
//#define CLK_46_996M 46996000
#define CLK_49_500M 49500000
#define CLK_52_406M 52406000
#define CLK_56_250M 56250000
#define CLK_65_000M 65000000
#define CLK_68_179M 68179000
#define CLK_78_750M 78750000
#define CLK_80_136M 80136000
#define CLK_83_950M 83950000
#define CLK_85_860M 85860000
#define CLK_94_500M 94500000
#define CLK_108_000M 108000000
#define CLK_125_104M 125104000
#define CLK_133_308M 133308000
#define CLK_135_000M 135000000
//#define CLK_148_500M 148500000
#define CLK_157_500M 157500000
#define CLK_162_000M 162000000
#define CLK_202_500M 202500000
#define CLK_234_000M 234000000
#define CLK_297_500M 297500000
#define CLK_74_481M 74481000
#define CLK_172_798M 172798000
// CLE266 PLL value
#define CLE266_PLL_25_175M 0x0000C763
#define CLE266_PLL_26_880M 0x0000440F
#define CLE266_PLL_29_581M 0x00008421
#define CLE266_PLL_31_490M 0x00004721
#define CLE266_PLL_31_500M 0x0000C3B5
#define CLE266_PLL_31_728M 0x0000471F
#define CLE266_PLL_32_668M 0x0000C449
#define CLE266_PLL_36_000M 0x0000C5E5
#define CLE266_PLL_40_000M 0x0000C459
#define CLE266_PLL_41_291M 0x00004417
#define CLE266_PLL_43_163M 0x0000C579
//#define CLE266_PLL_46_996M 0x0000C4E9
#define CLE266_PLL_49_500M 0x00008653
#define CLE266_PLL_52_406M 0x0000C475
#define CLE266_PLL_56_250M 0x000047B7
#define CLE266_PLL_65_000M 0x000086ED
#define CLE266_PLL_68_179M 0x00000413
#define CLE266_PLL_78_750M 0x00004321
#define CLE266_PLL_80_136M 0x0000051C
#define CLE266_PLL_83_950M 0x00000729
#define CLE266_PLL_85_860M 0x00004754
#define CLE266_PLL_94_500M 0x00000521
#define CLE266_PLL_108_000M 0x00008479
#define CLE266_PLL_125_104M 0x000006B5
#define CLE266_PLL_133_308M 0x0000465F
#define CLE266_PLL_135_000M 0x0000455E
//#define CLE266_PLL_148_500M 0x0000
#define CLE266_PLL_157_500M 0x000005B7
#define CLE266_PLL_162_000M 0x00004571
#define CLE266_PLL_202_500M 0x00000763
#define CLE266_PLL_234_000M 0x00000662
#define CLE266_PLL_297_500M 0x000005E6
#define CLE266_PLL_74_481M 0x0000051A
#define CLE266_PLL_172_798M 0x00004579
// K800 PLL value
#define K800_PLL_25_175M 0x00539001
#define K800_PLL_26_880M 0x001C8C80
#define K800_PLL_29_581M 0x00409080
#define K800_PLL_31_490M 0x006F9001
#define K800_PLL_31_500M 0x008B9002
#define K800_PLL_31_728M 0x00AF9003
#define K800_PLL_32_668M 0x00909002
#define K800_PLL_36_000M 0x009F9002
#define K800_PLL_40_000M 0x00578C02
#define K800_PLL_41_291M 0x00438C01
#define K800_PLL_43_163M 0x00778C03
//#define K800_PLL_46_996M 0x00000000
#define K800_PLL_49_500M 0x00518C01
#define K800_PLL_52_406M 0x00738C02
#define K800_PLL_56_250M 0x007C8C02
#define K800_PLL_65_000M 0x006B8C01
#define K800_PLL_68_179M 0x00708C01
#define K800_PLL_78_750M 0x00408801
#define K800_PLL_80_136M 0x00428801
#define K800_PLL_83_950M 0x00738803
#define K800_PLL_85_860M 0x00768883
#define K800_PLL_94_500M 0x00828803
#define K800_PLL_108_000M 0x00778882
#define K800_PLL_125_104M 0x00688801
#define K800_PLL_133_308M 0x005D8801
#define K800_PLL_135_000M 0x001A4081
//#define K800_PLL_148_500M 0x0000
#define K800_PLL_157_500M 0x00142080
#define K800_PLL_162_000M 0x006F8483
#define K800_PLL_202_500M 0x00538481
#define K800_PLL_234_000M 0x00608401
#define K800_PLL_297_500M 0x00A48402
#define K800_PLL_74_481M 0x007B8C81
#define K800_PLL_172_798M 0x00778483
/* PLL for VT3324 */
#define CX700_25_175M 0x008B1003
#define CX700_26_719M 0x00931003
#define CX700_26_880M 0x00941003
#define CX700_29_581M 0x00A49003
#define CX700_31_490M 0x00AE1003
#define CX700_31_500M 0x00AE1003
#define CX700_31_728M 0x00AF1003
#define CX700_32_668M 0x00B51003
#define CX700_36_000M 0x00C81003
#define CX700_40_000M 0x006E0C03
#define CX700_41_291M 0x00710C03
#define CX700_43_163M 0x00770C03
#define CX700_49_500M 0x00880C03
#define CX700_52_406M 0x00730C02
#define CX700_56_250M 0x009B0C03
#define CX700_65_000M 0x006B0C01
#define CX700_68_179M 0x00BC0C03
#define CX700_74_481M 0x00CE0C03
#define CX700_78_750M 0x006C0803
#define CX700_80_136M 0x006E0803
#define CX700_83_375M 0x005B0882
#define CX700_83_950M 0x00730803
#define CX700_85_860M 0x00760803
#define CX700_94_500M 0x00820803
#define CX700_108_000M 0x00950803
#define CX700_125_104M 0x00AD0803
#define CX700_133_308M 0x00930802
#define CX700_135_000M 0x00950802
#define CX700_157_500M 0x006C0403
#define CX700_162_000M 0x006F0403
#define CX700_172_798M 0x00770403
#define CX700_202_500M 0x008C0403
#define CX700_234_000M 0x00600401
#define CX700_297_500M 0x00CE0403
/* Definition CRTC Timing Index */
#define H_TOTAL_INDEX 0
#define H_ADDR_INDEX 1
#define H_BLANK_START_INDEX 2
#define H_BLANK_END_INDEX 3
#define H_SYNC_START_INDEX 4
#define H_SYNC_END_INDEX 5
#define V_TOTAL_INDEX 6
#define V_ADDR_INDEX 7
#define V_BLANK_START_INDEX 8
#define V_BLANK_END_INDEX 9
#define V_SYNC_START_INDEX 10
#define V_SYNC_END_INDEX 11
#define H_TOTAL_SHADOW_INDEX 12
#define H_BLANK_END_SHADOW_INDEX 13
#define V_TOTAL_SHADOW_INDEX 14
#define V_ADDR_SHADOW_INDEX 15
#define V_BLANK_SATRT_SHADOW_INDEX 16
#define V_BLANK_END_SHADOW_INDEX 17
#define V_SYNC_SATRT_SHADOW_INDEX 18
#define V_SYNC_END_SHADOW_INDEX 19
// Definition Video Mode Pixel Clock (picoseconds)
#define RES_640X480_60HZ_PIXCLOCK 39722
#define RES_640X480_75HZ_PIXCLOCK 31747
#define RES_640X480_85HZ_PIXCLOCK 27777
#define RES_640X480_100HZ_PIXCLOCK 23168
#define RES_640X480_120HZ_PIXCLOCK 19081
#define RES_720X480_60HZ_PIXCLOCK 37020
#define RES_720X576_60HZ_PIXCLOCK 30611
#define RES_800X600_60HZ_PIXCLOCK 25000
#define RES_800X600_75HZ_PIXCLOCK 20203
#define RES_800X600_85HZ_PIXCLOCK 17777
#define RES_800X600_100HZ_PIXCLOCK 14815
#define RES_800X600_120HZ_PIXCLOCK 11912
#define RES_800X480_60HZ_PIXCLOCK 33805
#define RES_848X480_60HZ_PIXCLOCK 31756
#define RES_856X480_60HZ_PIXCLOCK 31518
#define RES_1024X512_60HZ_PIXCLOCK 24218
#define RES_1024X768_60HZ_PIXCLOCK 15385
#define RES_1024X768_75HZ_PIXCLOCK 12699
#define RES_1024X768_85HZ_PIXCLOCK 10582
#define RES_1024X768_100HZ_PIXCLOCK 9091
#define RES_1152X864_70HZ_PIXCLOCK 10000
#define RES_1152X864_75HZ_PIXCLOCK 9091
#define RES_1280X768_60HZ_PIXCLOCK 12480
#define RES_1280X960_60HZ_PIXCLOCK 9259
#define RES_1280X1024_60HZ_PIXCLOCK 9260
#define RES_1280X1024_75HZ_PIXCLOCK 7408
#define RES_1280X768_85HZ_PIXCLOCK 6349
#define RES_1440X1050_60HZ_PIXCLOCK 7993
#define RES_1600X1200_60HZ_PIXCLOCK 6411
#define RES_1600X1200_75HZ_PIXCLOCK 4938
#define RES_1280X720_60HZ_PIXCLOCK 13426
#define RES_1920X1080_60HZ_PIXCLOCK 5787
#define RES_1400X1050_60HZ_PIXCLOCK 9260
#define RES_1366X768_60HZ_PIXCLOCK 11647
// LCD display method
#define LCD_EXPANDSION 0x00
#define LCD_CENTERING 0x01
// Define display timing
struct display_timing {
uint16_t hor_total;
uint16_t hor_addr;
uint16_t hor_blank_start;
uint16_t hor_blank_end;
uint16_t hor_sync_start;
uint16_t hor_sync_end;
uint16_t ver_total;
uint16_t ver_addr;
uint16_t ver_blank_start;
uint16_t ver_blank_end;
uint16_t ver_sync_start;
uint16_t ver_sync_end;
};
struct crt_mode_table {
int refresh_rate;
unsigned long clk;
int h_sync_polarity;
int v_sync_polarity;
struct display_timing crtc;
};
struct io_reg{
int port;
uint8_t index;
uint8_t mask;
uint8_t value;
};
#endif /* _DEV_PCI_UNICHROMEREG_H */