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Use all 64 address bits in ld*a()/st*a() macros so physical device addresses

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work.  (Also add some bus_space_*() debug hooks).
This commit is contained in:
eeh 2000-06-02 22:56:32 +00:00
parent 02cd59a751
commit 03228642f7
3 changed files with 475 additions and 155 deletions
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385
sys/arch/sparc64/include/bus.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus.h,v 1.15 2000/04/22 17:06:06 mrg Exp $ */ /* $NetBSD: bus.h,v 1.16 2000/06/02 22:56:33 eeh Exp $ */
/*- /*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -356,7 +356,7 @@ int bus_space_probe __P((
* Read a 1, 2, 4, or 8 byte quantity from bus space * Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset. * described by tag/handle/offset.
*/ */
#if 1 #ifndef BUS_SPACE_DEBUG
#define bus_space_read_1(t, h, o) \ #define bus_space_read_1(t, h, o) \
lduba((h) + (o), bus_type_asi[(t)->type]) lduba((h) + (o), bus_type_asi[(t)->type])
@ -369,18 +369,42 @@ int bus_space_probe __P((
#define bus_space_read_8(t, h, o) \ #define bus_space_read_8(t, h, o) \
ldxa((h) + (o), bus_type_asi[(t)->type]) ldxa((h) + (o), bus_type_asi[(t)->type])
#else #else
/* For the time being don't use address spaces */ extern int bus_space_debug;
#define bus_space_read_1(t, h, o) \ #define bus_space_read_1(t, h, o) ({ \
(*(volatile u_int8_t *)((h) + (o))) unsigned char __bv = \
lduba((h) + (o), bus_type_asi[(t)->type]); \
if (bus_space_debug) \
printf("bsr1(%llx + %llx, %x) -> %x\n", (u_int64_t)(h), \
(u_int64_t)(o), \
bus_type_asi[(t)->type], (unsigned int) __bv); \
__bv; })
#define bus_space_read_2(t, h, o) \ #define bus_space_read_2(t, h, o) ({ \
(*(volatile u_int16_t *)((h) + (o))) unsigned short __bv = \
lduha((h) + (o), bus_type_asi[(t)->type]); \
if (bus_space_debug) \
printf("bsr2(%llx + %llx, %x) -> %x\n", (u_int64_t)(h), \
(u_int64_t)(o), \
bus_type_asi[(t)->type], (unsigned int)__bv); \
__bv; })
#define bus_space_read_4(t, h, o) \ #define bus_space_read_4(t, h, o) ({ \
(*(volatile u_int32_t *)((h) + (o))) unsigned int __bv = \
lda((h) + (o), bus_type_asi[(t)->type]); \
if (bus_space_debug) \
printf("bsr4(%llx + %llx, %x) -> %x\n", (u_int64_t)(h), \
(u_int64_t)(h), \
bus_type_asi[(t)->type], __bv); \
__bv; })
#define bus_space_read_8(t, h, o) \ #define bus_space_read_8(t, h, o) ({ \
(*(volatile u_int64_t *)((h) + (o))) u_int64_t __bv = \
ldxa((h) + (o), bus_type_asi[(t)->type]); \
if (bus_space_debug) \
printf("bsr8(%llx + %llx, %x) -> %llx\n", (u_int64_t)(h), \
(u_int64_t) (o), \
bus_type_asi[(t)->type], __bv); \
__bv; })
#endif #endif
/* /*
* void bus_space_read_multi_N __P((bus_space_tag_t tag, * void bus_space_read_multi_N __P((bus_space_tag_t tag,
@ -427,7 +451,7 @@ int bus_space_probe __P((
* Write the 1, 2, 4, or 8 byte value `value' to bus space * Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset. * described by tag/handle/offset.
*/ */
#if 1 #ifndef BUS_SPACE_DEBUG
#define bus_space_write_1(t, h, o, v) \ #define bus_space_write_1(t, h, o, v) \
((void)(stba((h) + (o), bus_type_asi[(t)->type], (v)))) ((void)(stba((h) + (o), bus_type_asi[(t)->type], (v))))
@ -440,22 +464,33 @@ int bus_space_probe __P((
#define bus_space_write_8(t, h, o, v) \ #define bus_space_write_8(t, h, o, v) \
((void)(stxa((h) + (o), bus_type_asi[(t)->type], (v)))) ((void)(stxa((h) + (o), bus_type_asi[(t)->type], (v))))
#else #else
/* Use primary ASI for now for debug */ #define bus_space_write_1(t, h, o, v) ({ \
#define bus_space_write_1(t, h, o, v) do { \ if (bus_space_debug) \
((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); \ printf("bsw1(%llx + %llx, %x) <- %x\n", (u_int64_t)(h), \
} while (0) (u_int64_t)(o), \
bus_type_asi[(t)->type], (unsigned int) v); \
((void)(stba((h) + (o), bus_type_asi[(t)->type], (v)))); })
#define bus_space_write_2(t, h, o, v) do { \ #define bus_space_write_2(t, h, o, v) ({ \
((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); \ if (bus_space_debug) \
} while (0) printf("bsw2(%llx + %llx, %x) <- %x\n", (u_int64_t)(h), \
(u_int64_t)(o), \
bus_type_asi[(t)->type], (unsigned int) v); \
((void)(stha((h) + (o), bus_type_asi[(t)->type], (v)))); })
#define bus_space_write_4(t, h, o, v) do { \ #define bus_space_write_4(t, h, o, v) ({ \
((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); \ if (bus_space_debug) \
} while (0) printf("bsw4(%llx + %llx, %x) <- %x\n", (u_int64_t)(h), \
(u_int64_t)(o), \
bus_type_asi[(t)->type], (unsigned int) v); \
((void)(sta((h) + (o), bus_type_asi[(t)->type], (v)))); })
#define bus_space_write_8(t, h, o, v) do { \ #define bus_space_write_8(t, h, o, v) ({ \
((void)(*(volatile u_int64_t *)((h) + (o)) = (v))); \ if (bus_space_debug) \
} while (0) printf("bsw8(%llx + %llx, %x) <- %llx\n", (u_int64_t)(h), \
(u_int64_t)(o), \
bus_type_asi[(t)->type], (u_int64_t) v); \
((void)(stxa((h) + (o), bus_type_asi[(t)->type], (v)))); })
#endif #endif
/* /*
* void bus_space_write_multi_N __P((bus_space_tag_t tag, * void bus_space_write_multi_N __P((bus_space_tag_t tag,
@ -527,40 +562,296 @@ int bus_space_probe __P((
bus_space_write_8(t, h, o, v); \ bus_space_write_8(t, h, o, v); \
} while (0) } while (0)
/*
* void bus_space_read_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t off,
* u_intN_t *addr, bus_size_t count));
*
*/
void bus_space_read_region_1 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
u_int8_t *,
bus_size_t));
void bus_space_read_region_2 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
u_int16_t *,
bus_size_t));
void bus_space_read_region_4 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
u_int32_t *,
bus_size_t));
void bus_space_read_region_8 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
u_int64_t *,
bus_size_t));
extern __inline__ void
bus_space_read_region_1(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
u_int8_t *a;
{
for (; c; a++, c--, o++)
*a = bus_space_read_1(t, h, o);
}
extern __inline__ void
bus_space_read_region_2(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
u_int16_t *a;
{
for (; c; a++, c--, o+=2)
*a = bus_space_read_1(t, h, o);
}
extern __inline__ void
bus_space_read_region_4(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
u_int32_t *a;
{
for (; c; a++, c--, o+=4)
*a = bus_space_read_1(t, h, o);
}
extern __inline__ void
bus_space_read_region_8(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
u_int64_t *a;
{
for (; c; a++, c--, o+=8)
*a = bus_space_read_1(t, h, o);
}
/* /*
* void bus_space_copy_N __P((bus_space_tag_t tag, * void bus_space_write_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t off,
* u_intN_t *addr, bus_size_t count));
*
*/
void bus_space_write_region_1 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int8_t *,
bus_size_t));
void bus_space_write_region_2 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int16_t *,
bus_size_t));
void bus_space_write_region_4 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int32_t *,
bus_size_t));
void bus_space_write_region_8 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int64_t *,
bus_size_t));
extern __inline__ void
bus_space_write_region_1(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int8_t *a;
{
for (; c; a++, c--, o++)
bus_space_write_1(t, h, o, *a);
}
extern __inline__ void
bus_space_write_region_2(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int16_t *a;
{
for (; c; a++, c--, o+=2)
bus_space_write_2(t, h, o, *a);
}
extern __inline__ void
bus_space_write_region_4(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int32_t *a;
{
for (; c; a++, c--, o+=4)
bus_space_write_4(t, h, o, *a);
}
extern __inline__ void
bus_space_write_region_8(t, h, o, a, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int64_t *a;
{
for (; c; a++, c--, o+=8)
bus_space_write_8(t, h, o, *a);
}
/*
* void bus_space_set_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t off,
* u_intN_t *addr, bus_size_t count));
*
*/
void bus_space_set_region_1 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int8_t,
bus_size_t));
void bus_space_set_region_2 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int16_t,
bus_size_t));
void bus_space_set_region_4 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int32_t,
bus_size_t));
void bus_space_set_region_8 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
const u_int64_t,
bus_size_t));
extern __inline__ void
bus_space_set_region_1(t, h, o, v, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int8_t v;
{
for (; c; c--, o++)
bus_space_write_1(t, h, o, v);
}
extern __inline__ void
bus_space_set_region_2(t, h, o, v, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int16_t v;
{
for (; c; c--, o+=2)
bus_space_write_2(t, h, o, v);
}
extern __inline__ void
bus_space_set_region_4(t, h, o, v, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int32_t v;
{
for (; c; c--, o+=4)
bus_space_write_4(t, h, o, v);
}
extern __inline__ void
bus_space_set_region_8(t, h, o, v, c)
bus_space_tag_t t;
bus_space_handle_t h;
bus_size_t o, c;
const u_int64_t v;
{
for (; c; c--, o+=8)
bus_space_write_8(t, h, o, v);
}
/*
* void bus_space_copy_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh1, bus_size_t off1, * bus_space_handle_t bsh1, bus_size_t off1,
* bus_space_handle_t bsh2, bus_size_t off2, * bus_space_handle_t bsh2, bus_size_t off2,
* size_t count)); * bus_size_t count));
* *
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/ */
void bus_space_copy_region_1 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
bus_space_handle_t,
bus_size_t,
bus_size_t));
void bus_space_copy_region_2 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
bus_space_handle_t,
bus_size_t,
bus_size_t));
void bus_space_copy_region_4 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
bus_space_handle_t,
bus_size_t,
bus_size_t));
void bus_space_copy_region_8 __P((bus_space_tag_t,
bus_space_handle_t,
bus_size_t,
bus_space_handle_t,
bus_size_t,
bus_size_t));
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
{ int i = c; \
for (; i; i--, o1++, o2++) \
bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2)); \
} while (0)
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ extern __inline__ void
{ int i = c; \ bus_space_copy_region_1(t, h1, o1, h2, o2, c)
for (; i; i--, o1 += 2, o2 += 2) \ bus_space_tag_t t;
bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2)); \ bus_space_handle_t h1, h2;
} while (0) bus_size_t o1, o2;
bus_size_t c;
{
for (; c; c--, o1++, o2++)
bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2));
}
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ extern __inline__ void
{ int i = c; \ bus_space_copy_region_2(t, h1, o1, h2, o2, c)
for (; i; i--, o1 += 4, o2 += 4) \ bus_space_tag_t t;
bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2)); \ bus_space_handle_t h1, h2;
} while (0) bus_size_t o1, o2;
bus_size_t c;
{
for (; c; c--, o1+=2, o2+=2)
bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2));
}
extern __inline__ void
bus_space_copy_region_4(t, h1, o1, h2, o2, c)
bus_space_tag_t t;
bus_space_handle_t h1, h2;
bus_size_t o1, o2;
bus_size_t c;
{
for (; c; c--, o1+=4, o2+=4)
bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2));
}
extern __inline__ void
bus_space_copy_region_8(t, h1, o1, h2, o2, c)
bus_space_tag_t t;
bus_space_handle_t h1, h2;
bus_size_t o1, o2;
bus_size_t c;
{
for (; c; c--, o1+=8, o2+=8)
bus_space_write_8(t, h1, o1, bus_space_read_8(t, h2, o2));
}
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
{ int i = c; \
for (; i; i--, o1 += 8, o2 += 8) \
bus_space_write_8(t, h1, o1, bus_space_read_4(t, h2, o2)); \
} while (0)
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)

188
sys/arch/sparc64/include/ctlreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ctlreg.h,v 1.13 2000/04/10 16:05:13 mrg Exp $ */ /* $NetBSD: ctlreg.h,v 1.14 2000/06/02 22:56:33 eeh Exp $ */
/* /*
* Copyright (c) 1996-1999 Eduardo Horvath * Copyright (c) 1996-1999 Eduardo Horvath
@ -164,6 +164,9 @@
#define ASI_BLK_S ASI_BLOCK_SECONDARY #define ASI_BLK_S ASI_BLOCK_SECONDARY
#define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE
#define PHYS_ASI(x) (((x) | 0x09) == 0x1d)
#define LITTLE_ASI(x) ((x) & ASI_LITTLE)
/* /*
* The following are 4u control registers * The following are 4u control registers
*/ */
@ -432,7 +435,7 @@
#ifdef DCACHE_BUG #ifdef DCACHE_BUG
#define lduba(loc, asi) ({ \ #define lduba(loc, asi) ({ \
register int _lduba_v; \ register int _lduba_v; \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %2,%%g0,%%asi; " \ __asm __volatile("wr %2,%%g0,%%asi; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
" lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \ " lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \
@ -455,27 +458,32 @@
/* load byte from alternate address space */ /* load byte from alternate address space */
#ifdef DCACHE_BUG #ifdef DCACHE_BUG
#define lduba(loc, asi) ({ \ #define lduba(loc, asi) ({ \
register int _lduba_v, _loc_hi; \ register int _lduba_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %3,%%g0,%%asi; " \ __asm __volatile("wr %4,%%g0,%%asi; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ " andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " \
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ " sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " \
" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lduba_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), \ "r" ((long)(loc)), "r" (_loc_hi), \
"r" (asi), "n" (ASI_DCACHE_TAG)); \ "r" (asi), "n" (ASI_DCACHE_TAG)); \
} else { \ } else { \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ " rdpr %%pstate,%1; wrpr %1,8,%%pstate; " \
" or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lduba_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
} \ } \
_lduba_v; \ _lduba_v; \
}) })
#else #else
#define lduba(loc, asi) ({ \ #define lduba(loc, asi) ({ \
register int _lduba_v, _loc_hi; \ register int _lduba_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; sllx %3,32,%0; " \
" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ " wrpr %1,8,%%pstate; or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lduba_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
_lduba_v; \ _lduba_v; \
}) })
@ -487,7 +495,7 @@
#ifdef DCACHE_BUG #ifdef DCACHE_BUG
#define lduha(loc, asi) ({ \ #define lduha(loc, asi) ({ \
register int _lduha_v; \ register int _lduha_v; \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %2,%%g0,%%asi; " \ __asm __volatile("wr %2,%%g0,%%asi; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
" lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \ " lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \
@ -510,17 +518,20 @@
/* load half-word from alternate address space */ /* load half-word from alternate address space */
#ifdef DCACHE_BUG #ifdef DCACHE_BUG
#define lduha(loc, asi) ({ \ #define lduha(loc, asi) ({ \
register int _lduha_v, _loc_hi; \ register int _lduha_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %3,%%g0,%%asi; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " \
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lduha_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), \ "r" ((long)(loc)), "r" (_loc_hi), \
"r" (asi), "n" (ASI_DCACHE_TAG)); \ "r" (asi), "n" (ASI_DCACHE_TAG)); \
} else { \ } else { \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \
" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ " sllx %3,32,%0; wrpr %1,8,%%pstate; " \
" or %0,%2,%0; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lduha_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
} \ } \
_lduha_v; \ _lduha_v; \
@ -529,8 +540,9 @@
#define lduha(loc, asi) ({ \ #define lduha(loc, asi) ({ \
register int _lduha_v, _loc_hi; \ register int _lduha_v, _loc_hi; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1; " \
" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ " or %0,%2,%0; wrpr %1,8,%%pstate; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lduha_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
_lduha_v; \ _lduha_v; \
}) })
@ -542,7 +554,7 @@
#ifdef DCACHE_BUG #ifdef DCACHE_BUG
#define lda(loc, asi) ({ \ #define lda(loc, asi) ({ \
register int _lda_v; \ register int _lda_v; \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %2,%%g0,%%asi; " \ __asm __volatile("wr %2,%%g0,%%asi; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
" lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ " lda [%1]%%asi,%0" : "=&r" (_lda_v) : \
@ -557,7 +569,7 @@
/* load signed int from alternate address space */ /* load signed int from alternate address space */
#define ldswa(loc, asi) ({ \ #define ldswa(loc, asi) ({ \
register int _lda_v; \ register int _lda_v; \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %2,%%g0,%%asi; " \ __asm __volatile("wr %2,%%g0,%%asi; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
" ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ " ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \
@ -587,17 +599,20 @@
/* load unsigned int from alternate address space */ /* load unsigned int from alternate address space */
#ifdef DCACHE_BUG #ifdef DCACHE_BUG
#define lda(loc, asi) ({ \ #define lda(loc, asi) ({ \
register int _lda_v, _loc_hi; \ register int _lda_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %3,%%g0,%%asi; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " \
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ " sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " \
" wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), \ "r" ((long)(loc)), "r" (_loc_hi), \
"r" (asi), "n" (ASI_DCACHE_TAG)); \ "r" (asi), "n" (ASI_DCACHE_TAG)); \
} else { \ } else { \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ " sllx %3,32,%0; wrpr %1,8,%%pstate;" \
" or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
} \ } \
_lda_v; \ _lda_v; \
@ -605,36 +620,41 @@
/* load signed int from alternate address space */ /* load signed int from alternate address space */
#define ldswa(loc, asi) ({ \ #define ldswa(loc, asi) ({ \
register int _lda_v, _loc_hi; \ register int _lda_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %3,%%g0,%%asi; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" \
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), \ "r" ((long)(loc)), "r" (_loc_hi), \
"r" (asi), "n" (ASI_DCACHE_TAG)); \ "r" (asi), "n" (ASI_DCACHE_TAG)); \
} else { \ } else { \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0;" \
" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ " rdpr %%pstate,%1; wrpr %1,8,%%pstate;" \
" or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
} \ } \
_lda_v; \ _lda_v; \
}) })
#else #else
#define lda(loc, asi) ({ \ #define lda(loc, asi) ({ \
register int _lda_v, _loc_hi; \ register int _lda_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \
" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ " wrpr %1,8,%%pstate; or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%pstate" : \
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
_lda_v; \ _lda_v; \
}) })
#define ldswa(loc, asi) ({ \ #define ldswa(loc, asi) ({ \
register int _lda_v, _loc_hi; \ register int _lda_v, _loc_hi, _pstate;; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \
" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ " wrpr %1,8,%%pstate; or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
_lda_v; \ _lda_v; \
}) })
@ -647,7 +667,7 @@
/* load 64-bit int from alternate address space */ /* load 64-bit int from alternate address space */
#define ldda(loc, asi) ({ \ #define ldda(loc, asi) ({ \
register long long _lda_v; \ register long long _lda_v; \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %2,%%g0,%%asi; " \ __asm __volatile("wr %2,%%g0,%%asi; " \
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
" ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \ " ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \
@ -661,16 +681,18 @@
#else #else
/* load 64-bit int from alternate address space */ /* load 64-bit int from alternate address space */
#define ldda(loc, asi) ({ \ #define ldda(loc, asi) ({ \
register long long _lda_v, _loc_hi; \ register long long _lda_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %3,%%g0,%%asi; " \ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" \
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" :\
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \
} else { \ } else { \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ " rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0;" \
" wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
} \ } \
_lda_v; \ _lda_v; \
@ -681,7 +703,7 @@
/* native load 64-bit int from alternate address space w/64-bit compiler*/ /* native load 64-bit int from alternate address space w/64-bit compiler*/
#define ldxa(loc, asi) ({ \ #define ldxa(loc, asi) ({ \
register long _lda_v; \ register long _lda_v; \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %2,%%g0,%%asi; "\ __asm __volatile("wr %2,%%g0,%%asi; "\
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
" ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \ " ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \
@ -697,17 +719,18 @@
#define ldxa(loc, asi) ({ \ #define ldxa(loc, asi) ({ \
register long _ldxa_lo, _ldxa_hi, _loc_hi; \ register long _ldxa_lo, _ldxa_hi, _loc_hi; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
if (asi == ASI_PHYS_CACHED) { \ if (PHYS_ASI(asi)) { \
__asm __volatile("wr %4,%%g0,%%asi; " \ __asm __volatile("wr %4,%%g0,%%asi; " \
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; " \ " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " \
" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \ " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \
" srlx %0,32,%1; srl %0,0,%0" : \ " wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0" : \
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
"r" ((long)(loc)), "r" (_loc_hi), \ "r" ((long)(loc)), "r" (_loc_hi), \
"r" (asi), "n" (ASI_DCACHE_TAG)); \ "r" (asi), "n" (ASI_DCACHE_TAG)); \
} else { \ } else { \
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ " rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; " \
" wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0;" : \
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
} \ } \
@ -727,10 +750,11 @@
}) })
#else #else
#define ldda(loc, asi) ({ \ #define ldda(loc, asi) ({ \
register long long _lda_v, _loc_hi; \ register long long _lda_v, _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1" \
" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ " or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
"=&r" (_lda_v), "=&r" (_pstate) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
_lda_v; \ _lda_v; \
}) })
@ -749,8 +773,9 @@
#define ldxa(loc, asi) ({ \ #define ldxa(loc, asi) ({ \
register long _ldxa_lo, _ldxa_hi, _loc_hi; \ register long _ldxa_lo, _ldxa_hi, _loc_hi; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \ __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1" \
" or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ " or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \
" srlx %0,32,%1; srl %0,0,%0;" : \
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
@ -767,10 +792,11 @@
}) })
#else #else
#define stba(loc, asi, value) ({ \ #define stba(loc, asi, value) ({ \
register int _loc_hi; \ register int _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
" or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \ " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
"=&r" (_loc_hi), "=&r" (_pstate) : \
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
}) })
#endif #endif
@ -783,10 +809,11 @@
}) })
#else #else
#define stha(loc, asi, value) ({ \ #define stha(loc, asi, value) ({ \
register int _loc_hi; \ register int _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
" or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \ " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
"=&r" (_loc_hi), "=&r" (_pstate) : \
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
}) })
#endif #endif
@ -799,10 +826,11 @@ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
}) })
#else #else
#define sta(loc, asi, value) ({ \ #define sta(loc, asi, value) ({ \
register int _loc_hi; \ register int _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
" or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \ " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
"=&r" (_loc_hi), "=&r" (_pstate) : \
"r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
}) })
#endif #endif
@ -815,10 +843,11 @@ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
}) })
#else #else
#define stda(loc, asi, value) ({ \ #define stda(loc, asi, value) ({ \
register int _loc_hi; \ register int _loc_hi, _pstate; \
_loc_hi = (((u_int64_t)loc)>>32); \ _loc_hi = (((u_int64_t)loc)>>32); \
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \
" or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \ " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
"=&r" (_loc_hi), "=&r" (_pstate) : \
"r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
}) })
#endif #endif
@ -834,10 +863,11 @@ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
#define stxa(loc, asi, value) ({ \ #define stxa(loc, asi, value) ({ \
int _stxa_lo, _stxa_hi, _loc_hi; \ int _stxa_lo, _stxa_hi, _loc_hi; \
_stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \
_loc_hi = (((u_int64_t)(long)loc)>>32); \ _loc_hi = (((u_int64_t)(u_long)loc)>>32); \
__asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \ __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \
" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \ " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \
"=&r" (_loc_hi), "=&r" (_stxa_hi) : \ " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \
"=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \
"r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
"r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
}) })

37
sys/arch/sparc64/sparc64/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.62 2000/05/26 21:20:21 thorpej Exp $ */ /* $NetBSD: machdep.c,v 1.63 2000/06/02 22:56:32 eeh Exp $ */
/*- /*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@ -131,6 +131,7 @@
/* Our exported CPU info; we have only one for now. */ /* Our exported CPU info; we have only one for now. */
struct cpu_info cpu_info_store; struct cpu_info cpu_info_store;
int bus_space_debug = 0;
vm_map_t exec_map = NULL; vm_map_t exec_map = NULL;
vm_map_t mb_map = NULL; vm_map_t mb_map = NULL;
@ -1219,26 +1220,20 @@ _bus_dmamap_sync(t, map, offset, len, ops)
* *
* Actually a #Sync is expensive. We should optimize. * Actually a #Sync is expensive. We should optimize.
*/ */
switch (ops) { if ((ops & BUS_DMASYNC_PREREAD) || (ops & BUS_DMASYNC_PREWRITE)) {
case BUS_DMASYNC_PREREAD: /*
/* Flush any pending writes */ * Don't really need to do anything, but flush any pending
* writes anyway.
*/
__asm("membar #Sync" : ); __asm("membar #Sync" : );
break; }
case BUS_DMASYNC_POSTREAD: if (ops & BUS_DMASYNC_POSTREAD) {
/* Invalidate the vcache */ /* Invalidate the vcache */
blast_vcache(); blast_vcache();
/* Maybe we should flush the I$? */ /* Maybe we should flush the I$? When we support LKMs.... */
break; }
case BUS_DMASYNC_PREWRITE: if (ops & BUS_DMASYNC_POSTWRITE) {
/* Flush any pending writes */ /* Nothing to do. Handled by the bus controller. */
__asm("membar #Sync" : );
break;
case BUS_DMASYNC_POSTWRITE:
/* Nothing to do */
break;
default:
__asm("membar #Sync" : );
printf("_bus_dmamap_sync: unknown sync op\n");
} }
} }
@ -1502,6 +1497,7 @@ static vaddr_t iobase = IODEV_BASE;
* out of IO mappings, config space will not be mapped in, * out of IO mappings, config space will not be mapped in,
* rather it will be accessed through MMU bypass ASI accesses. * rather it will be accessed through MMU bypass ASI accesses.
*/ */
if (flags & BUS_SPACE_MAP_LINEAR) return (-1);
*hp = (bus_space_handle_t)addr; *hp = (bus_space_handle_t)addr;
if (!vaddr) return (0); if (!vaddr) return (0);
/* FALLTHROUGH */ /* FALLTHROUGH */
@ -1516,6 +1512,8 @@ static vaddr_t iobase = IODEV_BASE;
break; break;
} }
if (!(flags & BUS_SPACE_MAP_CACHEABLE)) pm_flags |= PMAP_NC;
if (vaddr) if (vaddr)
v = trunc_page(vaddr); v = trunc_page(vaddr);
else { else {
@ -1537,7 +1535,8 @@ static vaddr_t iobase = IODEV_BASE;
do { do {
#ifdef NOTDEF_DEBUG #ifdef NOTDEF_DEBUG
printf("sparc_bus_map: phys %llx virt %p hp %llx\n", (u_int64_t)pa, (char *)v, (u_int64_t)*hp); printf("sparc_bus_map: phys %llx virt %p hp %llx\n",
(u_int64_t)pa, (char *)v, (u_int64_t)*hp);
#endif #endif
pmap_enter(pmap_kernel(), v, pa | pm_flags, pmap_enter(pmap_kernel(), v, pa | pm_flags,
(flags&BUS_SPACE_MAP_READONLY) ? VM_PROT_READ (flags&BUS_SPACE_MAP_READONLY) ? VM_PROT_READ