Use all 64 address bits in ld*a()/st*a() macros so physical device addresses
work. (Also add some bus_space_*() debug hooks).
This commit is contained in:
eeh
parent
02cd59a751
commit
03228642f7
@ -1,4 +1,4 @@
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/* $NetBSD: bus.h,v 1.15 2000/04/22 17:06:06 mrg Exp $ */
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/* $NetBSD: bus.h,v 1.16 2000/06/02 22:56:33 eeh Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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@ -356,7 +356,7 @@ int bus_space_probe __P((
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* Read a 1, 2, 4, or 8 byte quantity from bus space
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* described by tag/handle/offset.
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*/
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#if 1
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#ifndef BUS_SPACE_DEBUG
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#define bus_space_read_1(t, h, o) \
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lduba((h) + (o), bus_type_asi[(t)->type])
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@ -369,18 +369,42 @@ int bus_space_probe __P((
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#define bus_space_read_8(t, h, o) \
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ldxa((h) + (o), bus_type_asi[(t)->type])
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#else
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/* For the time being don't use address spaces */
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#define bus_space_read_1(t, h, o) \
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(*(volatile u_int8_t *)((h) + (o)))
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extern int bus_space_debug;
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#define bus_space_read_1(t, h, o) ({ \
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unsigned char __bv = \
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lduba((h) + (o), bus_type_asi[(t)->type]); \
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if (bus_space_debug) \
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printf("bsr1(%llx + %llx, %x) -> %x\n", (u_int64_t)(h), \
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(u_int64_t)(o), \
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bus_type_asi[(t)->type], (unsigned int) __bv); \
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__bv; })
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#define bus_space_read_2(t, h, o) \
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(*(volatile u_int16_t *)((h) + (o)))
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#define bus_space_read_2(t, h, o) ({ \
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unsigned short __bv = \
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lduha((h) + (o), bus_type_asi[(t)->type]); \
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if (bus_space_debug) \
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printf("bsr2(%llx + %llx, %x) -> %x\n", (u_int64_t)(h), \
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(u_int64_t)(o), \
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bus_type_asi[(t)->type], (unsigned int)__bv); \
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__bv; })
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#define bus_space_read_4(t, h, o) \
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(*(volatile u_int32_t *)((h) + (o)))
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#define bus_space_read_4(t, h, o) ({ \
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unsigned int __bv = \
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lda((h) + (o), bus_type_asi[(t)->type]); \
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if (bus_space_debug) \
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printf("bsr4(%llx + %llx, %x) -> %x\n", (u_int64_t)(h), \
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(u_int64_t)(h), \
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bus_type_asi[(t)->type], __bv); \
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__bv; })
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#define bus_space_read_8(t, h, o) \
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(*(volatile u_int64_t *)((h) + (o)))
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#define bus_space_read_8(t, h, o) ({ \
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u_int64_t __bv = \
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ldxa((h) + (o), bus_type_asi[(t)->type]); \
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if (bus_space_debug) \
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printf("bsr8(%llx + %llx, %x) -> %llx\n", (u_int64_t)(h), \
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(u_int64_t) (o), \
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bus_type_asi[(t)->type], __bv); \
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__bv; })
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#endif
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/*
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* void bus_space_read_multi_N __P((bus_space_tag_t tag,
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@ -427,7 +451,7 @@ int bus_space_probe __P((
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* Write the 1, 2, 4, or 8 byte value `value' to bus space
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* described by tag/handle/offset.
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*/
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#if 1
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#ifndef BUS_SPACE_DEBUG
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#define bus_space_write_1(t, h, o, v) \
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((void)(stba((h) + (o), bus_type_asi[(t)->type], (v))))
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@ -440,22 +464,33 @@ int bus_space_probe __P((
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#define bus_space_write_8(t, h, o, v) \
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((void)(stxa((h) + (o), bus_type_asi[(t)->type], (v))))
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#else
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/* Use primary ASI for now for debug */
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#define bus_space_write_1(t, h, o, v) do { \
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((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); \
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} while (0)
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#define bus_space_write_1(t, h, o, v) ({ \
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if (bus_space_debug) \
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printf("bsw1(%llx + %llx, %x) <- %x\n", (u_int64_t)(h), \
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(u_int64_t)(o), \
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bus_type_asi[(t)->type], (unsigned int) v); \
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((void)(stba((h) + (o), bus_type_asi[(t)->type], (v)))); })
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#define bus_space_write_2(t, h, o, v) do { \
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((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); \
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} while (0)
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#define bus_space_write_2(t, h, o, v) ({ \
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if (bus_space_debug) \
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printf("bsw2(%llx + %llx, %x) <- %x\n", (u_int64_t)(h), \
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(u_int64_t)(o), \
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bus_type_asi[(t)->type], (unsigned int) v); \
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((void)(stha((h) + (o), bus_type_asi[(t)->type], (v)))); })
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#define bus_space_write_4(t, h, o, v) do { \
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((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); \
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} while (0)
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#define bus_space_write_4(t, h, o, v) ({ \
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if (bus_space_debug) \
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printf("bsw4(%llx + %llx, %x) <- %x\n", (u_int64_t)(h), \
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(u_int64_t)(o), \
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bus_type_asi[(t)->type], (unsigned int) v); \
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((void)(sta((h) + (o), bus_type_asi[(t)->type], (v)))); })
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#define bus_space_write_8(t, h, o, v) do { \
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((void)(*(volatile u_int64_t *)((h) + (o)) = (v))); \
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} while (0)
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#define bus_space_write_8(t, h, o, v) ({ \
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if (bus_space_debug) \
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printf("bsw8(%llx + %llx, %x) <- %llx\n", (u_int64_t)(h), \
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(u_int64_t)(o), \
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bus_type_asi[(t)->type], (u_int64_t) v); \
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((void)(stxa((h) + (o), bus_type_asi[(t)->type], (v)))); })
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#endif
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/*
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* void bus_space_write_multi_N __P((bus_space_tag_t tag,
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@ -527,40 +562,296 @@ int bus_space_probe __P((
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bus_space_write_8(t, h, o, v); \
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} while (0)
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/*
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* void bus_space_read_region_N __P((bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t off,
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* u_intN_t *addr, bus_size_t count));
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*
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*/
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void bus_space_read_region_1 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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u_int8_t *,
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bus_size_t));
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void bus_space_read_region_2 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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u_int16_t *,
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bus_size_t));
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void bus_space_read_region_4 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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u_int32_t *,
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bus_size_t));
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void bus_space_read_region_8 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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u_int64_t *,
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bus_size_t));
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extern __inline__ void
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bus_space_read_region_1(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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u_int8_t *a;
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{
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for (; c; a++, c--, o++)
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*a = bus_space_read_1(t, h, o);
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}
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extern __inline__ void
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bus_space_read_region_2(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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u_int16_t *a;
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{
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for (; c; a++, c--, o+=2)
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*a = bus_space_read_1(t, h, o);
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}
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extern __inline__ void
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bus_space_read_region_4(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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u_int32_t *a;
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{
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for (; c; a++, c--, o+=4)
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*a = bus_space_read_1(t, h, o);
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}
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extern __inline__ void
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bus_space_read_region_8(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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u_int64_t *a;
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{
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for (; c; a++, c--, o+=8)
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*a = bus_space_read_1(t, h, o);
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}
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/*
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* void bus_space_copy_N __P((bus_space_tag_t tag,
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* void bus_space_write_region_N __P((bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t off,
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* u_intN_t *addr, bus_size_t count));
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*
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*/
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void bus_space_write_region_1 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int8_t *,
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bus_size_t));
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void bus_space_write_region_2 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int16_t *,
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bus_size_t));
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void bus_space_write_region_4 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int32_t *,
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bus_size_t));
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void bus_space_write_region_8 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int64_t *,
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bus_size_t));
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extern __inline__ void
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bus_space_write_region_1(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int8_t *a;
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{
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for (; c; a++, c--, o++)
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bus_space_write_1(t, h, o, *a);
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}
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extern __inline__ void
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bus_space_write_region_2(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int16_t *a;
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{
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for (; c; a++, c--, o+=2)
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bus_space_write_2(t, h, o, *a);
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}
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extern __inline__ void
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bus_space_write_region_4(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int32_t *a;
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{
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for (; c; a++, c--, o+=4)
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bus_space_write_4(t, h, o, *a);
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}
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extern __inline__ void
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bus_space_write_region_8(t, h, o, a, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int64_t *a;
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{
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for (; c; a++, c--, o+=8)
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bus_space_write_8(t, h, o, *a);
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}
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/*
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* void bus_space_set_region_N __P((bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t off,
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* u_intN_t *addr, bus_size_t count));
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*
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*/
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void bus_space_set_region_1 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int8_t,
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bus_size_t));
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void bus_space_set_region_2 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int16_t,
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bus_size_t));
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void bus_space_set_region_4 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int32_t,
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bus_size_t));
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void bus_space_set_region_8 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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const u_int64_t,
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bus_size_t));
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extern __inline__ void
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bus_space_set_region_1(t, h, o, v, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int8_t v;
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{
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for (; c; c--, o++)
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bus_space_write_1(t, h, o, v);
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}
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extern __inline__ void
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bus_space_set_region_2(t, h, o, v, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int16_t v;
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{
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for (; c; c--, o+=2)
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bus_space_write_2(t, h, o, v);
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}
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extern __inline__ void
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bus_space_set_region_4(t, h, o, v, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int32_t v;
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{
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for (; c; c--, o+=4)
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bus_space_write_4(t, h, o, v);
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}
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extern __inline__ void
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bus_space_set_region_8(t, h, o, v, c)
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bus_space_tag_t t;
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bus_space_handle_t h;
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bus_size_t o, c;
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const u_int64_t v;
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{
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for (; c; c--, o+=8)
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bus_space_write_8(t, h, o, v);
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}
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/*
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* void bus_space_copy_region_N __P((bus_space_tag_t tag,
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* bus_space_handle_t bsh1, bus_size_t off1,
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* bus_space_handle_t bsh2, bus_size_t off2,
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* size_t count));
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* bus_size_t count));
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*
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* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
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* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
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*/
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void bus_space_copy_region_1 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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bus_space_handle_t,
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bus_size_t,
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bus_size_t));
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void bus_space_copy_region_2 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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bus_space_handle_t,
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bus_size_t,
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bus_size_t));
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void bus_space_copy_region_4 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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bus_space_handle_t,
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bus_size_t,
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bus_size_t));
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void bus_space_copy_region_8 __P((bus_space_tag_t,
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bus_space_handle_t,
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bus_size_t,
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bus_space_handle_t,
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bus_size_t,
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bus_size_t));
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#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
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{ int i = c; \
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for (; i; i--, o1++, o2++) \
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bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2)); \
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} while (0)
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#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
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{ int i = c; \
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for (; i; i--, o1 += 2, o2 += 2) \
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bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2)); \
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} while (0)
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extern __inline__ void
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bus_space_copy_region_1(t, h1, o1, h2, o2, c)
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bus_space_tag_t t;
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bus_space_handle_t h1, h2;
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bus_size_t o1, o2;
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bus_size_t c;
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{
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for (; c; c--, o1++, o2++)
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bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2));
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}
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#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
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{ int i = c; \
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for (; i; i--, o1 += 4, o2 += 4) \
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bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2)); \
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} while (0)
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extern __inline__ void
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bus_space_copy_region_2(t, h1, o1, h2, o2, c)
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bus_space_tag_t t;
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bus_space_handle_t h1, h2;
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bus_size_t o1, o2;
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bus_size_t c;
|
||||
{
|
||||
for (; c; c--, o1+=2, o2+=2)
|
||||
bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2));
|
||||
}
|
||||
|
||||
extern __inline__ void
|
||||
bus_space_copy_region_4(t, h1, o1, h2, o2, c)
|
||||
bus_space_tag_t t;
|
||||
bus_space_handle_t h1, h2;
|
||||
bus_size_t o1, o2;
|
||||
bus_size_t c;
|
||||
{
|
||||
for (; c; c--, o1+=4, o2+=4)
|
||||
bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2));
|
||||
}
|
||||
|
||||
extern __inline__ void
|
||||
bus_space_copy_region_8(t, h1, o1, h2, o2, c)
|
||||
bus_space_tag_t t;
|
||||
bus_space_handle_t h1, h2;
|
||||
bus_size_t o1, o2;
|
||||
bus_size_t c;
|
||||
{
|
||||
for (; c; c--, o1+=8, o2+=8)
|
||||
bus_space_write_8(t, h1, o1, bus_space_read_8(t, h2, o2));
|
||||
}
|
||||
|
||||
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
|
||||
{ int i = c; \
|
||||
for (; i; i--, o1 += 8, o2 += 8) \
|
||||
bus_space_write_8(t, h1, o1, bus_space_read_4(t, h2, o2)); \
|
||||
} while (0)
|
||||
|
||||
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ctlreg.h,v 1.13 2000/04/10 16:05:13 mrg Exp $ */
|
||||
/* $NetBSD: ctlreg.h,v 1.14 2000/06/02 22:56:33 eeh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-1999 Eduardo Horvath
|
||||
@ -164,6 +164,9 @@
|
||||
#define ASI_BLK_S ASI_BLOCK_SECONDARY
|
||||
#define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE
|
||||
|
||||
#define PHYS_ASI(x) (((x) | 0x09) == 0x1d)
|
||||
#define LITTLE_ASI(x) ((x) & ASI_LITTLE)
|
||||
|
||||
/*
|
||||
* The following are 4u control registers
|
||||
*/
|
||||
@ -432,7 +435,7 @@
|
||||
#ifdef DCACHE_BUG
|
||||
#define lduba(loc, asi) ({ \
|
||||
register int _lduba_v; \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
|
||||
" lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \
|
||||
@ -455,28 +458,33 @@
|
||||
/* load byte from alternate address space */
|
||||
#ifdef DCACHE_BUG
|
||||
#define lduba(loc, asi) ({ \
|
||||
register int _lduba_v, _loc_hi; \
|
||||
register int _lduba_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \
|
||||
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; " \
|
||||
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " \
|
||||
" sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " \
|
||||
" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lduba_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), \
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG)); \
|
||||
} else { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" rdpr %%pstate,%1; wrpr %1,8,%%pstate; " \
|
||||
" or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lduba_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
} \
|
||||
_lduba_v; \
|
||||
})
|
||||
#else
|
||||
#define lduba(loc, asi) ({ \
|
||||
register int _lduba_v, _loc_hi; \
|
||||
register int _lduba_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; sllx %3,32,%0; " \
|
||||
" wrpr %1,8,%%pstate; or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lduba_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
_lduba_v; \
|
||||
})
|
||||
#endif
|
||||
@ -487,7 +495,7 @@
|
||||
#ifdef DCACHE_BUG
|
||||
#define lduha(loc, asi) ({ \
|
||||
register int _lduha_v; \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
|
||||
" lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \
|
||||
@ -510,17 +518,20 @@
|
||||
/* load half-word from alternate address space */
|
||||
#ifdef DCACHE_BUG
|
||||
#define lduha(loc, asi) ({ \
|
||||
register int _lduha_v, _loc_hi; \
|
||||
register int _lduha_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \
|
||||
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \
|
||||
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " \
|
||||
" or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lduha_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), \
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG)); \
|
||||
} else { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \
|
||||
" sllx %3,32,%0; wrpr %1,8,%%pstate; " \
|
||||
" or %0,%2,%0; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lduha_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
} \
|
||||
_lduha_v; \
|
||||
@ -529,9 +540,10 @@
|
||||
#define lduha(loc, asi) ({ \
|
||||
register int _lduha_v, _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1; " \
|
||||
" or %0,%2,%0; wrpr %1,8,%%pstate; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lduha_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
_lduha_v; \
|
||||
})
|
||||
#endif
|
||||
@ -542,7 +554,7 @@
|
||||
#ifdef DCACHE_BUG
|
||||
#define lda(loc, asi) ({ \
|
||||
register int _lda_v; \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
|
||||
" lda [%1]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
@ -557,7 +569,7 @@
|
||||
/* load signed int from alternate address space */
|
||||
#define ldswa(loc, asi) ({ \
|
||||
register int _lda_v; \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
|
||||
" ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
@ -587,17 +599,20 @@
|
||||
/* load unsigned int from alternate address space */
|
||||
#ifdef DCACHE_BUG
|
||||
#define lda(loc, asi) ({ \
|
||||
register int _lda_v, _loc_hi; \
|
||||
register int _lda_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \
|
||||
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; lda [%1]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
|
||||
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " \
|
||||
" sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " \
|
||||
" wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), \
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG)); \
|
||||
} else { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
|
||||
" sllx %3,32,%0; wrpr %1,8,%%pstate;" \
|
||||
" or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
} \
|
||||
_lda_v; \
|
||||
@ -605,37 +620,42 @@
|
||||
|
||||
/* load signed int from alternate address space */
|
||||
#define ldswa(loc, asi) ({ \
|
||||
register int _lda_v, _loc_hi; \
|
||||
register int _lda_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \
|
||||
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
|
||||
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" \
|
||||
" or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), \
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG)); \
|
||||
} else { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0;" \
|
||||
" rdpr %%pstate,%1; wrpr %1,8,%%pstate;" \
|
||||
" or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
} \
|
||||
_lda_v; \
|
||||
})
|
||||
#else
|
||||
#define lda(loc, asi) ({ \
|
||||
register int _lda_v, _loc_hi; \
|
||||
register int _lda_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \
|
||||
" wrpr %1,8,%%pstate; or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%pstate" : \
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
_lda_v; \
|
||||
})
|
||||
|
||||
#define ldswa(loc, asi) ({ \
|
||||
register int _lda_v, _loc_hi; \
|
||||
register int _lda_v, _loc_hi, _pstate;; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \
|
||||
" wrpr %1,8,%%pstate; or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
_lda_v; \
|
||||
})
|
||||
#endif
|
||||
@ -647,7 +667,7 @@
|
||||
/* load 64-bit int from alternate address space */
|
||||
#define ldda(loc, asi) ({ \
|
||||
register long long _lda_v; \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
|
||||
" ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
@ -661,16 +681,18 @@
|
||||
#else
|
||||
/* load 64-bit int from alternate address space */
|
||||
#define ldda(loc, asi) ({ \
|
||||
register long long _lda_v, _loc_hi; \
|
||||
register long long _lda_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; " \
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \
|
||||
" sllx %2,32,%0; or %0,%1,%0; membar #Sync; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
|
||||
" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" \
|
||||
" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" :\
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \
|
||||
} else { \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0;" \
|
||||
" wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
} \
|
||||
_lda_v; \
|
||||
@ -681,7 +703,7 @@
|
||||
/* native load 64-bit int from alternate address space w/64-bit compiler*/
|
||||
#define ldxa(loc, asi) ({ \
|
||||
register long _lda_v; \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; "\
|
||||
" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
|
||||
" ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
@ -697,17 +719,18 @@
|
||||
#define ldxa(loc, asi) ({ \
|
||||
register long _ldxa_lo, _ldxa_hi, _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
if (asi == ASI_PHYS_CACHED) { \
|
||||
if (PHYS_ASI(asi)) { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; " \
|
||||
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; " \
|
||||
" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \
|
||||
" srlx %0,32,%1; srl %0,0,%0" : \
|
||||
" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " \
|
||||
" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \
|
||||
" wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0" : \
|
||||
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), \
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG)); \
|
||||
} else { \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
|
||||
" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; " \
|
||||
" wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0;" : \
|
||||
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
} \
|
||||
@ -727,11 +750,12 @@
|
||||
})
|
||||
#else
|
||||
#define ldda(loc, asi) ({ \
|
||||
register long long _lda_v, _loc_hi; \
|
||||
register long long _lda_v, _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1" \
|
||||
" or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_lda_v), "=&r" (_pstate) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
_lda_v; \
|
||||
})
|
||||
#endif
|
||||
@ -749,8 +773,9 @@
|
||||
#define ldxa(loc, asi) ({ \
|
||||
register long _ldxa_lo, _ldxa_hi, _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \
|
||||
" or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1" \
|
||||
" or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \
|
||||
" srlx %0,32,%1; srl %0,0,%0;" : \
|
||||
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
|
||||
"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
|
||||
@ -767,11 +792,12 @@
|
||||
})
|
||||
#else
|
||||
#define stba(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
register int _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
@ -783,11 +809,12 @@
|
||||
})
|
||||
#else
|
||||
#define stha(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
register int _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
@ -799,11 +826,12 @@ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
})
|
||||
#else
|
||||
#define sta(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
register int _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) : \
|
||||
"r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
@ -815,11 +843,12 @@ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
})
|
||||
#else
|
||||
#define stda(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
register int _loc_hi, _pstate; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) : \
|
||||
"r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
@ -834,10 +863,11 @@ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
#define stxa(loc, asi, value) ({ \
|
||||
int _stxa_lo, _stxa_hi, _loc_hi; \
|
||||
_stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \
|
||||
_loc_hi = (((u_int64_t)(long)loc)>>32); \
|
||||
__asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \
|
||||
" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \
|
||||
"=&r" (_loc_hi), "=&r" (_stxa_hi) : \
|
||||
_loc_hi = (((u_int64_t)(u_long)loc)>>32); \
|
||||
__asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \
|
||||
" or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \
|
||||
" stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \
|
||||
"=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \
|
||||
"r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
|
||||
"r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: machdep.c,v 1.62 2000/05/26 21:20:21 thorpej Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.63 2000/06/02 22:56:32 eeh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
|
||||
@ -131,6 +131,7 @@
|
||||
|
||||
/* Our exported CPU info; we have only one for now. */
|
||||
struct cpu_info cpu_info_store;
|
||||
int bus_space_debug = 0;
|
||||
|
||||
vm_map_t exec_map = NULL;
|
||||
vm_map_t mb_map = NULL;
|
||||
@ -1219,26 +1220,20 @@ _bus_dmamap_sync(t, map, offset, len, ops)
|
||||
*
|
||||
* Actually a #Sync is expensive. We should optimize.
|
||||
*/
|
||||
switch (ops) {
|
||||
case BUS_DMASYNC_PREREAD:
|
||||
/* Flush any pending writes */
|
||||
if ((ops & BUS_DMASYNC_PREREAD) || (ops & BUS_DMASYNC_PREWRITE)) {
|
||||
/*
|
||||
* Don't really need to do anything, but flush any pending
|
||||
* writes anyway.
|
||||
*/
|
||||
__asm("membar #Sync" : );
|
||||
break;
|
||||
case BUS_DMASYNC_POSTREAD:
|
||||
}
|
||||
if (ops & BUS_DMASYNC_POSTREAD) {
|
||||
/* Invalidate the vcache */
|
||||
blast_vcache();
|
||||
/* Maybe we should flush the I$? */
|
||||
break;
|
||||
case BUS_DMASYNC_PREWRITE:
|
||||
/* Flush any pending writes */
|
||||
__asm("membar #Sync" : );
|
||||
break;
|
||||
case BUS_DMASYNC_POSTWRITE:
|
||||
/* Nothing to do */
|
||||
break;
|
||||
default:
|
||||
__asm("membar #Sync" : );
|
||||
printf("_bus_dmamap_sync: unknown sync op\n");
|
||||
/* Maybe we should flush the I$? When we support LKMs.... */
|
||||
}
|
||||
if (ops & BUS_DMASYNC_POSTWRITE) {
|
||||
/* Nothing to do. Handled by the bus controller. */
|
||||
}
|
||||
}
|
||||
|
||||
@ -1502,6 +1497,7 @@ static vaddr_t iobase = IODEV_BASE;
|
||||
* out of IO mappings, config space will not be mapped in,
|
||||
* rather it will be accessed through MMU bypass ASI accesses.
|
||||
*/
|
||||
if (flags & BUS_SPACE_MAP_LINEAR) return (-1);
|
||||
*hp = (bus_space_handle_t)addr;
|
||||
if (!vaddr) return (0);
|
||||
/* FALLTHROUGH */
|
||||
@ -1516,6 +1512,8 @@ static vaddr_t iobase = IODEV_BASE;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(flags & BUS_SPACE_MAP_CACHEABLE)) pm_flags |= PMAP_NC;
|
||||
|
||||
if (vaddr)
|
||||
v = trunc_page(vaddr);
|
||||
else {
|
||||
@ -1532,12 +1530,13 @@ static vaddr_t iobase = IODEV_BASE;
|
||||
|
||||
#ifdef NOTDEF_DEBUG
|
||||
printf("\nsparc_bus_map: type %x addr %016llx virt %llx paddr %016llx\n",
|
||||
(int)iospace, (u_int64_t)addr, (u_int64_t)*hp, (u_int64_t)pa);
|
||||
(int)iospace, (u_int64_t)addr, (u_int64_t)*hp, (u_int64_t)pa);
|
||||
#endif
|
||||
|
||||
do {
|
||||
#ifdef NOTDEF_DEBUG
|
||||
printf("sparc_bus_map: phys %llx virt %p hp %llx\n", (u_int64_t)pa, (char *)v, (u_int64_t)*hp);
|
||||
printf("sparc_bus_map: phys %llx virt %p hp %llx\n",
|
||||
(u_int64_t)pa, (char *)v, (u_int64_t)*hp);
|
||||
#endif
|
||||
pmap_enter(pmap_kernel(), v, pa | pm_flags,
|
||||
(flags&BUS_SPACE_MAP_READONLY) ? VM_PROT_READ
|
||||
|
||||
Loading…
Reference in New Issue
Block a user