Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)

that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate
pages for r5k-class CPUs with secondary cache.

This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1.

This is the last bit of a patch that has been kicked around since 2000 between
rafal@, tsutsui@, and myself.
This commit is contained in:
sekiya 2005-03-01 04:23:44 +00:00
parent 802400546d
commit 02889050a3
3 changed files with 15 additions and 8 deletions

View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
/* $NetBSD: cache.h,v 1.7 2005/03/01 04:23:44 sekiya Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -185,6 +185,8 @@ extern int mips_sdcache_write_through;
extern int mips_scache_unified;
extern u_int mips_sdcache_forceinv; /* force pmap to invalidate for r5ksc */
/* TERTIARY CACHE VARIABLES */
extern u_int mips_tcache_size; /* always unified */
extern u_int mips_tcache_line_size;

View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.c,v 1.25 2004/12/13 08:39:21 sekiya Exp $ */
/* $NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.25 2004/12/13 08:39:21 sekiya Exp $");
__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@ -129,6 +129,8 @@ int mips_sdcache_write_through;
int mips_scache_unified;
u_int mips_sdcache_forceinv = 0;
/* TERTIARY CACHE VARIABLES */
u_int mips_tcache_size; /* always unified */
u_int mips_tcache_line_size;

View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.156 2005/01/17 04:54:14 atatat Exp $ */
/* $NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@ -74,7 +74,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.156 2005/01/17 04:54:14 atatat Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $");
/*
* Manages physical address maps.
@ -1598,7 +1598,8 @@ pmap_zero_page(phys)
*
* XXXJRT This is totally disgusting.
*/
if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
if (MIPS_HAS_R4K_MMU &&
( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv) ) )
mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
#endif /* MIPS3_PLUS */
}
@ -1635,7 +1636,8 @@ pmap_copy_page(src, dst)
* It would probably be better to map the destination as a
* write-through no allocate to reduce cache thrash.
*/
if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
if (MIPS_HAS_R4K_MMU &&
( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
/*XXX FIXME Not very sophisticated */
mips_flushcache_allpvh(src);
/* mips_flushcache_allpvh(dst); */
@ -1657,7 +1659,8 @@ pmap_copy_page(src, dst)
*
* XXXJRT -- This is totally disgusting.
*/
if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
if (MIPS_HAS_R4K_MMU &&
( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
}