Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)
that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate pages for r5k-class CPUs with secondary cache. This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1. This is the last bit of a patch that has been kicked around since 2000 between rafal@, tsutsui@, and myself.
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02889050a3
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
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/* $NetBSD: cache.h,v 1.7 2005/03/01 04:23:44 sekiya Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -185,6 +185,8 @@ extern int mips_sdcache_write_through;
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extern int mips_scache_unified;
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extern u_int mips_sdcache_forceinv; /* force pmap to invalidate for r5ksc */
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/* TERTIARY CACHE VARIABLES */
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extern u_int mips_tcache_size; /* always unified */
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extern u_int mips_tcache_line_size;
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.25 2004/12/13 08:39:21 sekiya Exp $ */
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/* $NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -68,7 +68,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.25 2004/12/13 08:39:21 sekiya Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $");
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#include "opt_cputype.h"
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#include "opt_mips_cache.h"
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@ -129,6 +129,8 @@ int mips_sdcache_write_through;
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int mips_scache_unified;
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u_int mips_sdcache_forceinv = 0;
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/* TERTIARY CACHE VARIABLES */
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u_int mips_tcache_size; /* always unified */
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u_int mips_tcache_line_size;
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.156 2005/01/17 04:54:14 atatat Exp $ */
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/* $NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $ */
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/*-
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* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
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@ -74,7 +74,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.156 2005/01/17 04:54:14 atatat Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $");
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/*
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* Manages physical address maps.
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@ -1598,7 +1598,8 @@ pmap_zero_page(phys)
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*
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* XXXJRT This is totally disgusting.
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*/
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if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
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if (MIPS_HAS_R4K_MMU &&
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( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv) ) )
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
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#endif /* MIPS3_PLUS */
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}
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@ -1635,7 +1636,8 @@ pmap_copy_page(src, dst)
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* It would probably be better to map the destination as a
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* write-through no allocate to reduce cache thrash.
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*/
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if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
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if (MIPS_HAS_R4K_MMU &&
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( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
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/*XXX FIXME Not very sophisticated */
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mips_flushcache_allpvh(src);
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/* mips_flushcache_allpvh(dst); */
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@ -1657,7 +1659,8 @@ pmap_copy_page(src, dst)
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*
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* XXXJRT -- This is totally disgusting.
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*/
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if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
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if (MIPS_HAS_R4K_MMU &&
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( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
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}
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