From 024e0031c7c828fb7db39f6aac5d1eb9ba85ce26 Mon Sep 17 00:00:00 2001 From: rjs Date: Mon, 26 Dec 2016 13:28:59 +0000 Subject: [PATCH] Remove trailing whitespace, no functional change. --- sys/arch/arm/allwinner/awin_board.c | 14 +++++++------- sys/arch/arm/allwinner/awin_var.h | 6 +++--- sys/arch/evbarm/awin/awin_start.S | 28 ++++++++++++++-------------- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/sys/arch/arm/allwinner/awin_board.c b/sys/arch/arm/allwinner/awin_board.c index 43c1b240ee0c..a0a1b6d8e53f 100644 --- a/sys/arch/arm/allwinner/awin_board.c +++ b/sys/arch/arm/allwinner/awin_board.c @@ -1,4 +1,4 @@ -/* $NetBSD: awin_board.c,v 1.40 2015/10/25 20:54:19 bouyer Exp $ */ +/* $NetBSD: awin_board.c,v 1.41 2016/12/26 13:28:59 rjs Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -36,7 +36,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.40 2015/10/25 20:54:19 bouyer Exp $"); +__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.41 2016/12/26 13:28:59 rjs Exp $"); #include #include @@ -248,7 +248,7 @@ awin_current_frequency_sysctl_helper(SYSCTLFN_ARGS) for (size_t i = 0; awin_freqs[i].freq > 0; i++) { if (awin_freqs[i].freq == freq) { new_awin_freq = awin_freqs[i]; - error = 0; + error = 0; break; } } @@ -315,7 +315,7 @@ awin_available_frequency_sysctl_helper(SYSCTLFN_ARGS) if (awin_freqs[i].freq < awin_freq_min || awin_freqs[i].freq > awin_freq_max) continue; - snprintf(cur_cpu_freq, sizeof(cur_cpu_freq), "%u", + snprintf(cur_cpu_freq, sizeof(cur_cpu_freq), "%u", awin_freqs[i].freq); if (strlen(available_frequencies) > 0) { strlcat(available_frequencies, " ", availfreq_size); @@ -370,17 +370,17 @@ SYSCTL_SETUP(sysctl_awin_machdep_setup, "sysctl allwinner machdep subtree setup" sysctl_createv(clog, 0, &freqnode, NULL, CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "current", NULL, - awin_current_frequency_sysctl_helper, 0, NULL, 0, + awin_current_frequency_sysctl_helper, 0, NULL, 0, CTL_CREATE, CTL_EOL); sysctl_createv(clog, 0, &freqnode, NULL, CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "min", NULL, - NULL, 0, &awin_freq_min, sizeof(awin_freq_min), + NULL, 0, &awin_freq_min, sizeof(awin_freq_min), CTL_CREATE, CTL_EOL); sysctl_createv(clog, 0, &freqnode, NULL, CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "max", NULL, - NULL, 0, &awin_freq_max, sizeof(awin_freq_max), + NULL, 0, &awin_freq_max, sizeof(awin_freq_max), CTL_CREATE, CTL_EOL); } diff --git a/sys/arch/arm/allwinner/awin_var.h b/sys/arch/arm/allwinner/awin_var.h index 91aea3eb1025..bbde013c4458 100644 --- a/sys/arch/arm/allwinner/awin_var.h +++ b/sys/arch/arm/allwinner/awin_var.h @@ -1,4 +1,4 @@ -/* $NetBSD: awin_var.h,v 1.40 2015/12/26 16:54:41 macallan Exp $ */ +/* $NetBSD: awin_var.h,v 1.41 2016/12/26 13:28:59 rjs Exp $ */ /*- * Copyright (c) 2013 The NetBSD Foundation, Inc. * All rights reserved. @@ -41,7 +41,7 @@ struct awin_locators { const char *loc_name; bus_size_t loc_offset; bus_size_t loc_size; - int loc_port; + int loc_port; int loc_intr; #define AWINIO_INTR_DEFAULT 0 int loc_flags; @@ -101,7 +101,7 @@ extern struct arm32_bus_dma_tag awin_dma_tag; extern struct arm32_bus_dma_tag awin_coherent_dma_tag; psize_t awin_memprobe(void); -void awin_bootstrap(vaddr_t, vaddr_t); +void awin_bootstrap(vaddr_t, vaddr_t); void awin_dma_bootstrap(psize_t); void awin_pll2_enable(void); void awin_pll3_enable(void); diff --git a/sys/arch/evbarm/awin/awin_start.S b/sys/arch/evbarm/awin/awin_start.S index 7ecec51c247f..95a151e8a64f 100644 --- a/sys/arch/evbarm/awin/awin_start.S +++ b/sys/arch/evbarm/awin/awin_start.S @@ -39,9 +39,9 @@ #include "assym.h" #include -#include +#include -RCSID("$NetBSD: awin_start.S,v 1.12 2015/04/18 11:04:49 skrll Exp $") +RCSID("$NetBSD: awin_start.S,v 1.13 2016/12/26 13:28:59 rjs Exp $") #if defined(VERBOSE_INIT_ARM) #define XPUTC(n) mov r0, n; bl xputc @@ -240,13 +240,13 @@ a20_mpinit: dsb /* Ensure CPU1 reset also invalidates its L1 caches */ - ldr r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] + ldr r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] bic r1, r1, #(1 << 1) str r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] dsb /* Hold DBGPWRDUP signal low */ - ldr r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] + ldr r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] bic r1, r1, #(1 << 1) str r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] dsb @@ -263,7 +263,7 @@ a20_mpinit: bl _C_LABEL(gtmr_bootdelay) // endian-neutral /* Clear power-off gating */ - ldr r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG] + ldr r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG] bic r1, r1, #(1 << 1) str r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG] dsb @@ -275,7 +275,7 @@ a20_mpinit: dsb /* Reassert DBGPWRDUP signal */ - ldr r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] + ldr r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] orr r1, r1, #(1 << 1) str r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] dsb @@ -285,7 +285,7 @@ a20_mpinit: #endif // - // Wait up a second for CPU1 to hatch. + // Wait up a second for CPU1 to hatch. // movw r6, #:lower16:arm_cpu_hatched movt r6, #:upper16:arm_cpu_hatched @@ -345,7 +345,7 @@ a31_mpinit_cpu: dsb /* Ensure CPUX reset also invalidates its L1 caches */ - ldr r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] + ldr r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] mov r0, #1 lsl r0, r0, r12 bic r1, r1, r0 @@ -391,9 +391,9 @@ a31_mpinit_cpu: /* We need to wait (at least) 10ms */ mov r0, #0x3b000 // 10.06ms bl _C_LABEL(gtmr_bootdelay) // endian-neutral - + /* Clear power-off gating */ - ldr r1, [r6, #AWIN_A31_PRCM_PWROFF_GATING_REG] + ldr r1, [r6, #AWIN_A31_PRCM_PWROFF_GATING_REG] mov r0, #1 lsl r0, r0, r12 bic r1, r1, r0 @@ -403,7 +403,7 @@ a31_mpinit_cpu: /* We need to wait (at least) 10ms */ mov r0, #0x3b000 // 10.06ms bl _C_LABEL(gtmr_bootdelay) // endian-neutral - + /* Bring CPUX out of reset */ mov r1, #(AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET|AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET) mov r2, #0x40 @@ -422,7 +422,7 @@ a31_mpinit_cpu: #endif // - // Wait up a second for CPU1-3 to hatch. + // Wait up a second for CPU1-3 to hatch. // movw r6, #:lower16:arm_cpu_hatched movt r6, #:upper16:arm_cpu_hatched @@ -510,7 +510,7 @@ a80_mpinit_cpu: bl _C_LABEL(gtmr_bootdelay) // endian-neutral /* Clear power-off gating */ - ldr r1, [r6, #AWIN_A80_RPRCM_CLUSTER0_PWR_GATING_REG] + ldr r1, [r6, #AWIN_A80_RPRCM_CLUSTER0_PWR_GATING_REG] mov r0, #1 lsl r0, r0, r12 bic r1, r1, r0 @@ -546,7 +546,7 @@ a80_mpinit_cpu: #endif // - // Wait up a second for CPU1-3 to hatch. + // Wait up a second for CPU1-3 to hatch. // movw r6, #:lower16:arm_cpu_hatched movt r6, #:upper16:arm_cpu_hatched