- add register & bit defines for GPIO, Peripherals IO Bus, Flash, NAND
This commit is contained in:
cliff
parent
c1a6784525
commit
0224687993
@ -1,4 +1,4 @@
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/* $NetBSD: rmixlreg.h,v 1.3 2011/02/20 07:48:37 matt Exp $ */
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/* $NetBSD: rmixlreg.h,v 1.4 2011/03/18 00:58:35 cliff Exp $ */
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/*-
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* Copyright (c) 2009 The NetBSD Foundation, Inc.
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@ -262,7 +262,7 @@
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#define RMIXL_IO_DEV_I2C_1 0x16000 /* I2C_1 */
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#define RMIXL_IO_DEV_I2C_2 0x17000 /* I2C_2 */
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#define RMIXL_IO_DEV_GPIO 0x18000 /* GPIO */
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#define RMIXL_IO_DEV_FLASH 0x19000 /* Flash ROM */
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#define RMIXL_IO_DEV_FLASH 0x19000 /* Peripherals IO Bus, to Flash memory &etc. */
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#define RMIXL_IO_DEV_DMA 0x1a000 /* DMA */
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#define RMIXL_IO_DEV_L2 0x1b000 /* L2 Cache */
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#define RMIXL_IO_DEV_TB 0x1c000 /* Trace Buffer */
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@ -303,9 +303,11 @@
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#define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n))
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/* DRAM Region Channels B,D Address Translation Regs[0-7] */
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#define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */
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#define RMIXL_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
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#define RMIXL_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */
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#if defined(MIPS64_XLR)
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#define RMIXLR_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
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#define RMIXLR_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */
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#define RMIXLR_SBC_SRAM_BAR _RMIXL_OFFSET(0x1b) /* SRAM Base Addr reg */
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#define RMIXLR_SBC_HTMEM_BAR _RMIXL_OFFSET(0x1c) /* HyperTransport Mem Base Addr reg */
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#define RMIXLR_SBC_HTINT_BAR _RMIXL_OFFSET(0x1d) /* HyperTransport Interrupt Base Addr reg */
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@ -319,8 +321,6 @@
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#define RMIXLR_SBC_SYS2IO_CREDITS _RMIXL_OFFSET(0x35) /* System Bridge I/O Transaction Credits register */
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#endif /* MIPS64_XLR */
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#if defined(MIPS64_XLS)
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#define RMIXLS_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
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#define RMIXLS_SBC_FLASH_BAR _RMIXL_OFFSET(0x20) /* Flash Memory Base Addr reg */
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#define RMIXLS_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */
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#define RMIXLS_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */
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#define RMIXLS_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */
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@ -349,6 +349,19 @@
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#define RMIXL_ADDR_ERR_DBE_COUNTS _RMIXL_OFFSET(0x33) /* Double Bit Error Counts */
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#define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */
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/*
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* RMIXL_SBC_FLASH_BAR bit defines
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*/
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#define RMIXL_FLASH_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */
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#define RMIXL_FLASH_BAR_TO_BA(r) \
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(((r) & RMIXL_FLASH_BAR_BASE) << (24 - 16))
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#define RMIXL_FLASH_BAR_MASK __BITS(15,5) /* phys address mask bits 34:24 */
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#define RMIXL_FLASH_BAR_TO_MASK(r) \
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(((((r) & RMIXL_FLASH_BAR_MASK)) << (24 - 5)) | __BITS(23, 0))
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#define RMIXL_FLASH_BAR_RESV __BITS(4,1) /* (reserved) */
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#define RMIXL_FLASH_BAR_ENB __BIT(0) /* 1=Enable */
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#define RMIXL_FLASH_BAR_MASK_MAX RMIXL_FLASH_BAR_TO_MASK(RMIXL_FLASH_BAR_MASK)
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/*
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* RMIXL_SBC_DRAM_BAR bit defines
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*/
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@ -429,7 +442,6 @@
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#define RMIXL_PCIX_IO_BAR(ba, en) \
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((uint32_t)(((ba) >> (26 - 18)) | ((en) ? RMIXL_PCIX_IO_BAR_ENB : 0)))
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/*
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* RMIXLS_SBC_PCIE_CFG_BAR bit defines
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*/
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@ -563,18 +575,92 @@
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/*
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* GPIO Controller registers
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* bit number is same as GPIO pin number for the GPIO masks below
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*/
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#define RMIXL_GPIO_NSIGNALS 25 /* 25 GPIO signals supported in HW */
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/* GPIO Signal Registers */
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#define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */
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#define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */
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#define RMIXL_GPIO_IO_DIR _RMIXL_OFFSET(0x2) /* I/O Direction register */
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#define RMIXL_GPIO_OUTPUT _RMIXL_OFFSET(0x3) /* Output Write register */
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#define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register */
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#define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Inversion register */
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#define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register */
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#define RMIXL_GPIO_INPUT _RMIXL_OFFSET(0x4) /* Intput Read register *//* ro */
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#define RMIXL_GPIO_INT_CLR _RMIXL_OFFSET(0x5) /* Interrupt Clear register */
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#define RMIXL_GPIO_INT_STS _RMIXL_OFFSET(0x6) /* Interrupt Status register *//* ro */
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#define RMIXL_GPIO_INT_TYP _RMIXL_OFFSET(0x7) /* Interrupt Type register */
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#define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */
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#define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLR/XLS Soft Reset register */
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/*
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* common GPIO bit masks
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*/
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#define RMIXL_GPIO_PGM_MASK (__BITS(13,0) | __BITS(22,20) | __BIT(24)) /* programmable pins */
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#define RMIXL_GPIO_INTR_MASK (__BITS(13,0) | __BITS(24,20)) /* intr-capable pins */
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/*
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* never-programmable fixed-function GPIO signals
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* bit number is same as GPIO pin
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*/
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#define RMIXL_GPIO_FLASH_CPUID __BITS(16,14) /* Flash CPU ID, output only */
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#define RMIXL_GPIO_FLASH_CPUID_SHFT 14
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#define RMIXL_GPIO_FLASH_RDY __BIT(17) /* Flash memory ready, input only */
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#define RMIXL_GPIO_FLASH_ADV __BIT(18) /* Flash memory address valid, output only */
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#define RMIXL_GPIO_FLASH_RESET_N __BIT(19) /* Flash memory reset, output only */
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#define RMIXL_GPIO_THERMAL_INTRPT __BIT(23) /* Thermal interrupt, interrupt only */
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/*
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* RMIXL_GPIO_INT_ENB bits
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*/
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#define RMIXL_GPIO_INT_ENB_MASK RMIXL_GPIO_INTR_MASK
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/*
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* RMIXL_GPIO_INT_INV bits
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* inversion control is possible only on the programmable pins
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*/
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#define RMIXL_GPIO_INT_INV_MASK RMIXL_GPIO_PGM_MASK
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/*
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* RMIXL_GPIO_IO_DIR bits
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* direction control is possible only on the programmable pins
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*/
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#define RMIXL_GPIO_IO_DIR_MASK RMIXL_GPIO_PGM_MASK
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/*
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* RMIXL_GPIO_OUTPUT bits
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* output is possible only on the programmable pins and fixed-function outputs
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*/
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#define RMIXL_GPIO_OUTPUT_MASK (RMIXL_GPIO_PGM_MASK \
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| RMIXL_GPIO_FLASH_ADV \
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| RMIXL_GPIO_FLASH_RESET_N)
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/*
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* RMIXL_GPIO_INPUT bits
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* input is possible only on the programmable pins and fixed-function inputs & interrupts
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*/
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#define RMIXL_GPIO_INPUT_MASK (RMIXL_GPIO_PGM_MASK \
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| RMIXL_GPIO_FLASH_RDY \
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| RMIXL_GPIO_THERMAL_INTRPT)
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/*
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* RMIXL_GPIO_INT_CLR bits
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*/
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#define RMIXL_GPIO_INT_CLR_MASK RMIXL_GPIO_INTR_MASK
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/*
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* RMIXL_GPIO_INT_STS bits
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*/
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#define RMIXL_GPIO_INT_STS_INT_HI_L __BIT(25) /* INT_HI_L (input) requested */
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#define RMIXL_GPIO_INT_STS_INT_LO_L __BIT(26) /* INT_LO_L (input) requested */
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#define RMIXL_GPIO_INT_STS_MASK (RMIXL_GPIO_INTR_MASK \
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| RMIXL_GPIO_INT_STS_INT_LO_L \
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| RMIXL_GPIO_INT_STS_INT_HI_L)
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/*
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* RMIXL_GPIO_INT_TYP bits
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* 0=Edge, 1=Level
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*/
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#define RMIXL_GPIO_INT_TYP_MASK RMIXL_GPIO_INTR_MASK
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/*
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* RMIXL_GPIO_RESET bits
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@ -632,7 +718,7 @@
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*/
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#define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */
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#define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */
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#define RMIXL_GPIO_RESET_CFG_NOOT_NAND __BIT(16) /* Enable boot from NAND Flash */
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#define RMIXL_GPIO_RESET_CFG_BOOT_NAND __BIT(16) /* Enable boot from NAND Flash */
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#define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */
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#define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration:
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* 0 = 32-bit address / 16-bit data
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@ -644,6 +730,15 @@
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#define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */
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#define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */
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/*
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* RMIXL_GPIO_EXT_INT bits
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*/
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#define RMIXL_GPIO_EXT_INT_RESV __BITS(31,4)
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#define RMIXL_GPIO_EXT_INT_HI_MASK __BIT(3) /* mask (input) INT_HI_L */
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#define RMIXL_GPIO_EXT_INT_LO_MASK __BIT(2) /* mask (input) INT_HI_L */
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#define RMIXL_GPIO_EXT_INT_HI_CTL __BIT(1) /* generate (output) INT_HI_L */
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#define RMIXL_GPIO_EXT_INT_LO_CTL __BIT(0) /* generate (output) INT_LO_L */
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/*
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* RMIXL_GPIO_LOW_PWR_DIS bits
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* except as noted, all bits are:
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@ -666,6 +761,85 @@
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*/
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#define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9)
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/*
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* Peripheral I/O bus (Flash/PCMCIA) controller registers
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*/
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#define RMIXL_FLASH_NCS 10 /* number of chip selects */
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#define RMIXL_FLASH_CS_BOOT 0 /* CS0 is boot flash */
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#define RMIXL_FLASH_CS_PCMCIA_CF 6 /* CS6 is PCMCIA compact flash */
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#define RMIXL_FLASH_CSBASE_ADDRn(n) _RMIXL_OFFSET(0x00+(n)) /* CSn Base Address reg */
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#define RMIXL_FLASH_CSADDR_MASKn(n) _RMIXL_OFFSET(0x10+(n)) /* CSn Address Mask reg */
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#define RMIXL_FLASH_CSDEV_PARMn(n) _RMIXL_OFFSET(0x20+(n)) /* CSn Device Parameter reg */
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#define RMIXL_FLASH_CSTIME_PARMAn(n) _RMIXL_OFFSET(0x30+(n)) /* CSn Timing Parameters A reg */
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#define RMIXL_FLASH_CSTIME_PARMBn(n) _RMIXL_OFFSET(0x40+(n)) /* CSn Timing Parameters B reg */
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#define RMIXL_FLASH_INT_MASK _RMIXL_OFFSET(0x50) /* Flash Interrupt Mask reg */
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#define RMIXL_FLASH_INT_STATUS _RMIXL_OFFSET(0x60) /* Flash Interrupt Status reg */
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#define RMIXL_FLASH_ERROR_STATUS _RMIXL_OFFSET(0x70) /* Flash Error Status reg */
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#define RMIXL_FLASH_ERROR_ADDR _RMIXL_OFFSET(0x80) /* Flash Error Address reg */
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/*
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* RMIXL_FLASH_CSDEV_PARMn bits
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*/
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#define RMIXL_FLASH_CSDEV_RESV __BITS(31,16)
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#define RMIXL_FLASH_CSDEV_BFN __BIT(15) /* Boot From Nand
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* 0=Boot from NOR or
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* PCCard Type 1 Flash
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* 1=Boot from NAND
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*/
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#define RMIXL_FLASH_CSDEV_NANDEN __BIT(14) /* NAND Flash Enable
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* 0=NOR
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* 1=NAND
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*/
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#define RMIXL_FLASH_CSDEV_ADVTYPE __BIT(13) /* Add Valid Sensing Type
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* 0=level
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* 1=pulse
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*/
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#define RMIXL_FLASH_CSDEV_PARITY_TYPE __BIT(12) /* Parity Type
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* 0=even
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* 1=odd
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*/
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#define RMIXL_FLASH_CSDEV_PARITY_EN __BIT(11) /* Parity Enable */
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#define RMIXL_FLASH_CSDEV_GENIF_EN __BIT(10) /* Generic PLD/FPGA interface mode
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* if this bit is set, then
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* GPIO[13:10] cannot be used
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* for interrupts
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*/
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#define RMIXL_FLASH_CSDEV_PCMCIA_EN __BIT(9) /* PCMCIA Interface mode */
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#define RMIXL_FLASH_CSDEV_DWIDTH __BITS(8,7) /* Data Bus Width:
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* 00: 8 bit
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* 01: 16 bit
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* 10: 32 bit
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* 11: 8 bit
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*/
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#define RMIXL_FLASH_CSDEV_DWIDTH_SHFT 7
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#define RMIXL_FLASH_CSDEV_MX_ADDR __BIT(6) /* Multiplexed Address
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* 0: non-muxed
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* AD[31:24] = Data,
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* AD[23:0] = Addr
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* 1: muxed
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* External latch required
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*/
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#define RMIXL_FLASH_CSDEV_WAIT_POL __BIT(5) /* WAIT polarity
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* 0: Active high
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* 1: Active low
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*/
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#define RMIXL_FLASH_CSDEV_WAIT_EN __BIT(4) /* Enable External WAIT Ack mode */
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#define RMIXL_FLASH_CSDEV_BURST __BITS(3,1) /* Burst Length:
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* 000: 2x
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* 001: 4x
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* 010: 8x
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* 011: 16x
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* 100: 32x
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*/
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#define RMIXL_FLASH_CSDEV_BURST_SHFT 1
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#define RMIXL_FLASH_CSDEV_BURST_EN __BITS(0) /* Burst Enable */
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/*
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* NAND Flash Memory Control registers
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*/
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#define RMIXL_NAND_CLEn(n) _RMIXL_OFFSET(0x90+(n)) /* CSn 8-bit CLE command value reg */
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#define RMIXL_NAND_ALEn(n) _RMIXL_OFFSET(0xa0+(n)) /* CSn 8-bit ALE address phase reg */
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/*
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* PCIE Interface Controller registers
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