Device driver for the Neterion (S2io) Xframe-I 10Gbit ethernet card.
Still missing: VLAN + IPv6 checksum support.
This commit is contained in:
ragge
parent
1fa8554ba6
commit
0217dc7934
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@ -1,4 +1,4 @@
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# $NetBSD: files.pci,v 1.237 2005/08/29 19:11:33 drochner Exp $
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# $NetBSD: files.pci,v 1.238 2005/09/09 10:30:27 ragge Exp $
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#
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# Config file and device description for machine-independent PCI code.
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# Included by ports that need it. Requires that the SCSI files be
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@ -762,6 +762,11 @@ file dev/pci/if_ipw.c ipw
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attach njs at pci with njs_pci
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file dev/pci/njs_pci.c njs_pci
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# S2io Xframe 10 Gigabit ethernet (Xframe driver)
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device xge: ether, ifnet, arp
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attach xge at pci
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file dev/pci/if_xge.c xge
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# Intel PRO/Wireless 2200BG/2915ABG
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device iwi: ifnet, wlan
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attach iwi at pci
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,427 @@
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/* $NetBSD: if_xgereg.h,v 1.1 2005/09/09 10:30:27 ragge Exp $ */
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/*
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* Copyright (c) 2004, SUNET, Swedish University Computer Network.
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* All rights reserved.
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*
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* Written by Anders Magnusson for SUNET, Swedish University Computer Network.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* SUNET, Swedish University Computer Network.
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* 4. The name of SUNET may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SUNET
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Defines for the S2io Xframe adapter.
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*/
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/* PCI address space */
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#define XGE_PIF_BAR 0x10
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#define XGE_TXP_BAR 0x18
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/* PIF register address calculation */
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#define DCSRB(x) (0x0000+(x)) /* 10GbE Device Control and Status Registers */
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#define PCIXB(x) (0x0800+(x)) /* PCI-X Interface Functional Registers */
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#define TDMAB(x) (0x1000+(x)) /* Transmit DMA Functional Registers */
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#define RDMAB(x) (0x1800+(x)) /* Receive DMA Functional Registers */
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#define MACRB(x) (0x2000+(x)) /* MAC functional registers */
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#define RLDRB(x) (0x2800+(x)) /* RLDRAM memory controller */
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#define XGXSB(x) (0x3000+(x)) /* XGXS functional Registers */
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/*
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* Control and Status Registers
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*/
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#define GENERAL_INT_STATUS DCSRB(0x0000)
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#define GENERAL_INT_MASK DCSRB(0x0008)
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#define SW_RESET DCSRB(0x0100)
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#define XGXS_RESET(x) ((uint64_t)(x) << 32)
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#define ADAPTER_STATUS DCSRB(0x0108)
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#define TDMA_READY (1ULL<<63)
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#define RDMA_READY (1ULL<<62)
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#define PFC_READY (1ULL<<61)
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#define TMAC_BUF_EMPTY (1ULL<<60)
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#define PIC_QUIESCENT (1ULL<<58)
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#define RMAC_REMOTE_FAULT (1ULL<<57)
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#define RMAC_LOCAL_FAULT (1ULL<<56)
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#define MC_DRAM_READY (1ULL<<39)
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#define MC_QUEUES_READY (1ULL<<38)
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#define M_PLL_LOCK (1ULL<<33)
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#define P_PLL_LOCK (1ULL<<32)
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#define ADAPTER_CONTROL DCSRB(0x0110)
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#define ADAPTER_EN (1ULL<<56)
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#define EOI_TX_ON (1ULL<<48)
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#define LED_ON (1ULL<<40)
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#define WAIT_INT_EN (1ULL<<15)
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#define ECC_ENABLE_N (1ULL<<8)
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/* for debug of ADAPTER_STATUS */
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#define QUIESCENT (TDMA_READY|RDMA_READY|PFC_READY|TMAC_BUF_EMPTY|\
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PIC_QUIESCENT|MC_DRAM_READY|MC_QUEUES_READY|M_PLL_LOCK|P_PLL_LOCK)
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#define QUIESCENT_BMSK \
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"\177\20b\x3fTDMA_READY\0b\x3eRDMA_READY\0b\x3dPFC_READY\0" \
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"b\x3cTMAC_BUF_EMPTY\0b\x3aPIC_QUIESCENT\0\x39RMAC_REMOTE_FAULT\0" \
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"b\x38RMAC_LOCAL_FAULT\0b\x27MC_DRAM_READY\0b\x26MC_QUEUES_READY\0" \
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"b\x21M_PLL_LOCK\0b\x20P_PLL_LOCK"
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/*
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* PCI-X registers
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*/
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/* Interrupt control registers */
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#define PIC_INT_STATUS PCIXB(0)
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#define PIC_INT_MASK PCIXB(0x008)
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#define TXPIC_INT_MASK PCIXB(0x018)
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#define RXPIC_INT_MASK PCIXB(0x030)
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#define FLASH_INT_MASK PCIXB(0x048)
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#define MDIO_INT_MASK PCIXB(0x060)
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#define IIC_INT_MASK PCIXB(0x078)
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#define GPIO_INT_MASK PCIXB(0x098)
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#define TX_TRAFFIC_INT PCIXB(0x0e0)
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#define TX_TRAFFIC_MASK PCIXB(0x0e8)
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#define RX_TRAFFIC_INT PCIXB(0x0f0)
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#define RX_TRAFFIC_MASK PCIXB(0x0f8)
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#define PIC_CONTROL PCIXB(0x100)
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/* Byte swapping for little-endian */
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#define SWAPPER_CTRL PCIXB(0x108)
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#define PIF_R_FE (1ULL<<63)
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#define PIF_R_SE (1ULL<<62)
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#define PIF_W_FE (1ULL<<55)
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#define PIF_W_SE (1ULL<<54)
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#define TxP_FE (1ULL<<47)
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#define TxP_SE (1ULL<<46)
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#define TxD_R_FE (1ULL<<45)
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#define TxD_R_SE (1ULL<<44)
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#define TxD_W_FE (1ULL<<43)
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#define TxD_W_SE (1ULL<<42)
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#define TxF_R_FE (1ULL<<41)
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#define TxF_R_SE (1ULL<<40)
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#define RxD_R_FE (1ULL<<31)
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#define RxD_R_SE (1ULL<<30)
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#define RxD_W_FE (1ULL<<29)
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#define RxD_W_SE (1ULL<<28)
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#define RxF_W_FE (1ULL<<27)
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#define RxF_W_SE (1ULL<<26)
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#define XMSI_FE (1ULL<<23)
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#define XMSI_SE (1ULL<<22)
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#define STATS_FE (1ULL<<15)
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#define STATS_SE (1ULL<<14)
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/* Diagnostic register to check byte-swapping conf */
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#define PIF_RD_SWAPPER_Fb PCIXB(0x110)
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#define SWAPPER_MAGIC 0x0123456789abcdefULL
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/* Stats registers */
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#define STAT_CFG PCIXB(0x1d0)
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#define STAT_ADDR PCIXB(0x1d8)
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/* DTE-XGXS Interface */
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#define MDIO_CONTROL PCIXB(0x1e0)
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#define DTX_CONTROL PCIXB(0x1e8)
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#define I2C_CONTROL PCIXB(0x1f0)
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#define GPIO_CONTROL PCIXB(0x1f8)
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/*
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* Transmit DMA registers.
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*/
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#define TXDMA_INT_MASK TDMAB(0x008)
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#define PFC_ERR_MASK TDMAB(0x018)
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#define TDA_ERR_MASK TDMAB(0x030)
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#define PCC_ERR_MASK TDMAB(0x048)
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#define TTI_ERR_MASK TDMAB(0x060)
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#define LSO_ERR_MASK TDMAB(0x078)
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#define TPA_ERR_MASK TDMAB(0x090)
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#define SM_ERR_MASK TDMAB(0x0a8)
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/* Transmit FIFO config */
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#define TX_FIFO_P0 TDMAB(0x0108)
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#define TX_FIFO_P1 TDMAB(0x0110)
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#define TX_FIFO_P2 TDMAB(0x0118)
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#define TX_FIFO_P3 TDMAB(0x0120)
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#define TX_FIFO_ENABLE (1ULL<<63)
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#define TX_FIFO_NUM0(x) ((uint64_t)(x) << 56)
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#define TX_FIFO_LEN0(x) ((uint64_t)((x)-1) << 32)
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#define TX_FIFO_NUM1(x) ((uint64_t)(x) << 24)
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#define TX_FIFO_LEN1(x) ((uint64_t)((x)-1) << 0)
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/* Transmit interrupts */
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#define TTI_COMMAND_MEM TDMAB(0x150)
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#define TTI_CMD_MEM_WE (1ULL<<56)
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#define TTI_CMD_MEM_STROBE (1ULL<<48)
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#define TTI_DATA1_MEM TDMAB(0x158)
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#define TX_TIMER_VAL(x) ((uint64_t)(x) << 32)
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#define TX_TIMER_AC (1ULL<<25)
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#define TX_TIMER_CI (1ULL<<24)
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#define TX_URNG_A(x) ((uint64_t)(x) << 16)
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#define TX_URNG_B(x) ((uint64_t)(x) << 8)
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#define TX_URNG_C(x) ((uint64_t)(x) << 0)
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#define TTI_DATA2_MEM TDMAB(0x160)
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#define TX_UFC_A(x) ((uint64_t)(x) << 48)
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#define TX_UFC_B(x) ((uint64_t)(x) << 32)
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#define TX_UFC_C(x) ((uint64_t)(x) << 16)
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#define TX_UFC_D(x) ((uint64_t)(x) << 0)
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/* Transmit protocol assist */
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#define TX_PA_CFG TDMAB(0x0168)
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#define TX_PA_CFG_IFR (1ULL<<62) /* Ignore frame error */
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#define TX_PA_CFG_ISO (1ULL<<61) /* Ignore snap OUI */
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#define TX_PA_CFG_ILC (1ULL<<60) /* Ignore LLC ctrl */
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#define TX_PA_CFG_ILE (1ULL<<57) /* Ignore L2 error */
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/*
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* Transmit descriptor list (TxDL) pointer and control.
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* There may be up to 8192 TxDL's per FIFO, but with a NIC total
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* of 8192. The TxDL's are located in the NIC memory.
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* Each TxDL can have up to 256 Transmit descriptors (TxD)
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* that are located in host memory.
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*
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* The txdl struct fields must be written in order.
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*/
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#ifdef notdef /* Use bus_space stuff instead */
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struct txdl {
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uint64_t txdl_pointer; /* address of TxD's */
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uint64_t txdl_control;
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};
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#endif
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#define TXDLOFF1(x) (16*(x)) /* byte offset in txdl for list */
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#define TXDLOFF2(x) (16*(x)+8) /* byte offset in txdl for list */
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#define TXDL_NUMTXD(x) ((uint64_t)(x) << 56) /* # of TxD's in the list */
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#define TXDL_LGC_FIRST (1ULL << 49) /* First special list */
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#define TXDL_LGC_LAST (1ULL << 48) /* Last special list */
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#define TXDL_SFF (1ULL << 40) /* List is a special function list */
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#define TXDL_PAR 0 /* Pointer address register */
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#define TXDL_LCR 8 /* List control register */
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struct txd {
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uint64_t txd_control1;
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uint64_t txd_control2;
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uint64_t txd_bufaddr;
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uint64_t txd_hostctrl;
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};
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#define TXD_CTL1_OWN (1ULL << 56) /* Owner, 0 == host, 1 == NIC */
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#define TXD_CTL1_GCF (1ULL << 41) /* First frame or LSO */
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#define TXD_CTL1_GCL (1ULL << 40) /* Last frame or LSO */
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#define TXD_CTL1_LSO (1ULL << 33) /* LSO should be performed */
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#define TXD_CTL1_COF (1ULL << 32) /* UDP Checksum over fragments */
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#define TXD_CTL1_MSS(x) ((uint64_t)(x) << 16)
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#define TXD_CTL2_INTLST (1ULL << 16) /* Per-list interrupt */
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#define TXD_CTL2_UTIL (1ULL << 17) /* Utilization interrupt */
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#define TXD_CTL2_CIPv4 (1ULL << 58) /* Calculate IPv4 header checksum */
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#define TXD_CTL2_CTCP (1ULL << 57) /* Calculate TCP checksum */
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#define TXD_CTL2_CUDP (1ULL << 56) /* Calculate UDP checksum */
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/*
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* Receive DMA registers
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*/
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/* Receive interrupt registers */
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#define RXDMA_INT_MASK RDMAB(0x008)
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#define RDA_ERR_MASK RDMAB(0x018)
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#define RC_ERR_MASK RDMAB(0x030)
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#define PRC_PCIX_ERR_MASK RDMAB(0x048)
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#define RPA_ERR_MASK RDMAB(0x060)
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#define RTI_ERR_MASK RDMAB(0x078)
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#define RX_QUEUE_PRIORITY RDMAB(0x100)
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#define RX_W_ROUND_ROBIN_0 RDMAB(0x108)
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#define RX_W_ROUND_ROBIN_1 RDMAB(0x110)
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#define RX_W_ROUND_ROBIN_2 RDMAB(0x118)
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#define RX_W_ROUND_ROBIN_3 RDMAB(0x120)
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#define RX_W_ROUND_ROBIN_4 RDMAB(0x128)
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#define PRC_RXD0_0 RDMAB(0x130)
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#define PRC_CTRL_0 RDMAB(0x170)
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#define RC_IN_SVC (1ULL << 56)
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#define RING_MODE_1 (0ULL << 48)
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#define RING_MODE_3 (1ULL << 48)
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#define RING_MODE_5 (2ULL << 48)
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#define RC_NO_SNOOP_D (1ULL << 41)
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#define RC_NO_SNOOP_B (1ULL << 40)
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#define PRC_ALARM_ACTION RDMAB(0x1b0)
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#define RTI_COMMAND_MEM RDMAB(0x1b8)
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#define RTI_CMD_MEM_WE (1ULL << 56)
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#define RTI_CMD_MEM_STROBE (1ULL << 48)
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#define RTI_DATA1_MEM RDMAB(0x1c0)
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#define RX_TIMER_VAL(x) ((uint64_t)(x) << 32)
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#define RX_TIMER_AC (1ULL << 25)
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#define RX_URNG_A(x) ((uint64_t)(x) << 16)
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#define RX_URNG_B(x) ((uint64_t)(x) << 8)
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#define RX_URNG_C(x) ((uint64_t)(x) << 0)
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#define RTI_DATA2_MEM RDMAB(0x1c8)
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#define RX_UFC_A(x) ((uint64_t)(x) << 48)
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#define RX_UFC_B(x) ((uint64_t)(x) << 32)
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#define RX_UFC_C(x) ((uint64_t)(x) << 16)
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#define RX_UFC_D(x) ((uint64_t)(x) << 0)
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#define RX_PA_CFG RDMAB(0x1d0)
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/*
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* Receive descriptor (RxD) format.
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* There are three formats of receive descriptors, 1, 3 and 5 buffer format.
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*/
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#define RX_MODE_1 1
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#define RX_MODE_3 3
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#define RX_MODE_5 5
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struct rxd1 {
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uint64_t rxd_hcontrol;
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uint64_t rxd_control1;
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uint64_t rxd_control2;
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uint64_t rxd_buf0;
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};
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/* 4k struct for 5 buffer mode */
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#define NDESC_1BUFMODE 127 /* # desc/page for 5-buffer mode */
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struct rxd1_4k {
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struct rxd1 r4_rxd[NDESC_1BUFMODE];
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uint64_t pad[3];
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uint64_t r4_next; /* phys address of next 4k buffer */
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};
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struct rxd3 {
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uint64_t rxd_hcontrol;
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uint64_t rxd_control1;
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uint64_t rxd_control2;
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uint64_t rxd_buf0;
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uint64_t rxd_buf1;
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uint64_t rxd_buf2;
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};
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struct rxd5 {
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uint64_t rxd_control3;
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uint64_t rxd_control1;
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uint64_t rxd_control2;
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uint64_t rxd_buf0;
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uint64_t rxd_buf1;
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uint64_t rxd_buf2;
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uint64_t rxd_buf3;
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uint64_t rxd_buf4;
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};
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/* 4k struct for 5 buffer mode */
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#define NDESC_5BUFMODE 63 /* # desc/page for 5-buffer mode */
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#define XGE_PAGE 4096 /* page size used for receive */
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struct rxd5_4k {
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struct rxd5 r4_rxd[NDESC_5BUFMODE];
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uint64_t pad[7];
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uint64_t r4_next; /* phys address of next 4k buffer */
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};
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#define RXD_MKCTL3(h,bs3,bs4) \
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(((uint64_t)(h) << 32) | ((uint64_t)(bs3) << 16) | (uint64_t)(bs4))
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#define RXD_MKCTL2(bs0,bs1,bs2) \
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(((uint64_t)(bs0) << 48) | ((uint64_t)(bs1) << 32) | \
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((uint64_t)(bs2) << 16))
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#define RXD_CTL2_BUF0SIZ(x) (((x) >> 48) & 0xffff)
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#define RXD_CTL2_BUF1SIZ(x) (((x) >> 32) & 0xffff)
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#define RXD_CTL2_BUF2SIZ(x) (((x) >> 16) & 0xffff)
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#define RXD_CTL3_BUF3SIZ(x) (((x) >> 16) & 0xffff)
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#define RXD_CTL3_BUF4SIZ(x) ((x) & 0xffff)
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#define RXD_CTL1_OWN (1ULL << 56)
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#define RXD_CTL1_XCODE(x) (((x) >> 48) & 0xf) /* Status bits */
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#define RXD_CTL1_X_OK 0
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#define RXD_CTL1_X_PERR 1 /* Parity error */
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#define RXD_CTL1_X_ABORT 2 /* Abort during xfer */
|
||||
#define RXD_CTL1_X_PA 3 /* Parity error and abort */
|
||||
#define RXD_CTL1_X_RDA 4 /* RDA failure */
|
||||
#define RXD_CTL1_X_UP 5 /* Unknown protocol */
|
||||
#define RXD_CTL1_X_FI 6 /* Frame integrity (FCS) error */
|
||||
#define RXD_CTL1_X_BSZ 7 /* Buffer size error */
|
||||
#define RXD_CTL1_X_ECC 8 /* Internal ECC */
|
||||
#define RXD_CTL1_X_UNK 15 /* Unknown error */
|
||||
#define RXD_CTL1_PROTOS(x) (((x) >> 32) & 0xff)
|
||||
#define RXD_CTL1_P_VLAN 0x80 /* VLAN tagged */
|
||||
#define RXD_CTL1_P_MSK 0x60 /* Mask for frame type */
|
||||
#define RXD_CTL1_P_DIX 0x00
|
||||
#define RXD_CTL1_P_LLC 0x20
|
||||
#define RXD_CTL1_P_SNAP 0x40
|
||||
#define RXD_CTL1_P_IPX 0x60
|
||||
#define RXD_CTL1_P_IPv4 0x10
|
||||
#define RXD_CTL1_P_IPv6 0x08
|
||||
#define RXD_CTL1_P_IPFRAG 0x04
|
||||
#define RXD_CTL1_P_TCP 0x02
|
||||
#define RXD_CTL1_P_UDP 0x01
|
||||
#define RXD_CTL1_L3CSUM(x) (((x) >> 16) & 0xffff)
|
||||
#define RXD_CTL1_L4CSUM(x) ((x) & 0xffff)
|
||||
#define RXD_CTL2_VLANTAG(x) ((x) & 0xffff)
|
||||
|
||||
/*
|
||||
* MAC Configuration/Status
|
||||
*/
|
||||
#define MAC_INT_STATUS MACRB(0x000)
|
||||
#define MAC_TMAC_INT (1ULL<<63)
|
||||
#define MAC_RMAC_INT (1ULL<<62)
|
||||
#define MAC_INT_MASK MACRB(0x008)
|
||||
#define MAC_TMAC_ERR_MASK MACRB(0x018)
|
||||
#define MAC_RMAC_ERR_REG MACRB(0x028)
|
||||
#define RMAC_LINK_STATE_CHANGE_INT (1ULL<<32)
|
||||
#define MAC_RMAC_ERR_MASK MACRB(0x030)
|
||||
|
||||
#define MAC_CFG MACRB(0x0100)
|
||||
#define TMAC_EN (1ULL<<63)
|
||||
#define RMAC_EN (1ULL<<62)
|
||||
#define UTILZATION_CALC_SEL (1ULL<<61)
|
||||
#define TMAC_LOOPBACK (1ULL<<60)
|
||||
#define TMAC_APPEND_PAD (1ULL<<59)
|
||||
#define RMAC_STRIP_FCS (1ULL<<58)
|
||||
#define RMAC_STRIP_PAD (1ULL<<57)
|
||||
#define RMAC_PROM_EN (1ULL<<56)
|
||||
#define RMAC_DISCARD_PFRM (1ULL<<55)
|
||||
#define RMAC_BCAST_EN (1ULL<<54)
|
||||
#define RMAC_ALL_ADDR_EN (1ULL<<53)
|
||||
#define RMAC_MAX_PYLD_LEN MACRB(0x0110)
|
||||
#define RMAC_PYLD_LEN(x) ((uint64_t)(x) << 48)
|
||||
#define RMAC_CFG_KEY MACRB(0x0120)
|
||||
#define RMAC_KEY_VALUE (0x4c0dULL<<48)
|
||||
#define RMAC_ADDR_CMD_MEM MACRB(0x0128)
|
||||
#define RMAC_ADDR_CMD_MEM_WE (1ULL<<56)
|
||||
#define RMAC_ADDR_CMD_MEM_STR (1ULL<<48)
|
||||
#define RMAC_ADDR_CMD_MEM_OFF(x) ((uint64_t)(x) << 32)
|
||||
#define MAX_MCAST_ADDR 64 /* slots in mcast table */
|
||||
#define RMAC_ADDR_DATA0_MEM MACRB(0x0130)
|
||||
#define RMAC_ADDR_DATA1_MEM MACRB(0x0138)
|
||||
#define RMAC_PAUSE_CFG MACRB(0x150)
|
||||
#define RMAC_PAUSE_GEN_EN (1ULL<<63)
|
||||
#define RMAC_PAUSE_RCV_EN (1ULL<<62)
|
||||
|
||||
/*
|
||||
* RLDRAM registers.
|
||||
*/
|
||||
#define MC_INT_MASK RLDRB(0x008)
|
||||
#define MC_ERR_MASK RLDRB(0x018)
|
||||
|
||||
#define RX_QUEUE_CFG RLDRB(0x100)
|
||||
#define MC_QUEUE(q,s) ((uint64_t)(s)<<(56-(q*8)))
|
||||
#define MC_RLDRAM_MRS RLDRB(0x108)
|
||||
#define MC_QUEUE_SIZE_ENABLE (1ULL<<24)
|
||||
#define MC_RLDRAM_MRS_ENABLE (1ULL<<16)
|
||||
|
||||
/*
|
||||
* XGXS registers.
|
||||
*/
|
||||
/* XGXS control/statue */
|
||||
#define XGXS_INT_MASK XGXSB(0x008)
|
||||
#define XGXS_TXGXS_ERR_MASK XGXSB(0x018)
|
||||
#define XGXS_RXGXS_ERR_MASK XGXSB(0x030)
|
||||
#define XGXS_CFG XGXSB(0x0100)
|
||||
Loading…
Reference in New Issue