From 01a4486595de7a8d327d349e981112b879bc9e39 Mon Sep 17 00:00:00 2001
From: mhitch <mhitch@NetBSD.org>
Date: Sat, 6 Nov 1999 17:35:55 +0000
Subject: [PATCH] Try to document the use of the XContext register in the
 TLBMiss and XTLBMiss exception handlers.

---
 sys/arch/mips/mips/locore_mips3.S | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/sys/arch/mips/mips/locore_mips3.S b/sys/arch/mips/mips/locore_mips3.S
index 05cec6c294b2..46d09a8b6f59 100644
--- a/sys/arch/mips/mips/locore_mips3.S
+++ b/sys/arch/mips/mips/locore_mips3.S
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore_mips3.S,v 1.11 1999/10/29 03:36:18 simonb Exp $	*/
+/*	$NetBSD: locore_mips3.S,v 1.12 1999/11/06 17:35:55 mhitch Exp $	*/
 
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -138,13 +138,22 @@
  * Don't check for invalid pte's here. We load them as well and
  * let the processor trap to load the correct value after service.
  *
+ * NOTE:  This relies on a non-standard use of the XContext register.  The
+ * upper 32 bits of the XContext register is loaded with the 32-bit address
+ * of the user PT segment table.  This eliminatees the need to load the
+ * address of the segment table from memory on each miss.
+ * Also, the BadVAddr register contains the virtual address that caused the
+ * TLBmiss - the 32-bit address is signed extended to 64 bits in the BadVAddr
+ * register, so the upper 32 bits will be the same as bit 31 of the virtual
+ * address and is used to check for a user or kernel address.
+ *
  *----------------------------------------------------------------------------
  */
 VECTOR(mips3_TLBMiss, unknown)
 	.set	noat
 	dmfc0	k0, MIPS_COP_0_BAD_VADDR	# get the virtual address
 	dmfc0	k1, MIPS_COP_0_TLB_XCONTEXT
-	bltz	k0, 4f
+	bltz	k0, 4f			# Kernel address (KSEG) if bit 31 set
 	srl	k0, k0, SEGSHIFT - 2	# compute segment table index
 	andi	k0, k0, 0x7fc		# index of segment table
 	dsra	k1, k1, 32		# Tricky -- The lower bit is
@@ -201,11 +210,20 @@ VECTOR_END(mips3_TLBMiss)
  *
  * Don't check for invalid pte's here. We load them as well and
  * let the processor trap to load the correct value after service.
+ *
+ * NOTE:  This also relies on a non-standard use of the XContext register.  The
+ * upper 32 bits of the XContext register is loaded with the 32-bit address
+ * of the user PT segment table.  This eliminatees the need to load the
+ * address of the segment table from memory on each miss.  The 32-bit address
+ * is shifted to form the 64-bit address, and will be a KSEG0 compatibility
+ * mode address (tricky!).
+ * Bit 63 in the BadVAddr register will be 0 for a user address, 1 for
+ * a kernel address.
  */
 VECTOR(mips3_XTLBMiss, unknown)
 	dmfc0	k0, MIPS_COP_0_BAD_VADDR	# get the virtual address
 	dmfc0	k1, MIPS_COP_0_TLB_XCONTEXT
-	bltz	k0, 4f
+	bltz	k0, 4f			# Kernel address if bit 63 set.
 	srl	k0, k0, SEGSHIFT - 2	# compute segment table index
 	andi	k0, k0, 0x7fc		# index of segment table
 	dsra	k1, k1, 32		# Tricky -- The lower bit is