Tidy up and correct some comments.
Replace the hand generated 28 lines that initialised fpetable[] with some pre-processor expressions. The latter was verified to give the same table entries.
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dsl
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75e68238c2
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01540ebaad
@ -1,4 +1,4 @@
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/* $NetBSD: npx.c,v 1.152 2014/02/04 21:09:23 dsl Exp $ */
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/* $NetBSD: npx.c,v 1.153 2014/02/09 22:47:04 dsl Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -96,13 +96,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.152 2014/02/04 21:09:23 dsl Exp $");
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#if 0
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#define IPRINTF(x) printf x
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#else
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#define IPRINTF(x)
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#endif
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__KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.153 2014/02/09 22:47:04 dsl Exp $");
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#include "opt_multiprocessor.h"
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#include "opt_xen.h"
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@ -137,7 +131,7 @@ __KERNEL_RCSID(0, "$NetBSD: npx.c,v 1.152 2014/02/04 21:09:23 dsl Exp $");
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*
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* DNA exceptions are handled like this:
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*
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* 1) If there is no NPX, return and go to the emulator.
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* 1) If there is no NPX, we ought to kill the process.
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* 2) If someone else has used the NPX, save its state into that process's PCB.
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* 3a) If MDL_USEDFPU is not set, set it and initialize the NPX.
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* 3b) Otherwise, reload the process's previous NPX state.
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@ -158,9 +152,6 @@ void fpudna(struct cpu_info *);
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#define stts() HYPERVISOR_fpu_taskswitch(1)
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#endif
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volatile u_int npx_intrs_while_probing;
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volatile u_int npx_traps_while_probing;
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extern int i386_fpu_present;
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extern int i386_fpu_fdivbug;
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@ -239,8 +230,6 @@ npxintr(void *arg, struct intrframe *frame)
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x86_enable_intr();
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#endif
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IPRINTF(("%s: fp intr\n", device_xname(ci->ci_dev)));
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/*
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* At this point, fpcurlwp should be curlwp. If it wasn't, the TS
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* bit should be set, and we should have gotten a DNA exception.
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@ -371,6 +360,8 @@ fpudna(struct cpu_info *ci)
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struct pcb *pcb;
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int s;
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/* XXX generate signal if no fpu */
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/* Lock out IPIs and disable preemption. */
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s = splhigh();
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#ifndef XEN
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@ -433,7 +424,7 @@ fpudna(struct cpu_info *ci)
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* manually.
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*/
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static const double zero = 0.0;
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int status;
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uint16_t status;
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/*
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* Clear the ES bit in the x87 status word if it is currently
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* set, in order to avoid causing a fault in the upcoming load.
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@ -528,8 +519,7 @@ fpusave_lwp(struct lwp *l, bool save)
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#else /* XEN */
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x86_send_ipi(oci, X86_IPI_SYNCH_FPU);
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#endif
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while (pcb->pcb_fpcpu == oci &&
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ticks == hardclock_ticks) {
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while (pcb->pcb_fpcpu == oci && ticks == hardclock_ticks) {
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x86_pause();
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spins++;
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}
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@ -583,137 +573,40 @@ fpusave_lwp(struct lwp *l, bool save)
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* 4 Denormal operand (FP_X_DNML)
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* 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
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* 6 Inexact result (FP_X_IMP)
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*
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* NB: the above seems to mix up the mxscr error bits and the x87 ones.
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* They are in the same order, but there is no EN_SW_STACK_FAULT in the mmx
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* status.
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*
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* The table is nearly, but not quite, in bit order (ZERODIV and DENORM
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* are swapped).
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*
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* This table assumes that any stack fault is cleared - so that an INVOP
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* fault will only be reported as FLTSUB once.
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* This might not happen if the mask is being changed.
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*/
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#define FPE_xxx1(f) (f & EN_SW_INVOP \
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? (f & EN_SW_STACK_FAULT ? FPE_FLTSUB : FPE_FLTINV) \
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: f & EN_SW_ZERODIV ? FPE_FLTDIV \
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: f & EN_SW_DENORM ? FPE_FLTUND \
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: f & EN_SW_OVERFLOW ? FPE_FLTOVF \
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: f & EN_SW_UNDERFLOW ? FPE_FLTUND \
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: f & EN_SW_PRECLOSS ? FPE_FLTRES \
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: f & EN_SW_STACK_FAULT ? FPE_FLTSUB : 0)
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#define FPE_xxx2(f) FPE_xxx1(f), FPE_xxx1((f + 1))
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#define FPE_xxx4(f) FPE_xxx2(f), FPE_xxx2((f + 2))
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#define FPE_xxx8(f) FPE_xxx4(f), FPE_xxx4((f + 4))
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#define FPE_xxx16(f) FPE_xxx8(f), FPE_xxx8((f + 8))
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#define FPE_xxx32(f) FPE_xxx16(f), FPE_xxx16((f + 16))
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static const uint8_t fpetable[128] = {
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0,
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FPE_FLTINV, /* 1 - INV */
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FPE_FLTUND, /* 2 - DNML */
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FPE_FLTINV, /* 3 - INV | DNML */
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FPE_FLTDIV, /* 4 - DZ */
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FPE_FLTINV, /* 5 - INV | DZ */
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FPE_FLTDIV, /* 6 - DNML | DZ */
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FPE_FLTINV, /* 7 - INV | DNML | DZ */
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FPE_FLTOVF, /* 8 - OFL */
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FPE_FLTINV, /* 9 - INV | OFL */
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FPE_FLTUND, /* A - DNML | OFL */
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FPE_FLTINV, /* B - INV | DNML | OFL */
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FPE_FLTDIV, /* C - DZ | OFL */
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FPE_FLTINV, /* D - INV | DZ | OFL */
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FPE_FLTDIV, /* E - DNML | DZ | OFL */
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FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
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FPE_FLTUND, /* 10 - UFL */
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FPE_FLTINV, /* 11 - INV | UFL */
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FPE_FLTUND, /* 12 - DNML | UFL */
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FPE_FLTINV, /* 13 - INV | DNML | UFL */
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FPE_FLTDIV, /* 14 - DZ | UFL */
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FPE_FLTINV, /* 15 - INV | DZ | UFL */
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FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
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FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
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FPE_FLTOVF, /* 18 - OFL | UFL */
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FPE_FLTINV, /* 19 - INV | OFL | UFL */
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FPE_FLTUND, /* 1A - DNML | OFL | UFL */
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FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
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FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
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FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
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FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
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FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
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FPE_FLTRES, /* 20 - IMP */
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FPE_FLTINV, /* 21 - INV | IMP */
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FPE_FLTUND, /* 22 - DNML | IMP */
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FPE_FLTINV, /* 23 - INV | DNML | IMP */
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FPE_FLTDIV, /* 24 - DZ | IMP */
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FPE_FLTINV, /* 25 - INV | DZ | IMP */
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FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
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FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
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FPE_FLTOVF, /* 28 - OFL | IMP */
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FPE_FLTINV, /* 29 - INV | OFL | IMP */
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FPE_FLTUND, /* 2A - DNML | OFL | IMP */
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FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
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FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
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FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
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FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
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FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
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FPE_FLTUND, /* 30 - UFL | IMP */
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FPE_FLTINV, /* 31 - INV | UFL | IMP */
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FPE_FLTUND, /* 32 - DNML | UFL | IMP */
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FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
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FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
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FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
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FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
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FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
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FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
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FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
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FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
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FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
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FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
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FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
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FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
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FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
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FPE_FLTSUB, /* 40 - STK */
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FPE_FLTSUB, /* 41 - INV | STK */
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FPE_FLTUND, /* 42 - DNML | STK */
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FPE_FLTSUB, /* 43 - INV | DNML | STK */
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FPE_FLTDIV, /* 44 - DZ | STK */
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FPE_FLTSUB, /* 45 - INV | DZ | STK */
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FPE_FLTDIV, /* 46 - DNML | DZ | STK */
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FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
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FPE_FLTOVF, /* 48 - OFL | STK */
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FPE_FLTSUB, /* 49 - INV | OFL | STK */
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FPE_FLTUND, /* 4A - DNML | OFL | STK */
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FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
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FPE_FLTDIV, /* 4C - DZ | OFL | STK */
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FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
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FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
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FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
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FPE_FLTUND, /* 50 - UFL | STK */
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FPE_FLTSUB, /* 51 - INV | UFL | STK */
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FPE_FLTUND, /* 52 - DNML | UFL | STK */
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FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
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FPE_FLTDIV, /* 54 - DZ | UFL | STK */
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FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
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FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
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FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
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FPE_FLTOVF, /* 58 - OFL | UFL | STK */
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FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
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FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
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FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
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FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
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FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
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FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
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FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
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FPE_FLTRES, /* 60 - IMP | STK */
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FPE_FLTSUB, /* 61 - INV | IMP | STK */
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FPE_FLTUND, /* 62 - DNML | IMP | STK */
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FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
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FPE_FLTDIV, /* 64 - DZ | IMP | STK */
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FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
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FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
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FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
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FPE_FLTOVF, /* 68 - OFL | IMP | STK */
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FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
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FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
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FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
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FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
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FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
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FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
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FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
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FPE_FLTUND, /* 70 - UFL | IMP | STK */
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FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
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FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
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FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
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FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
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FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
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FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
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FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
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FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
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FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
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FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
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FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
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FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
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FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
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FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
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FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
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FPE_xxx32(0), FPE_xxx32(32), FPE_xxx32(64), FPE_xxx32(96)
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};
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#undef FPE_xxx1
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#undef FPE_xxx2
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#undef FPE_xxx4
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#undef FPE_xxx8
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#undef FPE_xxx16
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#undef FPE_xxx32
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/*
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* Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
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