Clean up the interrupt handling somewhat.
This commit is contained in:
briggs
parent
100623915b
commit
014b404127
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@ -1,4 +1,4 @@
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/* $NetBSD: mac68k5380.c,v 1.23 1996/05/05 06:16:51 briggs Exp $ */
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/* $NetBSD: mac68k5380.c,v 1.24 1996/05/25 16:42:24 briggs Exp $ */
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/*
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* Copyright (c) 1995 Allen Briggs
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@ -127,8 +127,9 @@ static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000;
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#define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)]
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#define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val))
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void ncr5380_irq_intr(void *);
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void ncr5380_drq_intr(void *);
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static void ncr5380_irq_intr(void *);
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static void ncr5380_drq_intr(void *);
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static void do_ncr5380_drq_intr __P((void *));
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static __inline__ void scsi_clr_ipend __P((void));
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static void scsi_mach_init __P((struct ncr_softc *sc));
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@ -144,6 +145,7 @@ scsi_clr_ipend()
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int tmp;
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tmp = GET_5380_REG(NCR5380_IRCV);
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scsi_clear_irq();
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}
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static void
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@ -162,10 +164,13 @@ scsi_mach_init(sc)
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ncr_5380_without_drq = (volatile u_char *)
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(SCSIBase + (u_int) ncr_5380_without_drq);
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if (VIA2 == VIA2OFF)
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if (VIA2 == VIA2OFF) {
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scsi_enable = Via1Base + VIA2 * 0x2000 + vIER;
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else
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scsi_flag = Via1Base + VIA2 * 0x2000 + vIFR;
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} else {
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scsi_enable = Via1Base + VIA2 * 0x2000 + rIER;
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scsi_flag = Via1Base + VIA2 * 0x2000 + rIFR;
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}
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mac68k_register_scsi_irq(ncr5380_irq_intr, sc);
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mac68k_register_scsi_drq(ncr5380_drq_intr, sc);
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@ -269,15 +274,6 @@ extern u_char ncr5380_no_parchk;
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PID("pdma_ready0");
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if (pdma_5380_dir) {
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PID("pdma_ready1.")
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/*
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* If Mr. IRQ isn't set one might wonder how we got
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* here. It does happen, though.
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*/
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dmstat = GET_5380_REG(NCR5380_DMSTAT);
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if (!(dmstat & SC_IRQ_SET)) {
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PID("pdma_ready2");
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return 0;
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}
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/*
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* For a phase mis-match, ATN is a "don't care," IRQ is 1 and
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* all other bits in the Bus & Status Register are 0. Also,
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@ -285,18 +281,19 @@ extern u_char ncr5380_no_parchk;
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* REQ. Since we're just checking that this interrupt isn't a
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* reselection or a reset, we just check for either.
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*/
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dmstat = GET_5380_REG(NCR5380_DMSTAT);
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idstat = GET_5380_REG(NCR5380_IDSTAT);
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if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET)
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&& ((idstat & (SC_S_BSY|SC_S_REQ))
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== (SC_S_BSY | SC_S_REQ)) ) {
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PID("pdma_ready3");
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PID("pdma_ready2");
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pdma_cleanup();
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return 1;
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} else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) {
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if (!(ncr5380_no_parchk & (1 << reqp->targ_id)))
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/* XXX: Should be parity error ???? */
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reqp->xs->error = XS_DRIVER_STUFFUP;
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PID("pdma_ready4");
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PID("pdma_ready3");
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/* XXX: is this the right reaction? */
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pdma_cleanup();
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return 1;
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@ -315,25 +312,24 @@ extern u_char ncr5380_no_parchk;
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panic("Spurious interrupt during PDMA xfer.\n");
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}
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} else
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PID("pdma_ready5");
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PID("pdma_ready4");
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#endif
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return 0;
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}
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void
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static void
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ncr5380_irq_intr(p)
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void *p;
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{
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PID("irq");
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#if USE_PDMA
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if (pdma_ready()) {
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return;
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}
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#endif
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if (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) {
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scsi_idisable();
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ncr_ctrl_intr(cur_softc);
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}
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scsi_idisable();
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ncr_ctrl_intr(cur_softc);
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}
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/*
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@ -351,8 +347,8 @@ ncr5380_irq_intr(p)
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* detect and handle the bus error for early termination of a command.
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* This is usually caused by a disconnecting target.
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*/
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void
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ncr5380_drq_intr(p)
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static void
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do_ncr5380_drq_intr(p)
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void *p;
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{
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#if USE_PDMA
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@ -361,35 +357,9 @@ extern int *nofault, mac68k_buserr_addr;
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register int count;
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volatile u_int32_t *long_drq;
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u_int32_t *long_data;
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volatile u_int8_t *drq;
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volatile u_int8_t *drq, tmp_data;
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u_int8_t *data;
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/*
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* If we're not ready to xfer data, just return.
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*/
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if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)
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|| !pdma_5380_dir) {
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PID("drq0");
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return;
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}
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/*
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* I don't think this should be necessary, but it is
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* for writes--at least to some devices. They don't
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* let go of PH_DATAOUT until we do pdma_cleanup().
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*/
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if (pending_5380_count == 0) {
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#if DBG_PID
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if (pdma_5380_dir == 2) {
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PID("drq1 (in)");
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} else {
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PID("drq1 (out)");
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}
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#endif
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pdma_cleanup();
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return;
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}
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#if DBG_PID
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if (pdma_5380_dir == 2) {
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PID("drq (in)");
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@ -420,8 +390,10 @@ extern int *nofault, mac68k_buserr_addr;
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pending_5380_data += count;
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pending_5380_count -= count;
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PID("end drq early");
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mac68k_buserr_addr = 0;
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PID("end drq early");
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return;
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}
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@ -456,31 +428,10 @@ extern int *nofault, mac68k_buserr_addr;
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long_data = (u_int32_t *) pending_5380_data;
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#define R4 *long_data++ = *long_drq++
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while ( count >= 512 ) {
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if (!(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)) {
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nofault = (int *) 0;
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pending_5380_data += (dcount - count);
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pending_5380_count -= (dcount - count);
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return;
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}
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while ( count >= 64 ) {
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */
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count -= 512;
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count -= 64;
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}
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while (count >= 4) {
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R4; count -= 4;
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@ -546,6 +497,14 @@ extern int *nofault, mac68k_buserr_addr;
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pending_5380_count -= dcount;
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pending_5380_data += dcount;
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}
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PID("write complete");
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drq = (volatile u_int8_t *) ncr_5380_with_drq;
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tmp_data = *drq;
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PID("read a byte?");
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nofault = (int *) 0;
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}
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/*
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@ -555,9 +514,23 @@ extern int *nofault, mac68k_buserr_addr;
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nofault = (int *) 0;
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PID("end drq");
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return;
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#else
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return;
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#endif /* if USE_PDMA */
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}
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static void
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ncr5380_drq_intr(p)
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void *p;
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{
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while (GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ) {
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do_ncr5380_drq_intr(p);
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scsi_clear_drq();
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}
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}
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#if USE_PDMA
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#define SCSI_TIMEOUT_VAL 10000000
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@ -1,4 +1,4 @@
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/* $NetBSD: ncr5380var.h,v 1.1 1996/05/05 06:17:00 briggs Exp $ */
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/* $NetBSD: ncr5380var.h,v 1.2 1996/05/25 16:42:31 briggs Exp $ */
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/*
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* Copyright (c) 1995 Allen Briggs. All rights reserved.
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@ -29,7 +29,28 @@
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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static volatile u_char *scsi_enable = NULL;
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static volatile u_char *scsi_enable = NULL;
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static volatile u_char *scsi_flag = NULL;
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static __inline__ void
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scsi_clear_drq __P((void))
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{
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int s;
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s = splhigh();
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*scsi_flag = 0x80 | V2IF_SCSIDRQ;
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splx(s);
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}
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static __inline__ void
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scsi_clear_irq __P((void))
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{
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int s;
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s = splhigh();
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*scsi_flag = 0x80 | V2IF_SCSIIRQ;
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splx(s);
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}
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static __inline__ void
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scsi_ienable __P((void))
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@ -53,7 +74,5 @@ scsi_idisable __P((void))
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void pdma_stat __P((void));
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void pdma_cleanup __P((void));
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void ncr5380_irq_intr __P((void *p));
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void ncr5380_drq_intr __P((void *p));
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void scsi_show __P((void));
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