sun4 cpu types are determined by the idprom.
cache type is determined by the model number.
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@ -42,7 +42,7 @@
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* @(#)cpu.c 8.1 (Berkeley) 6/11/93
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*
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* from: Header: cpu.c,v 1.12 93/05/03 09:47:57 torek Exp (LBL)
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* $Id: cpu.c,v 1.7 1994/05/19 07:12:49 deraadt Exp $
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* $Id: cpu.c,v 1.8 1994/08/20 01:32:45 deraadt Exp $
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*/
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#include <sys/param.h>
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@ -52,9 +52,14 @@
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#include <machine/cpu.h>
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#include <machine/reg.h>
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#include <machine/trap.h>
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#include <machine/idprom.h>
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#include <sparc/sparc/cache.h>
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#ifdef SUN4
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extern struct idprom idprom;
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#endif
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/* This is declared here so that you must include a CPU for the cache code. */
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struct cacheinfo cacheinfo;
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@ -110,7 +115,7 @@ cpu_attach(parent, dev, aux)
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struct device *dev;
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void *aux;
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{
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register int node, clk, i, l;
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register int node, clk, bug = 0, i, l;
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register int impl, vers, fver;
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register char *fpuname;
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struct fpstate fpstate;
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@ -139,40 +144,83 @@ cpu_attach(parent, dev, aux)
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/* tell them what we have */
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node = ((struct romaux *)aux)->ra_node;
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clk = getpropint(node, "clock-frequency", 0);
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sprintf(cpu_model, "%s (%s @ %s MHz, %s FPU)",
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getpropstring(node, "name"),
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psrtoname(impl, vers, fver, iubuf), clockfreq(clk), fpuname);
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printf(": %s\n", cpu_model);
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#ifdef SUN4
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if (cputyp == CPU_SUN4) {
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clk = 0;
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vactype = VAC_WRITEBACK;
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switch (idprom.id_machine) {
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case SUN4_100:
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sprintf(cpu_model,"SUN-4/100 series (%s FPU)", fpuname);
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cacheinfo.c_totalsize = 0;
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cacheinfo.c_hwflush = 0;
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cacheinfo.c_linesize = 0;
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cacheinfo.c_l2linesize = 0;
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break;
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case SUN4_200:
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sprintf(cpu_model,"SUN-4/200 series (%s FPU)", fpuname);
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cacheinfo.c_totalsize = 128*1024;
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cacheinfo.c_hwflush = 0;
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cacheinfo.c_linesize = 16;
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cacheinfo.c_l2linesize = 4;
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break;
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case SUN4_300:
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sprintf(cpu_model,"SUN-4/300 series (%s FPU)", fpuname);
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bug = 1;
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cacheinfo.c_totalsize = 128*1024;
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cacheinfo.c_hwflush = 0;
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cacheinfo.c_linesize = 16;
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cacheinfo.c_l2linesize = 4;
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break;
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case SUN4_400:
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sprintf(cpu_model,"SUN-4/400 series (%s FPU)", fpuname);
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cacheinfo.c_totalsize = 128 * 1024;
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cacheinfo.c_hwflush = 0;
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cacheinfo.c_linesize = 32;
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cacheinfo.c_l2linesize = 5;
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break;
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}
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printf(": %s\n", cpu_model);
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}
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#endif
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#if defined(SUN4C) || defined(SUN4M)
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if (cputyp == CPU_SUN4C || cputyp == CPU_SUN4M) {
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clk = getpropint(node, "clock-frequency", 0);
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sprintf(cpu_model, "%s (%s @ %s MHz, %s FPU)",
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getpropstring(node, "name"),
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psrtoname(impl, vers, fver, iubuf), clockfreq(clk), fpuname);
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printf(": %s\n", cpu_model);
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/*
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* Fill in the cache info. Note, vac-hwflush is spelled
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* with an underscore on 4/75s.
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*/
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cacheinfo.c_totalsize = getpropint(node, "vac-size", 65536);
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cacheinfo.c_hwflush = getpropint(node, "vac_hwflush", 0) |
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getpropint(node, "vac-hwflush", 0);
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cacheinfo.c_linesize = l = getpropint(node, "vac-linesize", 16);
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for (i = 0; (1 << i) < l; i++)
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/* void */;
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if ((1 << i) != l)
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panic("bad cache line size %d", l);
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cacheinfo.c_l2linesize = i;
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vactype = VAC_WRITETHROUGH;
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/*
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* Fill in the cache info. Note, vac-hwflush is spelled
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* with an underscore on 4/75s.
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*/
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cacheinfo.c_totalsize = getpropint(node, "vac-size", 65536);
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cacheinfo.c_hwflush = getpropint(node, "vac_hwflush", 0) |
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getpropint(node, "vac-hwflush", 0);
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cacheinfo.c_linesize = l = getpropint(node, "vac-linesize", 16);
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for (i = 0; (1 << i) < l; i++)
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/* void */;
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if ((1 << i) != l)
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panic("bad cache line size %d", l);
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cacheinfo.c_l2linesize = i;
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vactype = VAC_WRITETHROUGH;
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/*
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* Machines with "buserr-type" 1 have a bug in the cache
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* chip that affects traps. (I wish I knew more about this
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* mysterious buserr-type variable....)
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*/
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if (getpropint(node, "buserr-type", 0) == 1) {
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/*
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* Machines with "buserr-type" 1 have a bug in the cache
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* chip that affects traps. (I wish I knew more about this
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* mysterious buserr-type variable....)
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*/
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bug = (getpropint(node, "buserr-type", 0) == 1);
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}
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#endif /* SUN4C || SUN4M */
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if (bug) {
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kvm_uncache((caddr_t)trapbase, 1);
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printf("%s: cache chip bug; trap page uncached\n",
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dev->dv_xname);
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}
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printf("%s: %d byte write-through, %d bytes/line, %cw flush ",
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dev->dv_xname, cacheinfo.c_totalsize, l,
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dev->dv_xname, cacheinfo.c_totalsize, cacheinfo.c_linesize,
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cacheinfo.c_hwflush ? 'h' : 's');
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cache_enable();
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}
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