Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added support for m68060 (activate with -m68060). This change has

Browse Source 
already been accepted and integrated into the FSF source tree.
This commit is contained in:
jtc 1996-02-19 21:26:53 +00:00
parent ada953057b
commit 00a38a0584
2 changed files with 41 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
gnu/usr.bin/gcc/arch/m68k/m68k.h
View File

@ -90,9 +90,17 @@ extern int target_flags;
run on a 68030 and 68881/2. */
#define TARGET_68040 (target_flags & 01400)
/* Use the 68040-only fp instructions (-m68040). */
/* Use the 68040-only fp instructions (-m68040 or -m68060). */
#define TARGET_68040_ONLY (target_flags & 01000)
/* Optimize for 68060, but still allow execution on 68020
(-m68060).
The 68060 will execute all 68030 and 68881/2 instructions, but some
of them must be emulated in software by the OS. When TARGET_68060 is
turned on, these instructions won't be used. This code will still
run on a 68030 and 68881/2. */
#define TARGET_68060 (target_flags & 02000)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
@ -100,15 +108,15 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "68020", -01400}, \
{ "c68020", -01400}, \
{ { "68020", -03400}, \
{ "c68020", -03400}, \
{ "68020", 5}, \
{ "c68020", 5}, \
{ "68881", 2}, \
{ "bitfield", 4}, \
{ "68000", -01405}, \
{ "c68000", -01405}, \
{ "soft-float", -01102}, \
{ "68000", -03405}, \
{ "c68000", -03405}, \
{ "soft-float", -03102}, \
{ "nobitfield", -4}, \
{ "rtd", 8}, \
{ "nortd", -8}, \
@ -119,9 +127,10 @@ extern int target_flags;
{ "sky", 0200}, \
{ "nosky", -0200}, \
{ "68020-40", 0407}, \
{ "68030", -01400}, \
{ "68030", -03400}, \
{ "68030", 5}, \
{ "68040", 01007}, \
{ "68060", 03007}, \
{ "68851", 0}, /* Affects *_SPEC and/or GAS. */ \
{ "no-68851", 0}, /* Affects *_SPEC and/or GAS. */ \
{ "68302", 0}, /* Affects *_SPEC and/or GAS. */ \

40
gnu/usr.bin/gcc/arch/m68k/m68k.md
View File

@ -92,6 +92,16 @@
;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
;;- than "".
;;- Information about 68060 port.
;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
;;- be emulated in software by the OS. It is faster to avoid these
;;- instructions and issue a library call rather than trapping into
;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq, fintrz;
;;- and fscale. The TARGET_68060 flag turns the use of the opcodes
;;- off.
;;- FPA port explanation:
@ -1906,7 +1916,7 @@
(define_insn "ftruncdf2"
[(set (match_operand:DF 0 "general_operand" "=f")
(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
"TARGET_68881 && !TARGET_68040"
"TARGET_68881 && !TARGET_68040 && !TARGET_68060"
"*
{
if (FP_REG_P (operands[1]))
@ -1917,7 +1927,7 @@
(define_insn "ftruncsf2"
[(set (match_operand:SF 0 "general_operand" "=f")
(fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
"TARGET_68881 && !TARGET_68040"
"TARGET_68881 && !TARGET_68040 && !TARGET_68060"
"*
{
if (FP_REG_P (operands[1]))
@ -2939,7 +2949,7 @@
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
(const_int 32))))])]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"")
(define_insn ""
@ -2950,7 +2960,7 @@
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
(const_int 32))))]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"mulu%.l %2,%3:%0")
; Match immediate case. For 2.4 only match things < 2^31.
@ -2965,7 +2975,7 @@
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(match_dup 2))
(const_int 32))))]
"TARGET_68020
"TARGET_68020 && !TARGET_68060
&& (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
"mulu%.l %2,%3:%0")
@ -2978,7 +2988,7 @@
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
(const_int 32))))])]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"")
(define_insn ""
@ -2989,7 +2999,7 @@
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
(const_int 32))))]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"muls%.l %2,%3:%0")
(define_insn ""
@ -3000,7 +3010,7 @@
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(match_dup 2))
(const_int 32))))]
"TARGET_68020
"TARGET_68020 && !TARGET_68060
/* This test is a noop on 32 bit machines,
but important for a cross-compiler hosted on 64-bit machines. */
&& INTVAL (operands[2]) <= 0x7fffffff
@ -3016,7 +3026,7 @@
(zero_extend:DI (match_operand:SI 2 "general_operand" "")))
(const_int 32))))
(clobber (match_dup 3))])]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"
{
operands[3] = gen_reg_rtx (SImode);
@ -3040,7 +3050,7 @@
(zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"mulu%.l %3,%0:%1")
(define_insn "const_umulsi3_highpart"
@ -3051,7 +3061,7 @@
(match_operand 3 "const_uint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"mulu%.l %3,%0:%1")
(define_expand "smulsi3_highpart"
@ -3063,7 +3073,7 @@
(sign_extend:DI (match_operand:SI 2 "general_operand" "")))
(const_int 32))))
(clobber (match_dup 3))])]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"
{
operands[3] = gen_reg_rtx (SImode);
@ -3087,7 +3097,7 @@
(sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"muls%.l %3,%0:%1")
(define_insn "const_smulsi3_highpart"
@ -3098,7 +3108,7 @@
(match_operand 3 "const_sint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020"
"TARGET_68020 && !TARGET_68060"
"muls%.l %3,%0:%1")
(define_expand "muldf3"
@ -3155,7 +3165,7 @@
"*
{
if (GET_CODE (operands[2]) == CONST_DOUBLE
&& floating_exact_log2 (operands[2]) && !TARGET_68040)
&& floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
{
int i = floating_exact_log2 (operands[2]);
operands[2] = gen_rtx (CONST_INT, VOIDmode, i);