Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code. Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by comparison to the OpenBSD 2.1 codebase of Soda's ARC port. Open issues: * Still no support for r4600 or mipsIV CPUs with two-way L1 cache. Code derived from Per Fogelstrom's OpenBSD source doesn't work on mips3 pmaxes with L2 cache. * Still some port-specific #ifdefs, for interrupt enable and pmax L2 cache-size. Needs more thought, but overlaps with work-in-progress by Tohru and Tsubai on spl()s and related stuff.
This commit is contained in:
jonathan
parent
d90bb7796e
commit
008816ea4f
@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.24 1998/02/25 23:25:16 thorpej Exp $ */
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/* $NetBSD: cpu.h,v 1.25 1998/09/11 16:46:31 jonathan Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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@ -141,8 +141,18 @@ struct clockframe {
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#define aston() (astpending = 1)
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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extern int astpending; /* need to trap before returning to user mode */
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extern int want_resched; /* resched() was called */
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#ifdef MIPS3
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extern u_int mips_L2CacheSize;
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extern int mips_L2CacheIsSnooping; /* L2 cache snoops uncached writes ? */
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extern int mips_L2CacheMixed;
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#ifdef MIPS3_INTERNAL_TIMER_INTERRUPT
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extern u_int32_t mips3_intr_cycle_count;
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extern u_int32_t mips3_timer_delta;
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#endif
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#endif
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/*
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* CTL_MACHDEP definitions.
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@ -158,6 +168,7 @@ int want_resched; /* resched() was called */
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/*
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* Misc prototypes.
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*/
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struct user;
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caddr_t allocsys __P((caddr_t));
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@ -166,6 +177,13 @@ int savectx __P((struct user *));
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void mips_init_msgbuf __P((void));
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void mips_init_proc0 __P((caddr_t));
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/* locore.S */
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extern void savefpregs __P((struct proc *));
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/* mips_machdep.c */
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extern void cpu_identify __P((void));
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extern void mips_vector_init __P((void));
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/*
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* MIPS CPU types (cp_imp).
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*/
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@ -178,13 +196,20 @@ void mips_init_proc0 __P((caddr_t));
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#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
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#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
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#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
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#define MIPS_UNKC1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
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#define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based CPU ISA I */
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/* ID conflict */
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#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
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#define MIPS_R3SONY MIPS_R4700 /* Sony R3000 CPU ISA I CLASH */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
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#define MIPS_R3NKK 0x23 /* NKK R3000 based CPU ISA I */
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/* ID conflict */
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#define MIPS_R5000 0x23 /* MIPS R5000 based CPU ISA IV */
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#define MIPS_R3NKK MIPS_R5000 /* NKK R3000 based CPU ISA I CLASH */
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#define MIPS_RM5230 0x28 /* QED RM5230 based CPU ISA IV */
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/*
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@ -202,9 +227,13 @@ void mips_init_proc0 __P((caddr_t));
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#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
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#define MIPS_R3SONY MIPS_R4700 /* Sony R3000 based FPU ISA I */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
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#define MIPS_R3NKK 0x23 /* NKK R3000 based FPU ISA I */
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/* ID conflict */
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#define MIPS_R3NKK MIPS_R5000 /* NKK R3000 based CPU ISA I CLASH */
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#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
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#define MIPS_RM5230 0x28 /* QED RM5230 based FPU ISA IV */
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuregs.h,v 1.14 1998/04/23 10:32:08 jonathan Exp $ */
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/* $NetBSD: cpuregs.h,v 1.15 1998/09/11 16:46:31 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -212,11 +212,6 @@
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#define MIPS3_SR_ERL 0x00000004
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#define MIPS3_SR_EXL 0x00000002
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/* backwards compatibility with names used in Pica port */
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#define MIPS_SR_RP MIPS3_SR_RP
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#define MIPS_SR_FR_32 MIPS3_SR_FR_32
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#define MIPS_SR_RE MIPS3_SR_RE
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#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
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#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
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#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
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@ -277,6 +272,76 @@
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#define MIPS3_CNTXT_PTE_BASE 0xFF800000
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#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
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/*
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* The bits in the MIPS3 config register.
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*
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* bit 0..5: R/W, Bit 6..31: R/O
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*/
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/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
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#define MIPS3_CONFIG_K0_MASK 0x00000007
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/*
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* R/W Update on Store Conditional
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* 0: Store Conditional uses coherency algorithm specified by TLB
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* 1: Store Conditional uses cacheable coherent update on write
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*/
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#define MIPS3_CONFIG_CU 0x00000008
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#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
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#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
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#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
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(((config) & (bit)) ? 0x10 : 0x20)
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#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
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#define MIPS3_CONFIG_DC_SHIFT 6
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#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
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#define MIPS3_CONFIG_IC_SHIFT 9
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
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(0x1000 << (((config) & (mask)) >> (shift)))
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/* Block ordering: 0: sequential, 1: sub-block */
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#define MIPS3_CONFIG_EB 0x00002000
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/* ECC mode - 0: ECC mode, 1: parity mode */
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#define MIPS3_CONFIG_EM 0x00004000
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/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
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#define MIPS3_CONFIG_BE 0x00008000
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/* Dirty Shared coherency state - 0: enabled, 1: disabled */
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#define MIPS3_CONFIG_SM 0x00010000
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/* Secondary Cache - 0: present, 1: not present */
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#define MIPS3_CONFIG_SC 0x00020000
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/* System Port width - 0: 64-bit, 1,2,3: reserved */
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#define MIPS3_CONFIG_EW_MASK 0x000c0000
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#define MIPS3_CONFIG_EW_SHIFT 18
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/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
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#define MIPS3_CONFIG_SW 0x00100000
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/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
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#define MIPS3_CONFIG_SS 0x00200000
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/* Secondary Cache line size */
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#define MIPS3_CONFIG_SB_MASK 0x00c00000
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#define MIPS3_CONFIG_SB_SHIFT 22
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#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
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(0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
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/* write back data rate */
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#define MIPS3_CONFIG_EP_MASK 0x0f000000
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#define MIPS3_CONFIG_EP_SHIFT 24
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/* System clock ratio - this value is CPU dependent */
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#define MIPS3_CONFIG_EC_MASK 0x70000000
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#define MIPS3_CONFIG_EC_SHIFT 28
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/* Master-Checker Mode - 1: enabled */
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#define MIPS3_CONFIG_CM 0x80000000
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/*
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* Location of exception vectors.
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*
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@ -437,11 +502,30 @@
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#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
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#define MIPS3_TLB_PF_NUM 0x3fffffc0
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#define MIPS3_TLB_ATTR_MASK 0x00000038
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#define MIPS3_TLB_MOD_BIT 0x00000004
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#define MIPS3_TLB_VALID_BIT 0x00000002
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#define MIPS3_TLB_GLOBAL_BIT 0x00000001
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/*
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* MIPS3_TLB_ATTR values - coherency algorithm:
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* 0: cacheable, noncoherent, write-through, no write allocate
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* 1: cacheable, noncoherent, write-through, write allocate
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* 2: uncached
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* 3: cacheable, noncoherent, write-back (noncoherent)
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* 4: cacheable, coherent, write-back, exclusive (exclusive)
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* 5: cacheable, coherent, write-back, exclusive on write (sharable)
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* 6: cacheable, coherent, write-back, update on write (update)
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* 7: cacheable, ?, ?, ?, ?
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*/
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#define MIPS3_TLB_ATTR_WT 0 /* IDT */
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#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
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#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
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#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
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#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
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#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
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#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
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/*
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* The high part of the TLB entry.
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#define MIPS1_TLB_FIRST_RAND_ENTRY 8
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#define MIPS3_TLB_NUM_TLB_ENTRIES 48
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#define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32
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#define MIPS3_TLB_WIRED_ENTRIES 8
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.h,v 1.13 1998/04/23 10:31:02 jonathan Exp $ */
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/* $NetBSD: locore.h,v 1.14 1998/09/11 16:46:31 jonathan Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* only to print them by name in stack tracebacks
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*/
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/* Block out one hardware interrupt-enable bit. */
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extern int Mach_spl0 __P((void)), Mach_spl1 __P((void));
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extern int Mach_spl2 __P((void)), Mach_spl3 __P((void));
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extern int Mach_spl4 __P((void)), Mach_spl5 __P((void));
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/* Block out nested interrupt-enable bits. */
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extern int cpu_spl0 __P((void)), cpu_spl1 __P((void));
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extern int cpu_spl2 __P((void)), cpu_spl3 __P((void));
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extern int cpu_spl4 __P((void)), cpu_spl5 __P((void));
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extern int splhigh __P((void));
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extern u_int32_t mips_read_causereg __P((void));
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extern u_int32_t mips_read_statusreg __P((void));
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extern void mips1_ConfigCache __P((void));
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extern void mips1_FlushCache __P((void));
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extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips1_ForceCacheUpdate __P((void));
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extern void mips1_SetPID __P((int pid));
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extern void mips1_TLBFlush __P((void));
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extern void mips1_TLBFlush __P((int numtlb));
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extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */
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(vm_offset_t addr));
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extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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@ -72,11 +86,13 @@ extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips3_ForceCacheUpdate __P((void));
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extern void mips3_HitFlushDCache __P((vm_offset_t, int));
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extern void mips3_SetPID __P((int pid));
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extern void mips3_TLBFlush __P((void));
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extern void mips3_TLBFlush __P((int numtlb));
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extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */
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(vm_offset_t addr));
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extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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extern void mips3_TLBWriteIndexedVPS __P((u_int index, void *tlb));
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struct tlb;
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extern void mips3_TLBRead __P((int, struct tlb *));
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extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb));
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extern void mips3_TLBWriteIndexed __P((u_int index, u_int high,
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u_int lo0, u_int lo1));
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extern void mips3_wbflush __P((void));
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@ -86,6 +102,10 @@ extern void mips3_cpu_switch_resume __P((void));
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extern void mips3_SetWIRED __P((int));
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extern u_int32_t mips3_cycle_count __P((void));
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extern u_int32_t mips3_read_compare __P((void));
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extern u_int32_t mips3_read_config __P((void));
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extern void mips3_write_compare __P((u_int32_t));
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/*
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* A vector with an entry for each mips-ISA-level dependent
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@ -100,7 +120,7 @@ typedef struct {
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void (*flushICache) __P((vm_offset_t addr, vm_offset_t len));
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void (*forceCacheUpdate) __P((void));
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void (*setTLBpid) __P((int pid));
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void (*tlbFlush) __P((void));
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void (*tlbFlush) __P((int numtlb));
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void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */
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int (*tlbUpdate) __P((u_int highreg, u_int lowreg));
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void (*wbflush) __P((void));
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@ -128,7 +148,7 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
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#define MachFlushICache mips3_FlushICache
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#define MachForceCacheUpdate mips3_ForceCacheUpdate
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#define MachSetPID mips3_SetPID
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#define MachTLBFlush mips3_TLBFlush
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#define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries)
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#define MachTLBFlushAddr mips3_TLBFlushAddr
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#define MachTLBUpdate mips3_TLBUpdate
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#define wbflush mips3_wbflush
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@ -143,7 +163,7 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
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#define MachFlushICache mips1_FlushICache
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#define MachForceCacheUpdate mips1_ForceCacheUpdate
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#define MachSetPID mips1_SetPID
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#define MachTLBFlush mips1_TLBFlush
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#define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES)
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#define MachTLBFlushAddr mips1_TLBFlushAddr
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#define MachTLBUpdate mips1_TLBUpdate
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#define wbflush mips1_wbflush
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@ -160,7 +180,7 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
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#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
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#define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate))
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#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
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#define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush))
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#define MachTLBFlush() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries)
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#define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr))
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#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
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#define wbflush (*(mips_locore_jumpvec.wbflush))
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@ -201,14 +221,21 @@ union cpuprid {
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extern union cpuprid cpu_id;
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extern union cpuprid fpu_id;
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extern int cpu_arch;
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extern u_int mips_L1DataCacheSize;
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extern u_int mips_L1InstCacheSize;
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extern u_int mips_L1DataCacheLSize;
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extern u_int mips_L1InstCacheLSize;
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extern u_int mips_L2CacheSize;
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extern int mips_num_tlb_entries;
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extern u_int mips_L1DCacheSize;
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extern u_int mips_L1ICacheSize;
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extern u_int mips_L1DCacheLSize;
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extern u_int mips_L1ICacheLSize;
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extern int mips_L2CachePresent;
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extern u_int mips_L2CacheLSize;
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extern u_int mips_CacheAliasMask;
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extern struct intr_tab intr_tab[];
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#ifdef MIPS3
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extern int mips3_L1TwoWayCache;
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extern int mips3_cacheflush_bug;
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#endif /* MIPS3 */
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#endif
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#endif /* _MIPS_LOCORE_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: mips3_pte.h,v 1.7 1997/06/16 23:41:44 jonathan Exp $ */
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/* $NetBSD: mips3_pte.h,v 1.8 1998/09/11 16:46:31 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -108,7 +108,9 @@ struct tlb {
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/* pte accessor macros */
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#define mips3_pfn_is_ext(x) ((x) & 0x3c000000)
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#define mips3_vad_to_pfn(x) (((unsigned)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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#define mips3_vad_to_pfn64(x) (((quad_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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#define mips3_pfn_to_vad(x) (((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
|
||||
#define mips3_vad_to_vpn(x) ((unsigned)(x) & MIPS3_PG_SVPN)
|
||||
#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: mips_param.h,v 1.9 1998/08/25 01:55:38 nisimura Exp $ */
|
||||
/* $NetBSD: mips_param.h,v 1.10 1998/09/11 16:46:31 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Architecture name.
|
||||
@ -29,6 +29,12 @@
|
||||
* Round p (pointer or byte index) up to a correctly-aligned value for all
|
||||
* data types (int, long, ...). The result is u_int and must be cast to
|
||||
* any desired pointer type.
|
||||
*
|
||||
* ALIGNED_POINTER is a boolean macro that checks whether an address
|
||||
* is valid to fetch data elements of type t from on this architecture.
|
||||
* This does not reflect the optimal alignment, just the possibility
|
||||
* (within reasonable limits).
|
||||
*
|
||||
*/
|
||||
#define ALIGNBYTES 7
|
||||
#define ALIGN(p) (((u_int)(p) + ALIGNBYTES) & ~ALIGNBYTES)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: profile.h,v 1.11 1997/11/05 04:02:26 thorpej Exp $ */
|
||||
/* $NetBSD: profile.h,v 1.12 1998/09/11 16:46:31 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -42,29 +42,35 @@
|
||||
#define _MIPS_PROFILE_H_
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
/*
|
||||
* Declare non-profiled _splhigh() /_splx() entrypoints for _mcount.
|
||||
* see MCOUNT_ENTER and MCOUNT_EXIT.
|
||||
*/
|
||||
#define _KERNEL_MCOUNT_DECL \
|
||||
extern int _splhigh __P((void)); extern int _splx __P((int));
|
||||
|
||||
#else /* !_KERNEL */
|
||||
|
||||
/* Make __mcount static. */
|
||||
#define _KERNEL_MCOUNT_DECL static
|
||||
#endif /* !_KERNEL */
|
||||
|
||||
#ifdef _KERNEL
|
||||
# define _PROF_CPLOAD ""
|
||||
#else
|
||||
# define _PROF_CPLOAD ".cpload $25;"
|
||||
#endif
|
||||
|
||||
|
||||
#define _MCOUNT_DECL \
|
||||
_KERNEL_MCOUNT_DECL \
|
||||
void __attribute__((unused)) __mcount
|
||||
|
||||
#define MCOUNT \
|
||||
__asm__(".globl _mcount;" \
|
||||
".type _mcount,@function;" \
|
||||
"_mcount:;" \
|
||||
".set noreorder;" \
|
||||
".set noat;" \
|
||||
_PROF_CPLOAD \
|
||||
"sw $4,8($29);" \
|
||||
"sw $5,12($29);" \
|
||||
"sw $6,16($29);" \
|
||||
@ -90,7 +96,7 @@
|
||||
/*
|
||||
* The following two macros do splhigh and splx respectively.
|
||||
* They have to be defined this way because these are real
|
||||
* functions on the PMAX, and we do not want to invoke mcount
|
||||
* functions on the MIPS, and we do not want to invoke mcount
|
||||
* recursively.
|
||||
*/
|
||||
#define MCOUNT_ENTER s = _splhigh()
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: psl.h,v 1.8 1997/06/22 07:42:52 jonathan Exp $ */
|
||||
/* $NetBSD: psl.h,v 1.9 1998/09/11 16:46:32 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -135,13 +135,13 @@
|
||||
|
||||
#if MIPS3 + MIPS1 > 1
|
||||
# define PSL_LOWIPL \
|
||||
((cpu_arch == 3) ? MIPS3_PSL_LOWIPL : MIPS1_PSL_LOWIPL)
|
||||
(CPUISMIPS3 ? MIPS3_PSL_LOWIPL : MIPS1_PSL_LOWIPL)
|
||||
#define PSL_USERSET \
|
||||
((cpu_arch == 3) ? MIPS3_PSL_USERSET : MIPS1_PSL_USERSET)
|
||||
(CPUISMIPS3 ? MIPS3_PSL_USERSET : MIPS1_PSL_USERSET)
|
||||
# define PSL_USRCLR \
|
||||
((cpu_arch == 3) ? MIPS3_PSL_USRCLR : MIPS1_PSL_USRCLR)
|
||||
(CPUISMIPS3 ? MIPS3_PSL_USRCLR : MIPS1_PSL_USRCLR)
|
||||
# define USERMODE(ps) \
|
||||
((cpu_arch == 3) ? MIPS3_USERMODE(ps) : MIPS1_USERMODE(ps))
|
||||
(CPUISMIPS3 ? MIPS3_USERMODE(ps) : MIPS1_USERMODE(ps))
|
||||
# define BASEPRI(ps) \
|
||||
((cpu_arch == 3) ? MIPS3_BASEPRI(ps) : MIPS1_BASEPRI(ps))
|
||||
(CPUISMIPS3 ? MIPS3_BASEPRI(ps) : MIPS1_BASEPRI(ps))
|
||||
#endif
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: stdarg.h,v 1.12 1998/07/27 13:55:33 mycroft Exp $ */
|
||||
/* $NetBSD: stdarg.h,v 1.13 1998/09/11 16:46:32 jonathan Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -35,8 +35,8 @@
|
||||
* @(#)stdarg.h 8.1 (Berkeley) 6/10/93
|
||||
*/
|
||||
|
||||
#ifndef _PMAX_STDARG_H_
|
||||
#define _PMAX_STDARG_H_
|
||||
#ifndef _MIPS_STDARG_H_
|
||||
#define _MIPS_STDARG_H_
|
||||
|
||||
#include <machine/ansi.h>
|
||||
|
||||
@ -61,4 +61,4 @@ typedef _BSD_VA_LIST_ va_list;
|
||||
|
||||
#define va_end(ap)
|
||||
|
||||
#endif /* !_PMAX_STDARG_H_ */
|
||||
#endif /* !_MIPS_STDARG_H_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: varargs.h,v 1.14 1998/07/27 13:55:34 mycroft Exp $ */
|
||||
/* $NetBSD: varargs.h,v 1.15 1998/09/11 16:46:32 jonathan Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -40,8 +40,8 @@
|
||||
* @(#)varargs.h 8.2 (Berkeley) 3/22/94
|
||||
*/
|
||||
|
||||
#ifndef _PMAX_VARARGS_H_
|
||||
#define _PMAX_VARARGS_H_
|
||||
#ifndef _MIPS_VARARGS_H_
|
||||
#define _MIPS_VARARGS_H_
|
||||
|
||||
#include <machine/ansi.h>
|
||||
|
||||
@ -65,4 +65,4 @@ typedef _BSD_VA_LIST_ va_list;
|
||||
|
||||
#define va_end(ap)
|
||||
|
||||
#endif /* !_PMAX_VARARGS_H_ */
|
||||
#endif /* !_MIPS_VARARGS_H_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore.S,v 1.54 1998/08/25 01:55:39 nisimura Exp $ */
|
||||
/* $NetBSD: locore.S,v 1.55 1998/09/11 16:46:32 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -122,7 +122,7 @@
|
||||
*
|
||||
* XXX we don't restore all the regs, because the r3000 and r4000
|
||||
* use different mechanisms to set up the return address.
|
||||
* the current Pica code uses v1 for that, so we leave
|
||||
* the current Arc code uses v1 for that, so we leave
|
||||
* it up to the caller of this macro to restore AT and v0.
|
||||
* Don't ask why, I don't know.
|
||||
*/
|
||||
@ -163,7 +163,7 @@
|
||||
*
|
||||
* XXX we don't restore all the regs, because the r3000 and r4000
|
||||
* use different mechanisms to set up the return address.
|
||||
* the current Pica code uses v1 for that, so we leave
|
||||
* the current Arc code uses v1 for that, so we leave
|
||||
* it up to the caller of this macro to restore AT and v0.
|
||||
* Don't ask why, I don't konw.
|
||||
*/
|
||||
@ -207,6 +207,9 @@
|
||||
start:
|
||||
_C_LABEL(kernel_text):
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
|
||||
#ifdef arc /* XXX */
|
||||
mtc0 zero, MIPS_COP_0_CAUSE_REG # Clear soft interrupts
|
||||
#endif
|
||||
/*
|
||||
* Initialize stack and call machine startup.
|
||||
*/
|
||||
@ -445,6 +448,15 @@ nomatch:
|
||||
li v0, 1
|
||||
END(bcmp)
|
||||
|
||||
/*
|
||||
* memcpy(to, from, len)
|
||||
* {ov}bcopy(from, to, len)
|
||||
*/
|
||||
ALEAF(memcpy)
|
||||
move v0, a0 # swap from and to
|
||||
move a0, a1
|
||||
move a1, v0
|
||||
|
||||
/*
|
||||
* {ov}bcopy(from, to, len)
|
||||
*/
|
||||
@ -583,6 +595,8 @@ backcopy:
|
||||
nop
|
||||
|
||||
.set at
|
||||
.globl _C_LABEL(bcopy_end)
|
||||
_C_LABEL(bcopy_end):
|
||||
END(bcopy)
|
||||
|
||||
/*
|
||||
@ -683,6 +697,8 @@ LEAF(idle)
|
||||
nop
|
||||
b sw1
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable all interrupts
|
||||
.globl _C_LABEL(idle_end)
|
||||
_C_LABEL(idle_end):
|
||||
END(idle)
|
||||
|
||||
/*
|
||||
@ -774,6 +790,8 @@ sw1:
|
||||
sw a0, _C_LABEL(curpcb) # set curpcb
|
||||
jr s1 # CPU-specific: resume process
|
||||
move a3, v0 # BDSLOT: a3 = TLB PID
|
||||
.globl _C_LABEL(cpu_switch_end)
|
||||
_C_LABEL(cpu_switch_end):
|
||||
END(cpu_switch)
|
||||
|
||||
/*
|
||||
@ -1280,6 +1298,13 @@ NLEAF(mips_read_causereg)
|
||||
nop
|
||||
END(mips_read_causereg)
|
||||
|
||||
#if defined(DEBUG)
|
||||
NLEAF(mips_read_statusreg)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG
|
||||
j ra
|
||||
nop
|
||||
END(mips_read_causereg)
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
@ -1690,28 +1715,28 @@ _C_LABEL(fpu_id):
|
||||
_C_LABEL(cpu_arch):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_L1DataCacheSize)
|
||||
_C_LABEL(mips_L1DataCacheSize):
|
||||
.globl _C_LABEL(mips_L1DCacheSize)
|
||||
_C_LABEL(mips_L1DCacheSize):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_L1InstCacheSize)
|
||||
_C_LABEL(mips_L1InstCacheSize):
|
||||
.globl _C_LABEL(mips_L1ICacheSize)
|
||||
_C_LABEL(mips_L1ICacheSize):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_L1DataCacheLSize)
|
||||
_C_LABEL(mips_L1DataCacheLSize):
|
||||
.globl _C_LABEL(mips_L1DCacheLSize)
|
||||
_C_LABEL(mips_L1DCacheLSize):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_L1InstCacheLSize)
|
||||
_C_LABEL(mips_L1InstCacheLSize):
|
||||
.globl _C_LABEL(mips_L1ICacheLSize)
|
||||
_C_LABEL(mips_L1ICacheLSize):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_CacheAliasMask)
|
||||
_C_LABEL(mips_CacheAliasMask):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_L2CacheSize)
|
||||
_C_LABEL(mips_L2CacheSize):
|
||||
.globl _C_LABEL(mips_L2CachePresent)
|
||||
_C_LABEL(mips_L2CachePresent):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips_L2CacheLSize)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore_r2000.S,v 1.44 1998/09/09 00:07:53 thorpej Exp $ */
|
||||
/* $NetBSD: locore_r2000.S,v 1.45 1998/09/11 16:46:32 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -61,6 +61,14 @@
|
||||
#define INTR_RA_OFFSET STAND_RA_OFFSET
|
||||
#define INTR_FRAME_OFFSET STAND_FRAME_SIZE
|
||||
|
||||
/*
|
||||
* Mark where code entered from exception hander jumptable
|
||||
* starts, for stack traceback code.
|
||||
*/
|
||||
|
||||
.globl _C_LABEL(mips1_exceptionentry_start)
|
||||
_C_LABEL(mips1_exceptionentry_start):
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
@ -158,7 +166,7 @@ _C_LABEL(mips1_exceptionEnd):
|
||||
*
|
||||
* mips1_SlowFault --
|
||||
*
|
||||
* Alternate entry point into the mips1_UserGenExceptionor or
|
||||
* Alternate entry point into the mips1_UserGenException or
|
||||
* or mips1_user_Kern_exception, when the ULTB miss handler couldn't
|
||||
* find a TLB entry.
|
||||
*
|
||||
@ -258,6 +266,8 @@ NNON_LEAF(mips1_KernGenException, TRAP_FRAME_SIZE, ra)
|
||||
j k0
|
||||
rfe
|
||||
.set at
|
||||
.global _C_LABEL(mips1_KernGenExceptionEnd)
|
||||
_C_LABEL(mips1_KernGenExceptionEnd):
|
||||
END(mips1_KernGenException)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
@ -373,6 +383,8 @@ NNON_LEAF(mips1_UserGenException, STAND_FRAME_SIZE, ra)
|
||||
j k0
|
||||
rfe
|
||||
.set at
|
||||
.globl _C_LABEL(mips1_UserGenExceptionEnd)
|
||||
_C_LABEL(mips1_UserGenExceptionEnd):
|
||||
END(mips1_UserGenException)
|
||||
|
||||
/*
|
||||
@ -477,6 +489,8 @@ NNON_LEAF(mips1_SystemCall, STAND_FRAME_SIZE, ra)
|
||||
j k0
|
||||
rfe
|
||||
.set at
|
||||
.globl _C_LABEL(mips1_SystemCallEnd)
|
||||
_C_LABEL(mips1_SystemCallEnd):
|
||||
END(mips1_SystemCall)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
@ -567,6 +581,8 @@ NNON_LEAF(mips1_KernIntr, INTR_FRAME_SIZE, ra)
|
||||
addu sp, sp, INTR_FRAME_SIZE # restore kernel SP
|
||||
j k0 # Now return from interrupt
|
||||
rfe #
|
||||
.globl _C_LABEL(mips1_KernIntrEnd)
|
||||
_C_LABEL(mips1_KernIntrEnd):
|
||||
END(mips1_KernIntr)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
@ -711,16 +727,10 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
|
||||
j k0
|
||||
rfe
|
||||
.set at
|
||||
.globl _C_LABEL(mips1_UserIntrEnd)
|
||||
_C_LABEL(mips1_UserIntrEnd):
|
||||
END(mips1_UserIntr)
|
||||
|
||||
/*
|
||||
* Mark where code entreed from exception hander jumptable
|
||||
* ends, for stack traceback code.
|
||||
*/
|
||||
|
||||
.globl _C_LABEL(mips1_exceptionentry_end)
|
||||
_C_LABEL(mips1_exceptionentry_end):
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
@ -730,7 +740,6 @@ _C_LABEL(mips1_exceptionentry_end):
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#if 0
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
@ -848,6 +857,14 @@ NLEAF(mips1_TLBMissException)
|
||||
.set at
|
||||
END(mips1_TLBMissException)
|
||||
|
||||
/*
|
||||
* Mark where code entered from exception hander jumptable
|
||||
* ends, for stack traceback code.
|
||||
*/
|
||||
|
||||
.globl _C_LABEL(mips1_exceptionentry_end)
|
||||
_C_LABEL(mips1_exceptionentry_end):
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------
|
||||
*
|
||||
@ -950,8 +967,9 @@ END(mips1_SetPID)
|
||||
* mips1_TLBFlush --
|
||||
*
|
||||
* Flush the "random" entries from the TLB.
|
||||
* Arg "tlbsize" is the number of entries to flush.
|
||||
*
|
||||
* mips1_TLBFlush()
|
||||
* mips1_TLBFlush(tlbsize)
|
||||
*
|
||||
* Results:
|
||||
* None.
|
||||
@ -972,7 +990,7 @@ LEAF(mips1_TLBFlush)
|
||||
* Align the starting value (t1) and the upper bound (t2).
|
||||
*/
|
||||
li t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
|
||||
li t2, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT
|
||||
sll t2, a0, MIPS1_TLB_INDEX_SHIFT
|
||||
1:
|
||||
mtc0 t1, MIPS_COP_0_TLB_INDEX # Set the index register.
|
||||
addu t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT # Increment index.
|
||||
@ -1237,8 +1255,8 @@ END(mips1_TLBGetPID)
|
||||
* None.
|
||||
*
|
||||
* Side effects:
|
||||
* The size of the data cache is stored into mips_L1DataCacheSize and the
|
||||
* size of instruction cache is stored into mips_L1InstCacheSize.
|
||||
* The size of the data cache is stored into mips_L1DCacheSize and the
|
||||
* size of instruction cache is stored into mips_L1ICacheSize.
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
@ -1259,7 +1277,7 @@ NON_LEAF(mips1_ConfigCache, STAND_FRAME_SIZE, ra)
|
||||
*/
|
||||
jal _C_LABEL(mips1_SizeCache) # Get the size of the d-cache.
|
||||
nop
|
||||
sw v0, _C_LABEL(mips_L1DataCacheSize)
|
||||
sw v0, _C_LABEL(mips_L1DCacheSize)
|
||||
nop # Make sure sw out of pipe
|
||||
nop
|
||||
nop
|
||||
@ -1277,7 +1295,7 @@ NON_LEAF(mips1_ConfigCache, STAND_FRAME_SIZE, ra)
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
sw v0, _C_LABEL(mips_L1InstCacheSize)
|
||||
sw v0, _C_LABEL(mips_L1ICacheSize)
|
||||
la t0, 1f
|
||||
j t0 # Back to cached mode
|
||||
nop
|
||||
@ -1361,8 +1379,8 @@ END(mips1_SizeCache)
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
LEAF(mips1_FlushCache)
|
||||
lw t1, _C_LABEL(mips_L1InstCacheSize) # Must load before isolating
|
||||
lw t2, _C_LABEL(mips_L1DataCacheSize) # Must load before isolating
|
||||
lw t1, _C_LABEL(mips_L1ICacheSize) # Must load before isolating
|
||||
lw t2, _C_LABEL(mips_L1DCacheSize) # Must load before isolating
|
||||
mfc0 t3, MIPS_COP_0_STATUS_REG # Save the status register.
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts.
|
||||
la v0, 1f
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore_r4000.S,v 1.44 1998/09/09 00:07:53 thorpej Exp $ */
|
||||
/* $NetBSD: locore_r4000.S,v 1.45 1998/09/11 16:46:33 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
|
||||
@ -94,12 +94,18 @@
|
||||
*
|
||||
*============================================================================
|
||||
|
||||
/*
|
||||
* Mark where code entered from exception hander jumptable
|
||||
* starts, for stack traceback code.
|
||||
*/
|
||||
|
||||
.globl _C_LABEL(mips3_exceptionentry_start)
|
||||
_C_LABEL(mips3_exceptionentry_start):
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* mips3_TLBMiss --
|
||||
* MachTLBMiss --
|
||||
*
|
||||
* Vector code for the TLB-miss exception vector 0x80000180
|
||||
* on an r4000.
|
||||
@ -114,8 +120,6 @@
|
||||
*/
|
||||
.globl _C_LABEL(mips3_TLBMiss)
|
||||
_C_LABEL(mips3_TLBMiss):
|
||||
.globl _C_LABEL(MachTLBMiss)
|
||||
_C_LABEL(MachTLBMiss):
|
||||
.set noat
|
||||
.set mips3
|
||||
dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
|
||||
@ -153,14 +157,12 @@ _C_LABEL(MachTLBMiss):
|
||||
nop
|
||||
eret
|
||||
1:
|
||||
j mips3_TLBMissException
|
||||
j _C_LABEL(mips3_TLBMissException)
|
||||
nop
|
||||
2:
|
||||
j mips3_SlowFault
|
||||
nop
|
||||
|
||||
.globl _C_LABEL(MachTLBMissEnd)
|
||||
_C_LABEL(MachTLBMissEnd):
|
||||
.globl _C_LABEL(mips3_TLBMissEnd)
|
||||
_C_LABEL(mips3_TLBMissEnd):
|
||||
.set at
|
||||
@ -178,7 +180,7 @@ _C_LABEL(mips3_TLBMissEnd):
|
||||
* NOTE: This code must be relocatable!!!
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
.globl mips3_exception
|
||||
.globl _C_LABEL(mips3_exception)
|
||||
_C_LABEL(mips3_exception):
|
||||
/*
|
||||
* Find out what mode we came from and jump to the proper handler.
|
||||
@ -193,7 +195,7 @@ _C_LABEL(mips3_exception):
|
||||
and k1, k1, MIPS3_CR_EXC_CODE # Mask out the cause bits.
|
||||
or k1, k1, k0 # change index to user table
|
||||
1:
|
||||
la k0, mips3_ExceptionTable # get base of the jump table
|
||||
la k0, _C_LABEL(mips3_ExceptionTable) # get base of the jump table
|
||||
addu k0, k0, k1 # Get the address of the
|
||||
# function entry. Note that
|
||||
# the cause is already
|
||||
@ -204,7 +206,7 @@ _C_LABEL(mips3_exception):
|
||||
j k0 # Jump to the function.
|
||||
nop
|
||||
.set at
|
||||
.globl mips3_exceptionEnd
|
||||
.globl _C_LABEL(mips3_exceptionEnd)
|
||||
_C_LABEL(mips3_exceptionEnd):
|
||||
|
||||
|
||||
@ -212,7 +214,7 @@ _C_LABEL(mips3_exceptionEnd):
|
||||
*
|
||||
* mips3_SlowFault --
|
||||
*
|
||||
* Alternate entry point into the mips3_UserGenExceptionor or
|
||||
* Alternate entry point into the mips3_UserGenException or
|
||||
* or mips3_user_Kern_exception, when the ULTB miss handler couldn't
|
||||
* find a TLB entry.
|
||||
*
|
||||
@ -230,7 +232,7 @@ mips3_SlowFault:
|
||||
mfc0 k0, MIPS_COP_0_STATUS_REG
|
||||
nop
|
||||
and k0, k0, MIPS3_SR_KSU_USER
|
||||
bne k0, zero, mips3_UserGenException
|
||||
bne k0, zero, _C_LABEL(mips3_UserGenException)
|
||||
nop
|
||||
.set at
|
||||
/*
|
||||
@ -357,6 +359,8 @@ NNON_LEAF(mips3_KernGenException, TRAP_FRAME_SIZE, ra)
|
||||
addu sp, sp, TRAP_FRAME_SIZE
|
||||
eret # exception.
|
||||
.set at
|
||||
.globl _C_LABEL(mips3_KernGenExceptionEnd)
|
||||
_C_LABEL(mips3_KernGenExceptionEnd):
|
||||
END(mips3_KernGenException)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
@ -499,6 +503,8 @@ NNON_LEAF(mips3_UserGenException, STAND_FRAME_SIZE, ra)
|
||||
|
||||
eret
|
||||
.set at
|
||||
.globl _C_LABEL(mips3_UserGenExceptionEnd)
|
||||
_C_LABEL(mips3_UserGenExceptionEnd):
|
||||
END(mips3_UserGenException)
|
||||
|
||||
/*
|
||||
@ -622,6 +628,8 @@ NNON_LEAF(mips3_SystemCall, STAND_FRAME_SIZE, ra)
|
||||
nop
|
||||
eret
|
||||
.set at
|
||||
.globl _C_LABEL(mips3_SystemCallEnd)
|
||||
_C_LABEL(mips3_SystemCallEnd):
|
||||
END(mips3_SystemCall)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
@ -724,6 +732,8 @@ NNON_LEAF(mips3_KernIntr, KINTR_FRAME_SIZE, ra)
|
||||
addu sp, sp, KINTR_FRAME_SIZE
|
||||
eret # interrupt.
|
||||
.set at
|
||||
.globl _C_LABEL(mips3_KernIntrEnd)
|
||||
_C_LABEL(mips3_KernIntrEnd):
|
||||
END(mips3_KernIntr)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
@ -812,7 +822,7 @@ NNON_LEAF(mips3_UserIntr, STAND_FRAME_SIZE, ra)
|
||||
|
||||
lw k1, _C_LABEL(curpcb)
|
||||
# lw a0, U_PCB_REGS+(SR * 4)(k1)
|
||||
lw v0, astpending # any pending interrupts?
|
||||
lw v0, _C_LABEL(astpending) # any pending interrupts?
|
||||
nop
|
||||
# mtc0 a0, MIPS_COP_0_STATUS_REG # Restore the SR, disable intrs
|
||||
bne v0, zero, 1f # dont restore, call softintr
|
||||
@ -920,6 +930,8 @@ NNON_LEAF(mips3_UserIntr, STAND_FRAME_SIZE, ra)
|
||||
|
||||
eret
|
||||
.set at
|
||||
.globl _C_LABEL(mips3_UserIntrEnd)
|
||||
_C_LABEL(mips3_UserIntrEnd):
|
||||
END(mips3_UserIntr)
|
||||
|
||||
|
||||
@ -960,11 +972,11 @@ NLEAF(mips3_TLBInvalidException)
|
||||
dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
|
||||
li k1, VM_MIN_KERNEL_ADDRESS # compute index
|
||||
subu k0, k0, k1
|
||||
lw k1, Sysmapsize # index within range?
|
||||
lw k1, _C_LABEL(Sysmapsize) # index within range?
|
||||
srl k0, k0, PGSHIFT
|
||||
sltu k1, k0, k1
|
||||
beq k1, zero, sys_stk_chk # No. check for valid stack
|
||||
lw k1, Sysmap
|
||||
lw k1, _C_LABEL(Sysmap)
|
||||
|
||||
sll k0, k0, 2 # compute offset from index
|
||||
tlbp # Probe the invalid entry
|
||||
@ -986,7 +998,7 @@ NLEAF(mips3_TLBInvalidException)
|
||||
dsrl k0, k0, 34
|
||||
dmtc0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
|
||||
and k0, k0, MIPS3_PG_V # check for valid entry
|
||||
beq k0, zero, mips3_KernGenException # PTE invalid
|
||||
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
|
||||
lw k0, 4(k1) # get odd PTE entry
|
||||
dsll k0, k0, 34
|
||||
dsrl k0, k0, 34
|
||||
@ -1014,7 +1026,7 @@ KernTLBIOdd:
|
||||
dsrl k0, k0, 34
|
||||
dmtc0 k0, MIPS_COP_0_TLB_LO1 # save PTE entry
|
||||
and k0, k0, MIPS3_PG_V # check for valid entry
|
||||
beq k0, zero, mips3_KernGenException # PTE invalid
|
||||
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
|
||||
lw k0, -4(k1) # get even PTE entry
|
||||
dsll k0, k0, 34
|
||||
dsrl k0, k0, 34
|
||||
@ -1050,11 +1062,11 @@ NLEAF(mips3_TLBMissException)
|
||||
dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
|
||||
li k1, VM_MIN_KERNEL_ADDRESS # compute index
|
||||
subu k0, k0, k1
|
||||
lw k1, Sysmapsize # index within range?
|
||||
lw k1, _C_LABEL(Sysmapsize) # index within range?
|
||||
srl k0, k0, PGSHIFT
|
||||
sltu k1, k0, k1
|
||||
beq k1, zero, sys_stk_chk # No. check for valid stack
|
||||
lw k1, Sysmap
|
||||
lw k1, _C_LABEL(Sysmap)
|
||||
srl k0, k0, 1
|
||||
sll k0, k0, 3 # compute offset from index
|
||||
addu k1, k1, k0
|
||||
@ -1078,7 +1090,7 @@ NLEAF(mips3_TLBMissException)
|
||||
sys_stk_chk:
|
||||
subu k0, sp, UADDR + 0x200 # check to see if we have a
|
||||
sltiu k0, UPAGES*NBPG - 0x200 # valid kernel stack
|
||||
bne k0, zero, mips3_KernGenException # Go panic
|
||||
bne k0, zero, _C_LABEL(mips3_KernGenException) # Go panic
|
||||
nop
|
||||
|
||||
la a0, start - START_FRAME - 8 # set sp to a valid place
|
||||
@ -1091,7 +1103,7 @@ sys_stk_chk:
|
||||
sw a2, 16(sp)
|
||||
sw a3, 20(sp)
|
||||
move a2, ra
|
||||
jal printf
|
||||
jal _C_LABEL(printf)
|
||||
dmfc0 a3, MIPS_COP_0_BAD_VADDR
|
||||
.data
|
||||
1:
|
||||
@ -1101,7 +1113,7 @@ sys_stk_chk:
|
||||
/* Call mips3_dump_tlb(0, 2, printf) to show the bad kstack TLB */
|
||||
la a2, _C_LABEL(printf)
|
||||
li a0, 0
|
||||
jal mips3_dump_tlb
|
||||
jal _C_LABEL(mips3_dump_tlb)
|
||||
li a1, 2 # BDslot
|
||||
|
||||
la sp, start - START_FRAME # set sp to a valid place
|
||||
@ -1113,7 +1125,7 @@ sys_stk_chk:
|
||||
END(mips3_TLBMissException)
|
||||
|
||||
/*
|
||||
* Mark where code entreed from exception hander jumptable
|
||||
* Mark where code entered from exception hander jumptable
|
||||
* ends, for stack traceback code.
|
||||
*/
|
||||
|
||||
@ -1296,8 +1308,9 @@ END(mips3_GetWIRED)
|
||||
*
|
||||
* Flush the "random" entries from the TLB.
|
||||
* Uses "wired" register to determine what register to start with.
|
||||
* Arg "tlbsize" is the number of entries to flush.
|
||||
*
|
||||
* mips3_TLBFlush()
|
||||
* mips3_TLBFlush(tlbsize)
|
||||
*
|
||||
* Results:
|
||||
* None.
|
||||
@ -1311,7 +1324,6 @@ LEAF(mips3_TLBFlush)
|
||||
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
|
||||
mfc0 t1, MIPS_COP_0_TLB_WIRED
|
||||
li t2, MIPS3_TLB_NUM_TLB_ENTRIES
|
||||
li v0, MIPS_KSEG0_START # invalid address
|
||||
dmfc0 t0, MIPS_COP_0_TLB_HI # Save the PID
|
||||
|
||||
@ -1320,7 +1332,7 @@ LEAF(mips3_TLBFlush)
|
||||
dmtc0 zero, MIPS_COP_0_TLB_LO1 # Zero out low entry1.
|
||||
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # Zero out mask entry.
|
||||
/*
|
||||
* Align the starting value (t1) and the upper bound (t2).
|
||||
* Align the starting value (t1) and the upper bound (a0).
|
||||
*/
|
||||
1:
|
||||
mtc0 t1, MIPS_COP_0_TLB_INDEX # Set the index register.
|
||||
@ -1328,7 +1340,7 @@ LEAF(mips3_TLBFlush)
|
||||
tlbwi # Write the TLB entry.
|
||||
nop
|
||||
nop
|
||||
bne t1, t2, 1b
|
||||
bne t1, a0, 1b
|
||||
nop
|
||||
|
||||
dmtc0 t0, MIPS_COP_0_TLB_HI # Restore the PID
|
||||
@ -1600,72 +1612,14 @@ END(mips3_TLBGetPID)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
* R4000 cache sizing and flushing code.
|
||||
* R4000 cache flushing code.
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
* mips3_ConfigCache --
|
||||
*
|
||||
* Size the caches.
|
||||
* NOTE: should only be called from mach_init().
|
||||
*
|
||||
* Results:
|
||||
* None.
|
||||
*
|
||||
* Side effects:
|
||||
* The size of the data cache is stored into mips_L1DataCacheSize.
|
||||
* The size of instruction cache is stored into mips_L1InstCacheSize.
|
||||
* Alignment mask for cache aliasing test is stored in mips_CacheAliasMask.
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
/*
|
||||
* XXX need to handle two-way caches for r4600 and mips ISA-IV.
|
||||
*/
|
||||
LEAF(mips3_ConfigCache)
|
||||
mfc0 v0, MIPS_COP_0_CONFIG # Get configuration register
|
||||
nop
|
||||
srl t1, v0, 9 # Get D cache size.
|
||||
and t1, 7 # ???
|
||||
li t2, 4096
|
||||
sllv t2, t2, t1
|
||||
sw t2, mips_L1DataCacheSize
|
||||
addiu t2, -1
|
||||
and t2, ~(NBPG - 1)
|
||||
sw t2, mips_CacheAliasMask
|
||||
|
||||
and t2, v0, 0x20
|
||||
srl t2, t2, 1
|
||||
addu t2, t2, 16
|
||||
sw t2, mips_L1DataCacheLSize
|
||||
|
||||
srl t1, v0, 6 # Get I cache size.
|
||||
and t1, 7 # ???
|
||||
li t2, 4096
|
||||
sllv t2, t2, t1
|
||||
sw t2, mips_L1InstCacheSize
|
||||
|
||||
and t2, v0, 0x10
|
||||
addu t2, t2, 16
|
||||
sw t2, mips_L1InstCacheLSize
|
||||
|
||||
lui t1, 2
|
||||
and t1, t1, v0
|
||||
bne t1, zero, 1f
|
||||
nop
|
||||
lui t1, 0x10
|
||||
sw t1, mips_L2CacheSize
|
||||
lui t1, 0xc0
|
||||
and t1, t1, v0
|
||||
srl t1, 22
|
||||
li t2, 16
|
||||
sllv t2, t2, t1
|
||||
sw t2, mips_L2CacheLSize
|
||||
1:
|
||||
j ra
|
||||
nop
|
||||
END(mips3_ConfigCache)
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
@ -1682,10 +1636,10 @@ END(mips3_ConfigCache)
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
LEAF(mips3_FlushCache)
|
||||
lw t1, mips_L1InstCacheSize
|
||||
lw t2, mips_L1DataCacheSize
|
||||
# lw t3, mips_L1InstCacheLSize
|
||||
# lw t4, mips_L1DataCacheLSize
|
||||
lw t1, mips_L1ICacheSize
|
||||
lw t2, mips_L1DCacheSize
|
||||
# lw t3, mips_L1ICacheLSize
|
||||
# lw t4, mips_L1DCacheLSize
|
||||
/*
|
||||
* Flush the instruction cache.
|
||||
*/
|
||||
@ -1803,7 +1757,7 @@ END(mips3_FlushICache)
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
LEAF(mips3_FlushDCache)
|
||||
lw a2, mips_L1DataCacheSize
|
||||
lw a2, mips_L1DCacheSize
|
||||
addiu a2, -1
|
||||
move t0, a0 # copy start address
|
||||
and a0, a0, a2 # get index into primary cache
|
||||
@ -1962,7 +1916,7 @@ ALEAF(mips3_VCEI) /* XXXX */
|
||||
and k0, -16
|
||||
sw k0, vce_savek0 # save virtual address
|
||||
cache 1, 0(k0) # writeback primary line
|
||||
lw k1, mips_L1DataCacheSize
|
||||
lw k1, _C_LABEL(mips_L1DCacheSize)
|
||||
addiu k1, -1
|
||||
and k0, k0, k1 # mask to cache index
|
||||
or k0, 0x80000000 # physical K0SEG address
|
||||
@ -2317,6 +2271,12 @@ LEAF(mips3_read_compare)
|
||||
nop
|
||||
END(mips3_read_compare)
|
||||
|
||||
LEAF(mips3_read_config)
|
||||
mfc0 v0, MIPS_COP_0_CONFIG
|
||||
nop
|
||||
j ra
|
||||
nop
|
||||
END(mips3_read_config)
|
||||
|
||||
/*
|
||||
* Write value to compare register.
|
||||
@ -2331,10 +2291,25 @@ LEAF(mips3_write_compare)
|
||||
nop
|
||||
END(mips3_write_compare)
|
||||
|
||||
/*
|
||||
* The variables below are used to communicate the cache handling
|
||||
* to higher-level software.
|
||||
*/
|
||||
.data
|
||||
|
||||
.globl _C_LABEL(mips3_L1TwoWayCache)
|
||||
_C_LABEL(mips3_L1TwoWayCache):
|
||||
.word 0
|
||||
|
||||
.globl _C_LABEL(mips3_cacheflush_bug)
|
||||
_C_LABEL(mips3_cacheflush_bug):
|
||||
.word 0
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
* XXX END of r4000-specific code XXX
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
.text
|
||||
.set mips2
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: mips_machdep.c,v 1.29 1998/09/02 06:41:22 nisimura Exp $ */
|
||||
/* $NetBSD: mips_machdep.c,v 1.30 1998/09/11 16:46:33 jonathan Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
@ -52,7 +52,7 @@
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.29 1998/09/02 06:41:22 nisimura Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.30 1998/09/11 16:46:33 jonathan Exp $");
|
||||
|
||||
#include "opt_uvm.h"
|
||||
|
||||
@ -102,8 +102,14 @@ int cpu_dumpsize __P((void));
|
||||
u_long cpu_dump_mempagecnt __P((void));
|
||||
int cpu_dump __P((void));
|
||||
|
||||
void mips1_vector_init __P((void));
|
||||
void mips3_vector_init __P((void));
|
||||
#ifdef MIPS1
|
||||
static void mips1_vector_init __P((void));
|
||||
#endif
|
||||
|
||||
#ifdef MIPS3
|
||||
static void mips3_vector_init __P((void));
|
||||
#endif
|
||||
|
||||
|
||||
mips_locore_jumpvec_t mips_locore_jumpvec = {
|
||||
NULL, NULL, NULL, NULL,
|
||||
@ -127,6 +133,13 @@ int bufpages = 0;
|
||||
#endif
|
||||
|
||||
int cpu_mhz;
|
||||
int mips_num_tlb_entries;
|
||||
|
||||
#ifdef MIPS3
|
||||
u_int mips_L2CacheSize;
|
||||
int mips_L2CacheIsSnooping; /* Set if L2 cache snoops uncached writes */
|
||||
int mips_L2CacheMixed;
|
||||
#endif
|
||||
|
||||
struct user *proc0paddr;
|
||||
struct proc nullproc; /* for use by switch_exit() */
|
||||
@ -164,7 +177,7 @@ mips_locore_jumpvec_t mips1_locore_vec =
|
||||
mips1_cpu_switch_resume
|
||||
};
|
||||
|
||||
void
|
||||
static void
|
||||
mips1_vector_init()
|
||||
{
|
||||
extern char mips1_UTLBMiss[], mips1_UTLBMissEnd[];
|
||||
@ -223,7 +236,64 @@ mips_locore_jumpvec_t mips3_locore_vec =
|
||||
mips3_cpu_switch_resume
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*
|
||||
* mips3_ConfigCache --
|
||||
*
|
||||
* Size the caches.
|
||||
* NOTE: should only be called from mach_init().
|
||||
*
|
||||
* Results:
|
||||
* None.
|
||||
*
|
||||
* Side effects:
|
||||
* The size of the data cache is stored into mips_L1DCacheSize.
|
||||
* The size of instruction cache is stored into mips_L1ICacheSize.
|
||||
* Alignment mask for cache aliasing test is stored in mips_CacheAliasMask.
|
||||
*
|
||||
* XXX: method to retrieve mips_L2CacheSize is port dependent.
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
void
|
||||
mips3_ConfigCache()
|
||||
{
|
||||
u_int32_t config = mips3_read_config();
|
||||
static int snoop_check = 0;
|
||||
register int i;
|
||||
|
||||
mips_L1ICacheSize = MIPS3_CONFIG_CACHE_SIZE(config,
|
||||
MIPS3_CONFIG_IC_MASK, MIPS3_CONFIG_IC_SHIFT);
|
||||
mips_L1ICacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
|
||||
MIPS3_CONFIG_IB);
|
||||
mips_L1DCacheSize = MIPS3_CONFIG_CACHE_SIZE(config,
|
||||
MIPS3_CONFIG_DC_MASK, MIPS3_CONFIG_DC_SHIFT);
|
||||
mips_L1DCacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
|
||||
MIPS3_CONFIG_DB);
|
||||
|
||||
mips_CacheAliasMask = (mips_L1DCacheLSize - 1) & ~(NBPG - 1);
|
||||
|
||||
/*
|
||||
* Clear out the I and D caches.
|
||||
*/
|
||||
mips_L2CachePresent = 0; /* kluge to skip L2 cache flush */
|
||||
mips3_FlushCache();
|
||||
|
||||
i = *(volatile int *)&snoop_check; /* Read and cache */
|
||||
mips3_FlushCache(); /* Flush */
|
||||
*(volatile int *)MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&snoop_check))
|
||||
= ~i; /* Write uncached */
|
||||
mips_L2CacheIsSnooping = *(volatile int *)&snoop_check == ~i;
|
||||
*(volatile int *)&snoop_check = i; /* Write uncached */
|
||||
mips3_FlushCache(); /* Flush */
|
||||
|
||||
|
||||
mips_L2CachePresent = (config & MIPS3_CONFIG_SC) == 0;
|
||||
mips_L2CacheLSize = MIPS3_CONFIG_CACHE_L2_LSIZE(config);
|
||||
mips_L2CacheMixed = (config & MIPS3_CONFIG_SS) == 0;
|
||||
}
|
||||
|
||||
static void
|
||||
mips3_vector_init()
|
||||
{
|
||||
|
||||
@ -236,7 +306,7 @@ mips3_vector_init()
|
||||
/*
|
||||
* Copy down exception vector code.
|
||||
*/
|
||||
#if 0 /* XXX not restricted? */
|
||||
#if 0 /* XXX: this should be checked, if we will handle XTLB miss. */
|
||||
if (mips3_TLBMissEnd - mips3_TLBMiss > 0x80)
|
||||
panic("startup: UTLB code too large");
|
||||
#endif
|
||||
@ -256,6 +326,12 @@ mips3_vector_init()
|
||||
* Clear out the I and D caches.
|
||||
*/
|
||||
mips3_ConfigCache();
|
||||
|
||||
#ifdef pmax /* XXX */
|
||||
mips_L2CachePresent = 1;
|
||||
mips_L2CacheSize = 1024 * 1024;
|
||||
#endif
|
||||
|
||||
mips3_FlushCache();
|
||||
}
|
||||
#endif /* MIPS3 */
|
||||
@ -299,24 +375,75 @@ mips_vector_init()
|
||||
case MIPS_R2000:
|
||||
case MIPS_R3000:
|
||||
cpu_arch = 1;
|
||||
mips1_TLBFlush();
|
||||
mips_num_tlb_entries = MIPS1_TLB_NUM_TLB_ENTRIES;
|
||||
break;
|
||||
#endif /* MIPS1 */
|
||||
|
||||
#ifdef MIPS3
|
||||
case MIPS_R4000:
|
||||
cpu_arch = 3;
|
||||
mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
|
||||
mips3_L1TwoWayCache = 0;
|
||||
mips3_cacheflush_bug = 0;
|
||||
mips3_cacheflush_bug = 1; /* XXX FIXME: probably not needed */
|
||||
break;
|
||||
case MIPS_R4300:
|
||||
cpu_arch = 3;
|
||||
mips_num_tlb_entries = MIPS_R4300_TLB_NUM_TLB_ENTRIES;
|
||||
mips3_L1TwoWayCache = 0;
|
||||
mips3_cacheflush_bug = 0;
|
||||
break;
|
||||
case MIPS_R4600:
|
||||
cpu_arch = 3;
|
||||
mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
|
||||
mips3_L1TwoWayCache = 1;
|
||||
/* disable interrupt while cacheflush to workaround the bug */
|
||||
mips3_cacheflush_bug = 1; /* R4600 only??? */
|
||||
break;
|
||||
#ifdef ENABLE_MIPS_R4700 /* ID conflict */
|
||||
case MIPS_R4700:
|
||||
cpu_arch = 3;
|
||||
mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
|
||||
mips3_L1TwoWayCache = 1;
|
||||
mips3_cacheflush_bug = 0;
|
||||
break;
|
||||
#endif
|
||||
#ifndef ENABLE_MIPS_R3NKK /* ID conflict */
|
||||
case MIPS_R5000:
|
||||
#endif
|
||||
case MIPS_RM5230:
|
||||
cpu_arch = 3 /*4*/; /* FIXME: these are MIPS ISA IV */
|
||||
mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
|
||||
mips3_L1TwoWayCache = 1;
|
||||
mips3_cacheflush_bug = 0;
|
||||
break;
|
||||
#endif /* MIPS3 */
|
||||
|
||||
default:
|
||||
printf("CPU type (%d) not supported\n", cpu_id.cpu.cp_imp);
|
||||
cpu_reboot(RB_HALT, NULL);
|
||||
}
|
||||
|
||||
switch (cpu_arch) {
|
||||
#ifdef MIPS1
|
||||
case 1:
|
||||
mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES);
|
||||
for (i = 0; i < MIPS1_TLB_FIRST_RAND_ENTRY; ++i)
|
||||
mips1_TLBWriteIndexed(i, MIPS_KSEG0_START, 0);
|
||||
mips1_vector_init();
|
||||
break;
|
||||
#endif
|
||||
#ifdef MIPS3
|
||||
case MIPS_R4000:
|
||||
cpu_arch = 3;
|
||||
case 3:
|
||||
case 4:
|
||||
mips3_SetWIRED(0);
|
||||
mips3_TLBFlush();
|
||||
mips3_TLBFlush(mips_num_tlb_entries);
|
||||
mips3_SetWIRED(MIPS3_TLB_WIRED_ENTRIES);
|
||||
mips3_vector_init();
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
printf("CPU type (%d) not supported\n", cpu_id.cpu.cp_imp);
|
||||
printf("MIPS ISA %d: not supported\n", cpu_arch);
|
||||
cpu_reboot(RB_HALT, NULL);
|
||||
}
|
||||
}
|
||||
@ -364,7 +491,7 @@ cpu_identify()
|
||||
printf("MIPS R6000 CPU");
|
||||
break;
|
||||
case MIPS_R4000:
|
||||
if(mips_L1InstCacheSize == 16384)
|
||||
if(mips_L1ICacheSize == 16384)
|
||||
printf("MIPS R4400 CPU");
|
||||
else
|
||||
printf("MIPS R4000 CPU");
|
||||
@ -382,7 +509,14 @@ cpu_identify()
|
||||
printf("MIPS R10000/T5 CPU");
|
||||
break;
|
||||
case MIPS_R4200:
|
||||
#if 0
|
||||
printf("NEC VR4200 CPU (ICE)");
|
||||
#else
|
||||
printf("MIPS R4200 CPU (ICE)");
|
||||
#endif
|
||||
break;
|
||||
case MIPS_R4300:
|
||||
printf("NEC VR4300 CPU");
|
||||
break;
|
||||
case MIPS_R8000:
|
||||
printf("MIPS R8000 Blackbird/TFP CPU");
|
||||
@ -390,14 +524,26 @@ cpu_identify()
|
||||
case MIPS_R4600:
|
||||
printf("QED R4600 Orion CPU");
|
||||
break;
|
||||
case MIPS_R3SONY:
|
||||
case MIPS_R4700: /* ID conflict: case MIPS_R3SONY: */
|
||||
#ifndef ENABLE_MIPS_R4700
|
||||
printf("Sony R3000 based CPU");
|
||||
#else
|
||||
printf("QED R4700 Orion CPU");
|
||||
#endif
|
||||
break;
|
||||
break;
|
||||
case MIPS_R3TOSH:
|
||||
printf("Toshiba R3000 based CPU");
|
||||
break;
|
||||
case MIPS_R3NKK:
|
||||
case MIPS_R5000: /* ID conflict: case MIPS_R3NKK: */
|
||||
#ifdef ENABLE_MIPS_R3NKK
|
||||
printf("NKK R3000 based CPU");
|
||||
#else
|
||||
printf("MIPS R5000 based CPU");
|
||||
#endif
|
||||
break;
|
||||
case MIPS_RM5230:
|
||||
printf("QED RM5230 based CPU");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown CPU type (0x%x)",cpu_id.cpu.cp_imp);
|
||||
@ -442,21 +588,37 @@ cpu_identify()
|
||||
printf("MIPS R10000/T5 FPU");
|
||||
break;
|
||||
case MIPS_R4210:
|
||||
#if 0
|
||||
printf("NEC VR4200 FPC (ICE)");
|
||||
#else
|
||||
printf("MIPS R4200 FPC (ICE)");
|
||||
#endif
|
||||
break;
|
||||
case MIPS_R8000:
|
||||
printf("MIPS R8000 Blackbird/TFP");
|
||||
break;
|
||||
case MIPS_R4600:
|
||||
printf("QED R4600 Orion FPC");
|
||||
break;
|
||||
case MIPS_R3SONY:
|
||||
case MIPS_R4700: /* ID conflict: case MIPS_R3SONY: */
|
||||
#ifndef ENALBE_MIPS_R4700
|
||||
printf("Sony R3000 based FPC");
|
||||
#else
|
||||
printf("QED R4700 Orion FPC");
|
||||
#endif
|
||||
break;
|
||||
case MIPS_R3TOSH:
|
||||
printf("Toshiba R3000 based FPC");
|
||||
break;
|
||||
case MIPS_R3NKK:
|
||||
case MIPS_R5010: /* ID conflict: case MIPS_R3NKK: */
|
||||
#ifdef ENABLE_MIPS_R3NKK
|
||||
printf("NKK R3000 based FPC");
|
||||
#else
|
||||
printf("MIPS R5010 based FPC");
|
||||
#endif
|
||||
break;
|
||||
case MIPS_RM5230:
|
||||
printf("QED RM5230 based FPC");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown FPU type (0x%x)", fpu_id.cpu.cp_imp);
|
||||
@ -465,16 +627,65 @@ cpu_identify()
|
||||
printf(" Rev. %d.%d", fpu_id.cpu.cp_majrev, fpu_id.cpu.cp_minrev);
|
||||
printf("\n");
|
||||
|
||||
printf(" L1 cache: %dkb Instruction, %dkb Data.",
|
||||
mips_L1InstCacheSize / 1024,
|
||||
mips_L1DataCacheSize / 1024);
|
||||
if (mips_L2CacheSize)
|
||||
printf(" L2 cache: %dkb mixed.\n", mips_L2CacheSize / 1024);
|
||||
printf(" L1 cache: %dkb/%db Instruction, %dkb/%db Data.",
|
||||
mips_L1ICacheSize / 1024, mips_L1ICacheLSize,
|
||||
mips_L1DCacheSize / 1024, mips_L1DCacheLSize);
|
||||
#ifdef MIPS3
|
||||
if (mips3_L1TwoWayCache)
|
||||
printf(" Two way set associative.");
|
||||
else
|
||||
#endif
|
||||
printf(" Direct mapped.");
|
||||
printf("\n");
|
||||
|
||||
#ifdef MIPS3
|
||||
if (!mips_L2CachePresent)
|
||||
printf(" No L2 cache.\n");
|
||||
else {
|
||||
printf(" L2 cache: ");
|
||||
if (mips_L2CacheSize)
|
||||
printf("%dkb", mips_L2CacheSize / 1024);
|
||||
else
|
||||
printf("unknown size");
|
||||
printf("/%db %s (%s).\n", mips_L2CacheLSize,
|
||||
mips_L2CacheMixed ? "mixed" : "separated",
|
||||
mips_L2CacheIsSnooping ? "snooping" : "no snooping");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* XXX cache sizes for MIPS1? */
|
||||
/* XXX hardware mcclock CPU-speed computation */
|
||||
|
||||
#ifdef MIPS3
|
||||
/*
|
||||
* sanity check.
|
||||
* good place to do this is mips_vector_init(),
|
||||
* but printf() doesn't work in it.
|
||||
*/
|
||||
if (mips3_L1TwoWayCache &&
|
||||
(mips_L1ICacheLSize < 32 || mips_L1DCacheLSize < 32)) {
|
||||
/*
|
||||
* current implementation of mips3_FlushCache(),
|
||||
* mips3_FlushICache(), mips3_FlushDCache() and
|
||||
* mips3_HitFlushDCache() assume that
|
||||
* if the CPU has two way L1 cache, line size >= 32.
|
||||
*/
|
||||
printf("L1 cache: two way, but Inst/Data line size = %d/%d\n",
|
||||
mips_L1ICacheLSize, mips_L1DCacheLSize);
|
||||
printf("Please fix implementation of mips3_*Flush*Cache\n");
|
||||
cpu_reboot(RB_HALT, NULL);
|
||||
}
|
||||
if (mips_L2CachePresent && mips_L2CacheLSize < 32) {
|
||||
/*
|
||||
* current implementation of mips3_FlushCache(),
|
||||
* mips3_FlushDCache() and mips3_HitFlushDCache() assume
|
||||
* that if the CPU has L2 cache, line size >= 32.
|
||||
*/
|
||||
printf("L2 cache line size = %d\n", mips_L2CacheLSize);
|
||||
printf("Please fix implementation of mips3_*Flush*Cache\n");
|
||||
cpu_reboot(RB_HALT, NULL);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -1083,8 +1294,8 @@ mips_init_proc0(space)
|
||||
int i;
|
||||
|
||||
proc0.p_addr = proc0paddr = (struct user *)space;
|
||||
curpcb = (struct pcb *)proc0.p_addr;
|
||||
proc0.p_md.md_regs = proc0paddr->u_pcb.pcb_regs;
|
||||
curpcb = &proc0.p_addr->u_pcb;
|
||||
|
||||
pa = MIPS_KSEG0_TO_PHYS(proc0.p_addr);
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pmap.c,v 1.40 1998/05/19 19:00:16 thorpej Exp $ */
|
||||
/* $NetBSD: pmap.c,v 1.41 1998/09/11 16:46:33 jonathan Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
@ -78,7 +78,7 @@
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.40 1998/05/19 19:00:16 thorpej Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.41 1998/09/11 16:46:33 jonathan Exp $");
|
||||
|
||||
/*
|
||||
* Manages physical address maps.
|
||||
@ -1493,7 +1493,7 @@ pmap_zero_page(phys)
|
||||
#endif
|
||||
|
||||
#if defined(MIPS3) && defined(MIPS3_FLUSH)
|
||||
if (CPUISMIPS3) {
|
||||
if (CPUISMIPS3 && !mips_L2CachePresent) {
|
||||
/*XXX FIXME Not very sophisticated */
|
||||
/* MachFlushCache();*/
|
||||
MachFlushDCache(phys, NBPG);
|
||||
@ -1534,7 +1534,7 @@ pmap_zero_page(phys)
|
||||
* XXX Do we need to also invalidate any cache lines matching
|
||||
* the destination as well?
|
||||
*/
|
||||
if (CPUISMIPS3) {
|
||||
if (CPUISMIPS3 && !mips_L2CachePresent) {
|
||||
/*XXX FIXME Not very sophisticated */
|
||||
/* MachFlushCache();*/
|
||||
MachFlushDCache(phys, NBPG);
|
||||
@ -1576,7 +1576,7 @@ pmap_copy_page(src, dst)
|
||||
* XXX invalidate any cached lines of the destination PA
|
||||
* here also?
|
||||
*/
|
||||
if (CPUISMIPS3) {
|
||||
if (CPUISMIPS3 && !mips_L2CachePresent) {
|
||||
/*XXX FIXME Not very sophisticated */
|
||||
/* MachFlushCache(); */
|
||||
MachFlushDCache(src, NBPG);
|
||||
@ -1855,7 +1855,8 @@ pmap_enter_pv(pmap, va, pa, npte)
|
||||
/*
|
||||
* Check cache aliasing incompatibility
|
||||
*/
|
||||
if((npv->pv_va & mips_CacheAliasMask) != (va & mips_CacheAliasMask)) {
|
||||
if ((npv->pv_va & mips_CacheAliasMask)
|
||||
!= (va & mips_CacheAliasMask)) {
|
||||
pmap_page_cache(pa,PV_UNCACHED);
|
||||
MachFlushDCache(pv->pv_va, PAGE_SIZE);
|
||||
*npte = (*npte & ~MIPS3_PG_CACHEMODE) | MIPS3_PG_UNCACHED;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: trap.c,v 1.91 1998/08/29 16:13:33 mrg Exp $ */
|
||||
/* $NetBSD: trap.c,v 1.92 1998/09/11 16:46:34 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
@ -43,7 +43,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.91 1998/08/29 16:13:33 mrg Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.92 1998/09/11 16:46:34 jonathan Exp $");
|
||||
|
||||
#include "opt_cputype.h" /* which mips CPU levels do we support? */
|
||||
#include "opt_inet.h"
|
||||
@ -120,13 +120,17 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.91 1998/08/29 16:13:33 mrg Exp $");
|
||||
* Port-specific hardware interrupt handler
|
||||
*/
|
||||
|
||||
int astpending;
|
||||
int want_resched;
|
||||
|
||||
int (*mips_hardware_intr) __P((unsigned mask, unsigned pc, unsigned status,
|
||||
unsigned cause)) =
|
||||
( int (*) __P((unsigned, unsigned, unsigned, unsigned)) ) 0;
|
||||
|
||||
#ifdef MIPS3
|
||||
#if defined(MIPS3) && defined(MIPS3_INTERNAL_TIMER_INTERRUPT)
|
||||
extern u_int32_t mips3_intr_cycle_count;
|
||||
u_int32_t mips3_intr_cycle_count;
|
||||
u_int32_t mips3_timer_delta;
|
||||
#endif
|
||||
|
||||
|
||||
@ -136,12 +140,21 @@ u_int32_t mips3_intr_cycle_count;
|
||||
#ifdef MIPS1
|
||||
extern void mips1_KernGenException __P((void));
|
||||
extern void mips1_UserGenException __P((void));
|
||||
extern void mips1_TLBMissException __P((void));
|
||||
extern void mips1_SystemCall __P((void));
|
||||
extern void mips1_KernIntr __P((void));
|
||||
extern void mips1_UserIntr __P((void));
|
||||
/* marks end of vector code */
|
||||
extern void mips1_UTLBMiss __P((void));
|
||||
#if 0
|
||||
extern void mips1_TLBModException __P((void));
|
||||
#endif
|
||||
extern void mips1_TLBMissException __P((void));
|
||||
|
||||
/* marks start/end of vector code */
|
||||
extern void mips1_KernGenExceptionEnd __P((void));
|
||||
extern void mips1_UserGenExceptionEnd __P((void));
|
||||
extern void mips1_SystemCallEnd __P((void));
|
||||
extern void mips1_KernIntrEnd __P((void));
|
||||
extern void mips1_UserIntrEnd __P((void));
|
||||
extern void mips1_exceptionentry_start __P((void));
|
||||
extern void mips1_exceptionentry_end __P((void));
|
||||
#endif
|
||||
|
||||
@ -151,14 +164,19 @@ extern void mips3_UserGenException __P((void));
|
||||
extern void mips3_SystemCall __P((void));
|
||||
extern void mips3_KernIntr __P((void));
|
||||
extern void mips3_UserIntr __P((void));
|
||||
extern void mips3_TLBModException __P((void));
|
||||
extern void mips3_TLBMissException __P((void));
|
||||
extern void mips3_TLBInvalidException __P((void));
|
||||
extern void mips3_VCED __P((void));
|
||||
extern void mips3_VCEI __P((void));
|
||||
extern void mips3_TLBMissException __P((void));
|
||||
|
||||
/* marks end of vector code */
|
||||
extern void mips3_TLBMiss __P((void));
|
||||
extern void mips3_VCED __P((void));
|
||||
extern void mips3_VCEI __P((void)); /* XXXX */
|
||||
|
||||
/* marks start/end of vector code */
|
||||
extern void mips3_KernGenExceptionEnd __P((void));
|
||||
extern void mips3_UserGenExceptionEnd __P((void));
|
||||
extern void mips3_SystemCallEnd __P((void));
|
||||
extern void mips3_KernIntrEnd __P((void));
|
||||
extern void mips3_UserIntrEnd __P((void));
|
||||
extern void mips3_exceptionentry_start __P((void));
|
||||
extern void mips3_exceptionentry_end __P((void));
|
||||
#endif
|
||||
|
||||
@ -365,6 +383,13 @@ struct trapdebug { /* trap history buffer for debugging */
|
||||
void trapDump __P((char * msg));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* marks start/end of code */
|
||||
extern void splx_end __P((void));
|
||||
extern void cpu_switch_end __P((void));
|
||||
extern void idle_end __P((void));
|
||||
extern void bcopy_end __P((void));
|
||||
extern char start[], edata[];
|
||||
|
||||
|
||||
void mips1_dump_tlb __P((int, int, void (*printfn)(const char*, ...)));
|
||||
void mips3_dump_tlb __P((int, int, void (*printfn)(const char*, ...)));
|
||||
@ -1013,9 +1038,11 @@ interrupt(status, cause, pc, frame)
|
||||
|
||||
mask = cause & status; /* pending interrupts & enable mask */
|
||||
|
||||
#if defined(MIPS3) && defined(MIPS_INT_MASK_CLOCK)
|
||||
if ((mask & MIPS_INT_MASK_CLOCK) && CPUISMIPS3)
|
||||
#if defined(MIPS3) && defined(MIPS3_INTERNAL_TIMER_INTERRUPT)
|
||||
if (CPUISMIPS3 && (mask & MIPS_INT_MASK_5)) {
|
||||
mips3_intr_cycle_count = mips3_cycle_count();
|
||||
mips3_write_compare(mips3_intr_cycle_count + mips3_timer_delta);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
@ -1472,7 +1499,6 @@ stacktrace_subr(a0, a1, a2, a3, pc, sp, fp, ra, printfn)
|
||||
unsigned instr, mask;
|
||||
InstFmt i;
|
||||
int more, stksize;
|
||||
extern char start[], edata[];
|
||||
unsigned int frames = 0;
|
||||
int foundframesize = 0;
|
||||
|
||||
@ -1507,7 +1533,7 @@ specialframe:
|
||||
|
||||
/* Backtraces should continue through interrupts from kernel mode */
|
||||
#ifdef MIPS1 /* r2000 family (mips-I cpu) */
|
||||
if (pcBetween(mips1_KernIntr, mips1_UserIntr)) {
|
||||
if (pcBetween(mips1_KernIntr, mips1_KernIntrEnd)) {
|
||||
/* NOTE: the offsets depend on the code in locore.s */
|
||||
(*printfn)("r3000 KernIntr+%x: (%x, %x ,%x) -------\n",
|
||||
pc-(unsigned)mips1_KernIntr, a0, a1, a2);
|
||||
@ -1521,7 +1547,7 @@ specialframe:
|
||||
sp = sp + 176;
|
||||
goto specialframe;
|
||||
}
|
||||
else if (pcBetween(mips1_KernGenException, mips1_UserGenException)) {
|
||||
else if (pcBetween(mips1_KernGenException, mips1_KernGenExceptionEnd)) {
|
||||
/* NOTE: the offsets depend on the code in locore.s */
|
||||
(*printfn)("------ kernel trap+%x: (%x, %x ,%x) -------\n",
|
||||
pc-(unsigned)mips1_KernGenException, a0, a1, a2);
|
||||
@ -1539,7 +1565,7 @@ specialframe:
|
||||
#endif /* MIPS1 */
|
||||
|
||||
#ifdef MIPS3 /* r4000 family (mips-III cpu) */
|
||||
if (pcBetween(mips3_KernIntr, mips3_UserIntr)) {
|
||||
if (pcBetween(mips3_KernIntr, mips3_KernIntrEnd)) {
|
||||
/* NOTE: the offsets depend on the code in locore.s */
|
||||
(*printfn)("------ mips3 KernIntr+%x: (%x, %x ,%x) -------\n",
|
||||
pc-(unsigned)mips3_KernIntr, a0, a1, a2);
|
||||
@ -1553,7 +1579,7 @@ specialframe:
|
||||
sp = sp + 176;
|
||||
goto specialframe;
|
||||
}
|
||||
else if (pcBetween(mips3_KernGenException, mips3_UserGenException)) {
|
||||
else if (pcBetween(mips3_KernGenException, mips3_KernGenExceptionEnd)) {
|
||||
/* NOTE: the offsets depend on the code in locore.s */
|
||||
(*printfn)("------ kernel trap+%x: (%x, %x ,%x) -------\n",
|
||||
pc-(unsigned)mips3_KernGenException, a0, a1, a2);
|
||||
@ -1582,17 +1608,17 @@ specialframe:
|
||||
/* R4000 exception handlers */
|
||||
|
||||
#ifdef MIPS1 /* r2000 family (mips-I cpu) */
|
||||
if (pcBetween(mips1_KernGenException, mips1_UserGenException))
|
||||
if (pcBetween(mips1_KernGenException, mips1_KernGenExceptionEnd))
|
||||
subr = (unsigned) mips1_KernGenException;
|
||||
else if (pcBetween(mips1_UserGenException,mips1_SystemCall))
|
||||
else if (pcBetween(mips1_UserGenException, mips1_UserGenExceptionEnd))
|
||||
subr = (unsigned) mips1_UserGenException;
|
||||
else if (pcBetween(mips1_SystemCall,mips1_KernIntr))
|
||||
subr = (unsigned) mips1_UserGenException;
|
||||
else if (pcBetween(mips1_KernIntr, mips1_UserIntr))
|
||||
else if (pcBetween(mips1_SystemCall, mips1_SystemCallEnd))
|
||||
subr = (unsigned) mips1_SystemCall;
|
||||
else if (pcBetween(mips1_KernIntr, mips1_KernIntrEnd))
|
||||
subr = (unsigned) mips1_KernIntr;
|
||||
else if (pcBetween(mips1_UserIntr, mips1_TLBMissException))
|
||||
else if (pcBetween(mips1_UserIntr, mips1_UserIntrEnd))
|
||||
subr = (unsigned) mips1_UserIntr;
|
||||
else if (pcBetween(mips1_UTLBMiss, mips1_exceptionentry_end)) {
|
||||
else if (pcBetween(mips1_exceptionentry_start, mips1_exceptionentry_end)) {
|
||||
(*printfn)("<<mips1 locore>>");
|
||||
goto done;
|
||||
}
|
||||
@ -1602,25 +1628,26 @@ specialframe:
|
||||
|
||||
#ifdef MIPS3 /* r4000 family (mips-III cpu) */
|
||||
/* R4000 exception handlers */
|
||||
if (pcBetween(mips3_KernGenException, mips3_UserGenException))
|
||||
if (pcBetween(mips3_KernGenException, mips3_KernGenExceptionEnd))
|
||||
subr = (unsigned) mips3_KernGenException;
|
||||
else if (pcBetween(mips3_UserGenException,mips3_SystemCall))
|
||||
else if (pcBetween(mips3_UserGenException, mips3_UserGenExceptionEnd))
|
||||
subr = (unsigned) mips3_UserGenException;
|
||||
else if (pcBetween(mips3_SystemCall,mips3_KernIntr))
|
||||
else if (pcBetween(mips3_SystemCall, mips3_SystemCallEnd))
|
||||
subr = (unsigned) mips3_SystemCall;
|
||||
else if (pcBetween(mips3_KernIntr, mips3_UserIntr))
|
||||
else if (pcBetween(mips3_KernIntr, mips3_KernIntrEnd))
|
||||
subr = (unsigned) mips3_KernIntr;
|
||||
|
||||
else if (pcBetween(mips3_UserIntr, mips3_TLBInvalidException))
|
||||
else if (pcBetween(mips3_UserIntr, mips3_UserIntrEnd))
|
||||
subr = (unsigned) mips3_UserIntr;
|
||||
else if (pcBetween(mips3_TLBMiss, mips3_exceptionentry_end)) {
|
||||
else if (pcBetween(mips3_exceptionentry_start, mips3_exceptionentry_end)) {
|
||||
(*printfn)("<<mips3 locore>>");
|
||||
goto done;
|
||||
} else
|
||||
#endif /* MIPS3 */
|
||||
|
||||
|
||||
if (pcBetween(cpu_switch, savectx))
|
||||
if (pcBetween(splx, splx_end))
|
||||
subr = (unsigned) splx;
|
||||
else if (pcBetween(cpu_switch, cpu_switch_end))
|
||||
subr = (unsigned) cpu_switch;
|
||||
else if (pcBetween(idle, cpu_switch)) {
|
||||
subr = (unsigned) idle;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore_machdep.S,v 1.7 1998/08/25 01:55:40 nisimura Exp $ */
|
||||
/* $NetBSD: locore_machdep.S,v 1.8 1998/09/11 16:46:34 jonathan Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -430,6 +430,8 @@ ALEAF(_splx)
|
||||
nop # 3 ins to disable
|
||||
j ra
|
||||
nop
|
||||
.globl _C_LABEL(splx_end)
|
||||
_C_LABEL(splx_end):
|
||||
END(splx)
|
||||
/*
|
||||
* Interrupt counters for vmstat.
|
||||
|
||||
@ -1,7 +1,8 @@
|
||||
# $NetBSD: Makefile.inc,v 1.10 1998/08/20 17:56:22 tls Exp $
|
||||
# $NetBSD: Makefile.inc,v 1.11 1998/09/11 16:46:34 jonathan Exp $
|
||||
#
|
||||
# There are likely more that we will notice when we go native
|
||||
|
||||
SRCS+= random.c scanc.c skpc.c strcat.c strcpy.c strncmp.c strncpy.c \
|
||||
bswap16.c bswap32.c bswap64.c memchr.c memcmp.c memset.c \
|
||||
strncasecmp.c __assert.c
|
||||
SRCS+= memcpy.S
|
||||
|
||||
8
sys/lib/libkern/arch/mips/memcpy.S
Normal file
8
sys/lib/libkern/arch/mips/memcpy.S
Normal file
@ -0,0 +1,8 @@
|
||||
/* $NetBSD: memcpy.S,v 1.1 1998/09/11 16:46:34 jonathan Exp $ */
|
||||
|
||||
#include <mips/asm.h>
|
||||
#include <machine/endian.h>
|
||||
|
||||
.data
|
||||
.globl __no_memcpy
|
||||
__no_memcpy: .word 0
|
||||
Loading…
Reference in New Issue
Block a user