2001-02-05 22:22:23 +03:00
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/* $NetBSD: openpicreg.h,v 1.2 2001/02/05 19:22:23 briggs Exp $ */
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2001-02-02 09:11:52 +03:00
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/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* GLOBAL/TIMER register (IDU base + 0x1000)
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*/
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/* feature reporting reg 0 */
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#define OPENPIC_FEATURE 0x1000
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/* global config reg 0 */
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#define OPENPIC_CONFIG 0x1020
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#define OPENPIC_CONFIG_RESET 0x80000000
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#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000
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/* vendor ID */
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#define OPENPIC_VENDOR_ID 0x1080
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/* processor initialization reg */
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#define OPENPIC_PROC_INIT 0x1090
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/* IPI vector/priority reg */
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#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10)
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/* spurious intr. vector */
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#define OPENPIC_SPURIOUS_VECTOR 0x10e0
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/*
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* INTERRUPT SOURCE register (IDU base + 0x10000)
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*/
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/* interrupt vector/priority reg */
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#ifndef OPENPIC_SRC_VECTOR
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#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20)
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#endif
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#define OPENPIC_SENSE_LEVEL 0x00400000
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#define OPENPIC_SENSE_EDGE 0x00000000
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#define OPENPIC_POLARITY_POSITIVE 0x00800000
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#define OPENPIC_POLARITY_NEGATIVE 0x00000000
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#define OPENPIC_IMASK 0x80000000
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#define OPENPIC_ACTIVITY 0x40000000
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#define OPENPIC_PRIORITY_MASK 0x000f0000
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#define OPENPIC_PRIORITY_SHIFT 16
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#define OPENPIC_VECTOR_MASK 0x000000ff
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/* interrupt destination cpu */
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#ifndef OPENPIC_IDEST
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#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20)
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#endif
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/*
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* PROCESSOR register (IDU base + 0x20000)
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*/
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/* IPI command reg */
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#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi))
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/* current task priority reg */
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#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000)
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#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f
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/* interrupt acknowledge reg */
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#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000)
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/* end of interrupt reg */
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#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000)
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