2003-12-19 06:33:52 +03:00
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/* $NetBSD: satalink.c,v 1.4 2003/12/19 03:33:52 thorpej Exp $ */
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2003-12-15 03:36:23 +03:00
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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2003-12-14 02:13:40 +03:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_sii3112_reg.h>
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2003-12-15 03:36:23 +03:00
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#include <dev/ata/satareg.h>
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2003-12-14 02:13:40 +03:00
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2003-12-19 06:33:52 +03:00
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/*
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* Register map for BA5 register space, indexed by channel.
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*/
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static const struct {
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bus_addr_t ba5_IDEDMA_CMD;
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bus_addr_t ba5_IDEDMA_CTL;
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bus_addr_t ba5_IDEDMA_TBL;
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bus_addr_t ba5_IDEDMA_CMD2;
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bus_addr_t ba5_IDEDMA_CTL2;
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bus_addr_t ba5_IDE_TF0;
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bus_addr_t ba5_IDE_TF1;
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bus_addr_t ba5_IDE_TF2;
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bus_addr_t ba5_IDE_TF3;
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bus_addr_t ba5_IDE_TF4;
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bus_addr_t ba5_IDE_TF5;
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bus_addr_t ba5_IDE_TF6;
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bus_addr_t ba5_IDE_TF7;
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bus_addr_t ba5_IDE_TF8;
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bus_addr_t ba5_IDE_RAD;
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bus_addr_t ba5_IDE_TF9;
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bus_addr_t ba5_IDE_TF10;
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bus_addr_t ba5_IDE_TF11;
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bus_addr_t ba5_IDE_TF12;
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bus_addr_t ba5_IDE_TF13;
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bus_addr_t ba5_IDE_TF14;
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bus_addr_t ba5_IDE_TF15;
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bus_addr_t ba5_IDE_TF16;
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bus_addr_t ba5_IDE_TF17;
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bus_addr_t ba5_IDE_TF18;
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bus_addr_t ba5_IDE_TF19;
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bus_addr_t ba5_IDE_RABC;
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bus_addr_t ba5_IDE_CMD_STS;
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bus_addr_t ba5_IDE_CFG_STS;
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bus_addr_t ba5_IDE_DTM;
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bus_addr_t ba5_SControl;
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bus_addr_t ba5_SStatus;
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bus_addr_t ba5_SError;
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} satalink_ba5_regmap[] = {
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{
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.ba5_IDEDMA_CMD = 0x000,
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.ba5_IDEDMA_CTL = 0x002,
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.ba5_IDEDMA_TBL = 0x004,
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.ba5_IDEDMA_CMD2 = 0x010,
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.ba5_IDEDMA_CTL2 = 0x012,
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.ba5_IDE_TF0 = 0x080, /* wd_data */
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.ba5_IDE_TF1 = 0x081, /* wd_error */
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.ba5_IDE_TF2 = 0x082, /* wd_seccnt */
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.ba5_IDE_TF3 = 0x083, /* wd_sector */
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.ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */
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.ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */
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.ba5_IDE_TF6 = 0x086, /* wd_sdh */
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.ba5_IDE_TF7 = 0x087, /* wd_command */
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.ba5_IDE_TF8 = 0x08a, /* wd_altsts */
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.ba5_IDE_RAD = 0x08c,
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.ba5_IDE_TF9 = 0x091, /* Features 2 */
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.ba5_IDE_TF10 = 0x092, /* Sector Count 2 */
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.ba5_IDE_TF11 = 0x093, /* Start Sector 2 */
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.ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */
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.ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */
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.ba5_IDE_TF14 = 0x096, /* Device/Head 2 */
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.ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */
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.ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */
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.ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */
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.ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */
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.ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */
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.ba5_IDE_RABC = 0x09c,
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.ba5_IDE_CMD_STS = 0x0a0,
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.ba5_IDE_CFG_STS = 0x0a1,
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.ba5_IDE_DTM = 0x0b4,
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.ba5_SControl = 0x100,
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.ba5_SStatus = 0x104,
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.ba5_SError = 0x108,
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},
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{
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.ba5_IDEDMA_CMD = 0x008,
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.ba5_IDEDMA_CTL = 0x00a,
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.ba5_IDEDMA_TBL = 0x00c,
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.ba5_IDEDMA_CMD2 = 0x018,
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.ba5_IDEDMA_CTL2 = 0x01a,
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.ba5_IDE_TF0 = 0x0c0, /* wd_data */
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.ba5_IDE_TF1 = 0x0c1, /* wd_error */
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.ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */
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.ba5_IDE_TF3 = 0x0c3, /* wd_sector */
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.ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */
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.ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */
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.ba5_IDE_TF6 = 0x0c6, /* wd_sdh */
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.ba5_IDE_TF7 = 0x0c7, /* wd_command */
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.ba5_IDE_TF8 = 0x0ca, /* wd_altsts */
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.ba5_IDE_RAD = 0x0cc,
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.ba5_IDE_TF9 = 0x0d1, /* Features 2 */
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.ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */
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.ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */
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.ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */
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.ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */
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.ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */
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.ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */
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.ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */
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.ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */
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.ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */
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.ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */
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.ba5_IDE_RABC = 0x0dc,
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.ba5_IDE_CMD_STS = 0x0e0,
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.ba5_IDE_CFG_STS = 0x0e1,
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.ba5_IDE_DTM = 0x0f4,
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.ba5_SControl = 0x180,
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.ba5_SStatus = 0x184,
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.ba5_SError = 0x188,
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}
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};
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2003-12-14 02:13:40 +03:00
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static int satalink_match(struct device *, struct cfdata *, void *);
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static void satalink_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(satalink, sizeof(struct pciide_softc),
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satalink_match, satalink_attach, NULL, NULL);
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static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*);
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2003-12-15 03:36:23 +03:00
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static int sii3112_drv_probe(struct channel_softc*);
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2003-12-14 02:13:40 +03:00
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static void sii3112_setup_channel(struct channel_softc*);
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static const struct pciide_product_desc pciide_satalink_products[] = {
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{ PCI_PRODUCT_CMDTECH_3112,
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0,
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"Silicon Image SATALink 3112",
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sii3112_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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satalink_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) {
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if (pciide_lookup_product(pa->pa_id, pciide_satalink_products))
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return (2);
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}
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return (0);
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}
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static void
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satalink_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_satalink_products));
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}
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2003-12-15 03:36:23 +03:00
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static __inline uint32_t
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ba5_read_4(struct pciide_softc *sc, bus_addr_t reg)
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{
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if (__predict_true(sc->sc_ba5_en != 0))
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return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg));
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
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return (pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA));
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}
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2003-12-19 06:33:52 +03:00
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#define BA5_READ_4(sc, chan, reg) \
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ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)
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2003-12-15 03:36:23 +03:00
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static __inline void
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ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)
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{
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if (__predict_true(sc->sc_ba5_en != 0))
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val);
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else {
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR,
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reg);
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pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA,
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val);
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}
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}
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2003-12-19 06:33:52 +03:00
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#define BA5_WRITE_4(sc, chan, reg, val) \
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ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
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2003-12-14 02:13:40 +03:00
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static void
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sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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bus_size_t cmdsize, ctlsize;
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2003-12-15 03:36:23 +03:00
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pcireg_t interface, scs_cmd, cfgctl;
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2003-12-14 02:13:40 +03:00
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int channel;
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if (pciide_chipen(sc, pa) == 0)
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return;
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2003-12-15 03:36:23 +03:00
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scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
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pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
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scs_cmd & SCS_CMD_BA5_EN);
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if (scs_cmd & SCS_CMD_BA5_EN) {
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aprint_verbose("%s: SATALink BA5 register space enabled\n",
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sc->sc_wdcdev.sc_dev.dv_xname);
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if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
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PCI_MAPREG_TYPE_MEM|
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PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&sc->sc_ba5_st, &sc->sc_ba5_sh,
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NULL, NULL) != 0)
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aprint_error("%s: unable to map SATALink BA5 "
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"register space\n", sc->sc_wdcdev.sc_dev.dv_xname);
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else
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sc->sc_ba5_en = 1;
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} else {
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aprint_verbose("%s: SATALink BA5 register space disabled\n",
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sc->sc_wdcdev.sc_dev.dv_xname);
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/* Enable indirect BA5 addressing. */
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cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
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SII3112_PCI_CFGCTL);
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pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL,
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cfgctl | CFGCTL_BA5INDEN);
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}
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2003-12-14 02:13:40 +03:00
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_normal("\n");
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/*
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* Rev. <= 0x01 of the 3112 have a bug that can cause data
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* corruption if DMA transfers cross an 8K boundary. This is
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* apparently hard to tickle, but we'll go ahead and play it
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* safe.
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*/
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if (PCI_REVISION(pa->pa_class) <= 0x01) {
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sc->sc_dma_maxsegsz = 8192;
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sc->sc_dma_boundary = 8192;
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}
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
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WDC_CAPABILITY_MODE;
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sc->sc_wdcdev.PIO_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.DMA_cap = 2;
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sc->sc_wdcdev.UDMA_cap = 6;
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}
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|
|
sc->sc_wdcdev.set_modes = sii3112_setup_channel;
|
|
|
|
|
2003-12-15 03:36:23 +03:00
|
|
|
/* We can use SControl and SStatus to probe for drives. */
|
|
|
|
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE;
|
|
|
|
sc->sc_wdcdev.drv_probe = sii3112_drv_probe;
|
|
|
|
|
2003-12-14 02:13:40 +03:00
|
|
|
sc->sc_wdcdev.channels = sc->wdc_chanarray;
|
|
|
|
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
|
|
|
|
|
|
|
|
/*
|
2003-12-15 03:36:23 +03:00
|
|
|
* The 3112 either identifies itself as a RAID storage device
|
|
|
|
* or a Misc storage device. Fake up the interface bits for
|
|
|
|
* what our driver expects.
|
2003-12-14 02:13:40 +03:00
|
|
|
*/
|
|
|
|
if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
|
|
|
|
interface = PCI_INTERFACE(pa->pa_class);
|
|
|
|
} else {
|
|
|
|
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
|
|
|
|
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
|
|
|
|
cp = &sc->pciide_channels[channel];
|
|
|
|
if (pciide_chansetup(sc, channel, interface) == 0)
|
|
|
|
continue;
|
|
|
|
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
|
|
|
|
pciide_pci_intr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-12-15 03:36:23 +03:00
|
|
|
static const char *sata_speed[] = {
|
|
|
|
"no negotiated speed",
|
|
|
|
"1.5Gb/s",
|
|
|
|
"<unknown 2>",
|
|
|
|
"<unknown 3>",
|
|
|
|
"<unknown 4>",
|
|
|
|
"<unknown 5>",
|
|
|
|
"<unknown 6>",
|
|
|
|
"<unknown 7>",
|
|
|
|
"<unknown 8>",
|
|
|
|
"<unknown 9>",
|
|
|
|
"<unknown 10>",
|
|
|
|
"<unknown 11>",
|
|
|
|
"<unknown 12>",
|
|
|
|
"<unknown 13>",
|
|
|
|
"<unknown 14>",
|
|
|
|
"<unknown 15>",
|
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
|
|
|
sii3112_drv_probe(struct channel_softc *chp)
|
|
|
|
{
|
|
|
|
struct pciide_channel *cp = (struct pciide_channel *)chp;
|
|
|
|
struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
|
|
|
|
uint32_t scontrol, sstatus;
|
|
|
|
int rv = 0;
|
|
|
|
uint8_t scnt, sn, cl, ch;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The 3112 is a 2-port part, and only has one drive per channel
|
|
|
|
* (each port emulates a master drive).
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Request communication initialization sequence, any speed.
|
|
|
|
* Performing this is the equivalent of an ATA Reset.
|
|
|
|
*/
|
|
|
|
scontrol = SControl_DET_INIT | SControl_SPD_ANY;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX We don't yet support SATA power management; disable all
|
|
|
|
* power management state transitions.
|
|
|
|
*/
|
|
|
|
scontrol |= SControl_IPM_NONE;
|
|
|
|
|
2003-12-19 06:33:52 +03:00
|
|
|
BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
|
2003-12-15 03:36:23 +03:00
|
|
|
delay(500);
|
|
|
|
scontrol &= ~SControl_DET_INIT;
|
2003-12-19 06:33:52 +03:00
|
|
|
BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol);
|
2003-12-15 03:36:23 +03:00
|
|
|
delay(500);
|
|
|
|
|
2003-12-19 06:33:52 +03:00
|
|
|
sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus);
|
2003-12-15 03:36:23 +03:00
|
|
|
switch (sstatus & SStatus_DET_mask) {
|
|
|
|
case SStatus_DET_NODEV:
|
|
|
|
/* No device; be silent. */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SStatus_DET_DEV_NE:
|
|
|
|
aprint_error("%s: port %d: device connected, but "
|
|
|
|
"communication not established\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SStatus_DET_OFFLINE:
|
|
|
|
aprint_error("%s: port %d: PHY offline\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SStatus_DET_DEV:
|
|
|
|
/*
|
|
|
|
* XXX ATAPI detection doesn't currently work. Don't
|
|
|
|
* XXX know why. But, it's not like the standard method
|
|
|
|
* XXX can detect an ATAPI device connected via a SATA/PATA
|
|
|
|
* XXX bridge, so at least this is no worse. --thorpej
|
|
|
|
*/
|
|
|
|
bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0,
|
|
|
|
WDSD_IBM | (0 << 4));
|
|
|
|
delay(10); /* 400ns delay */
|
|
|
|
/* Save register contents. */
|
|
|
|
scnt = bus_space_read_1(chp->cmd_iot,
|
|
|
|
chp->cmd_iohs[wd_seccnt], 0);
|
|
|
|
sn = bus_space_read_1(chp->cmd_iot,
|
|
|
|
chp->cmd_iohs[wd_sector], 0);
|
|
|
|
cl = bus_space_read_1(chp->cmd_iot,
|
|
|
|
chp->cmd_iohs[wd_cyl_lo], 0);
|
|
|
|
ch = bus_space_read_1(chp->cmd_iot,
|
|
|
|
chp->cmd_iohs[wd_cyl_hi], 0);
|
|
|
|
#if 0
|
|
|
|
printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
|
|
|
|
scnt, sn, cl, ch);
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* scnt and sn are supposed to be 0x1 for ATAPI, but in some
|
|
|
|
* cases we get wrong values here, so ignore it.
|
|
|
|
*/
|
|
|
|
if (cl == 0x14 && ch == 0xeb)
|
|
|
|
chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
|
|
|
|
else
|
|
|
|
chp->ch_drive[0].drive_flags |= DRIVE_ATA;
|
|
|
|
|
|
|
|
aprint_normal("%s: port %d: device present, speed: %s\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
|
|
|
|
sata_speed[(sstatus & SStatus_SPD_mask) >>
|
|
|
|
SStatus_SPD_shift]);
|
|
|
|
rv |= (1 << 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
aprint_error("%s: port %d: unknown SStatus: 0x%08x\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
2003-12-14 02:13:40 +03:00
|
|
|
static void
|
|
|
|
sii3112_setup_channel(struct channel_softc *chp)
|
|
|
|
{
|
|
|
|
struct ata_drive_datas *drvp;
|
|
|
|
int drive;
|
|
|
|
u_int32_t idedma_ctl, dtm;
|
|
|
|
struct pciide_channel *cp = (struct pciide_channel*)chp;
|
|
|
|
struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc;
|
|
|
|
|
|
|
|
/* setup DMA if needed */
|
|
|
|
pciide_channel_dma_setup(cp);
|
|
|
|
|
|
|
|
idedma_ctl = 0;
|
|
|
|
dtm = 0;
|
|
|
|
|
|
|
|
for (drive = 0; drive < 2; drive++) {
|
|
|
|
drvp = &chp->ch_drive[drive];
|
|
|
|
/* If no drive, skip */
|
|
|
|
if ((drvp->drive_flags & DRIVE) == 0)
|
|
|
|
continue;
|
|
|
|
if (drvp->drive_flags & DRIVE_UDMA) {
|
|
|
|
/* use Ultra/DMA */
|
|
|
|
drvp->drive_flags &= ~DRIVE_DMA;
|
|
|
|
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
|
|
|
|
dtm |= DTM_IDEx_DMA;
|
|
|
|
} else if (drvp->drive_flags & DRIVE_DMA) {
|
|
|
|
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
|
|
|
|
dtm |= DTM_IDEx_DMA;
|
|
|
|
} else {
|
|
|
|
dtm |= DTM_IDEx_PIO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Nothing to do to setup modes; it is meaningless in S-ATA
|
|
|
|
* (but many S-ATA drives still want to get the SET_FEATURE
|
|
|
|
* command).
|
|
|
|
*/
|
|
|
|
if (idedma_ctl != 0) {
|
|
|
|
/* Add software bits in status register */
|
|
|
|
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
|
|
|
|
idedma_ctl);
|
|
|
|
}
|
|
|
|
pci_conf_write(sc->sc_pc, sc->sc_tag,
|
|
|
|
chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm);
|
|
|
|
}
|