112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
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/* $NetBSD: fpu.h,v 1.1 2006/04/07 14:21:18 cherry Exp $ */
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/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_FPU_H_
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#define _MACHINE_FPU_H_
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/*
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* Floating point status register bits.
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*/
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#define IA64_FPSR_TRAP_VD 0x0000000000000001L
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#define IA64_FPSR_TRAP_DD 0x0000000000000002L
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#define IA64_FPSR_TRAP_ZD 0x0000000000000004L
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#define IA64_FPSR_TRAP_OD 0x0000000000000008L
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#define IA64_FPSR_TRAP_UD 0x0000000000000010L
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#define IA64_FPSR_TRAP_ID 0x0000000000000020L
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#define IA64_FPSR_SF(i,v) ((v) << ((i)*13+6))
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#define IA64_SF_FTZ 0x0001L
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#define IA64_SF_WRE 0x0002L
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#define IA64_SF_PC 0x000cL
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#define IA64_SF_PC_0 0x0000L
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#define IA64_SF_PC_1 0x0004L
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#define IA64_SF_PC_2 0x0008L
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#define IA64_SF_PC_3 0x000cL
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#define IA64_SF_RC 0x0030L
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#define IA64_SF_RC_NEAREST 0x0000L
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#define IA64_SF_RC_NEGINF 0x0010L
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#define IA64_SF_RC_POSINF 0x0020L
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#define IA64_SF_RC_TRUNC 0x0030L
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#define IA64_SF_TD 0x0040L
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#define IA64_SF_V 0x0080L
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#define IA64_SF_D 0x0100L
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#define IA64_SF_Z 0x0200L
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#define IA64_SF_O 0x0400L
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#define IA64_SF_U 0x0800L
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#define IA64_SF_I 0x1000L
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#define IA64_SF_DEFAULT (IA64_SF_PC_3 | IA64_SF_RC_NEAREST)
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#define IA64_FPSR_DEFAULT (IA64_FPSR_TRAP_VD \
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| IA64_FPSR_TRAP_DD \
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| IA64_FPSR_TRAP_ZD \
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| IA64_FPSR_TRAP_OD \
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| IA64_FPSR_TRAP_UD \
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| IA64_FPSR_TRAP_ID \
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| IA64_FPSR_SF(0, IA64_SF_DEFAULT) \
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| IA64_FPSR_SF(1, (IA64_SF_DEFAULT \
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| IA64_SF_TD \
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| IA64_SF_WRE)) \
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| IA64_FPSR_SF(2, (IA64_SF_DEFAULT \
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| IA64_SF_TD)) \
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| IA64_FPSR_SF(3, (IA64_SF_DEFAULT \
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| IA64_SF_TD)))
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struct fpswa_ret {
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unsigned long status;
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unsigned long err1;
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unsigned long err2;
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unsigned long err3;
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};
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struct fpswa_bundle {
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long double bits; /* Force 16-byte alignment. */
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};
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struct fpswa_fpctx {
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unsigned long mask_low; /* f63 - f2 */
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unsigned long mask_high; /* f127 - f64 */
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union _ia64_fpreg *fp_low_preserved; /* f2 - f5 */
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union _ia64_fpreg *fp_low_volatile; /* f6 - f15 */
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union _ia64_fpreg *fp_high_preserved; /* f16 - f31 */
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union _ia64_fpreg *fp_high_volatile; /* f32 - f127 */
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};
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struct fpswa_iface {
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unsigned int if_rev;
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unsigned int __res;
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struct fpswa_ret (*if_fpswa)(unsigned long, struct fpswa_bundle *,
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unsigned long *, unsigned long *, unsigned long *, unsigned long *,
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unsigned long *, struct fpswa_fpctx *);
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};
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#endif /* ! _MACHINE_FPU_H_ */
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