285 lines
7.1 KiB
C
285 lines
7.1 KiB
C
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: $Hdr: screg_1185.h,v 4.300 91/06/09 06:22:14 root Rel41 $ SONY
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*
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* @(#)screg_1185.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Copyright (c) 1989- by SONY Corporation.
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*/
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/*
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* screg_1185.h ver 0.0
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* for SCSI I/F Chip CXD1185Q
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*/
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/*
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* SCSI I/F Chip CXD1185Q Register address assignment
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*/
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#ifdef mips
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# define SCSI_BASE 0xbfe00100
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#else
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# define SCSI_BASE 0xe1900000
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#endif
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#ifndef U_CHAR
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#ifdef mips
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#define U_CHAR volatile u_char
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#else
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#define U_CHAR u_char
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#endif
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#endif
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#define sc_statr *( (U_CHAR *)(SCSI_BASE + 0x0) )
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#define sc_comr *( (U_CHAR *)(SCSI_BASE + 0x0) )
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#define sc_datr *( (U_CHAR *)(SCSI_BASE + 0x1) )
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#define sc_intrq1 *( (U_CHAR *)(SCSI_BASE + 0x2) )
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#define sc_intrq2 *( (U_CHAR *)(SCSI_BASE + 0x3) )
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#define sc_envir *( (U_CHAR *)(SCSI_BASE + 0x3) )
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#define sc_cmonr *( (U_CHAR *)(SCSI_BASE + 0x4) )
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#define sc_timer *( (U_CHAR *)(SCSI_BASE + 0x4) )
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#define sc_ffstr *( (U_CHAR *)(SCSI_BASE + 0x5) )
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#define sc_idenr *( (U_CHAR *)(SCSI_BASE + 0x6) )
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#define sc_tclow *( (U_CHAR *)(SCSI_BASE + 0x7) )
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#define sc_tcmid *( (U_CHAR *)(SCSI_BASE + 0x8) )
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#define sc_tchi *( (U_CHAR *)(SCSI_BASE + 0x9) )
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#define sc_intok1 *( (U_CHAR *)(SCSI_BASE + 0xa) )
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#define sc_intok2 *( (U_CHAR *)(SCSI_BASE + 0xb) )
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#define sc_moder *( (U_CHAR *)(SCSI_BASE + 0xc) )
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#define sc_syncr *( (U_CHAR *)(SCSI_BASE + 0xd) )
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#define sc_busconr *( (U_CHAR *)(SCSI_BASE + 0xe) )
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#define sc_ioptr *( (U_CHAR *)(SCSI_BASE + 0xf) )
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/*
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* CXD1185Q Register bit assignment
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*/
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/* sc_statr (status register) bit define
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*/
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#define R0_MRST 0x80
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#define R0_MDBP 0x40
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#define R0_INIT 0x10
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#define R0_TARG 8
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#define R0_TRBZ 4
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#define R0_MIRQ 2
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#define R0_CIP 1
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/* sc_comr (command register) bit define
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*/
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#define R0_DMA 0x20
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#define R0_TRBE 0x10
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/* sc_intrq1 (interrupt request register 1) bit define
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*/
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#define R2_STO 0x10
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#define R2_RSL 8
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#define R2_SWA 4
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#define R2_SWOA 2
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#define R2_ARBF 1
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/* sc_intrq2 (interrupt request register 2) bit define
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*/
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#define R3_FNC 0x80
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#define R3_DCNT 0x40
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#define R3_SRST 0x20
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#define R3_PHC 0x10
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#define R3_DATN 8
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#define R3_DPE 4
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#define R3_SPE 2
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#define R3_RMSG 1
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/* sc_envir (environment register) bit define
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*/
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#define R3_DIFE 0x80
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#define R3_SDPM 0x40
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#define R3_DPEN 0x20
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#define R3_SIRM 0x10
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#define R3_FS_MASK 3
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/* sc_cmonr (scsi control monitor register) bit define
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*/
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#define R4_MBSY 0x80
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#define R4_MSEL 0x40
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#define R4_MMSG 0x20
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#define R4_MCD 0x10
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#define R4_MIO 8
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#define R4_MREQ 4
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#define R4_MACK 2
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#define R4_MATN 1
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/* sc_ffstr (FIFO status register) bit define
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*/
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#define R5_FIE 0x80
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#define R5_FIF 0x10
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#define R5_FIFOREM 0x1f
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/* sc_idenr (scsi identify register) bit define
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*/
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#define R6_OID_MASK 0x07
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#define R6_SID_MASK 0xe0
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#define R6_TID_MASK 0xe0
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/* sc_intok1 (interrupt enable register 1) bit define
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*/
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#define Ra_STO 0x10
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#define Ra_RSL 8
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#define Ra_SWA 4
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#define Ra_SWOA 2
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#define Ra_ARBF 1
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/* sc_intok2 (interrupt enable register 2) bit define
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*/
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#define Rb_FNC 0x80
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#define Rb_DCNT 0x40
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#define Rb_SRST 0x20
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#define Rb_PHC 0x10
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#define Rb_DATN 8
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#define Rb_DPE 4
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#define Rb_SPE 2
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#define Rb_RMSG 1
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/* sc_moder (mode register) bit define
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*/
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#define Rc_HDPE 0x80
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#define Rc_HSPE 0x40
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#define Rc_HATN 0x20
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#define Rc_TMSL 0x10
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#define Rc_SPHI 8
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#define Rc_BDMA 1
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/* sc_syncr (synchronous transfer control register) bit define
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*/
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#define Rd_TPD_MASK 0xf0
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#define Rd_TOF_MASK 0x0f
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#define MIN_TP 62 /* minimum transfer period 4ns * 25 */
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#define MAX_OFFSET 15
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/* sc_busconr (scsi bus control register) bit define
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*/
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#define Re_ABSY 0x80
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#define Re_ASEL 0x40
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#define Re_AMSG 0x20
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#define Re_ACD 0x10
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#define Re_AIO 8
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#define Re_AREQ 4
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#define Re_AACK 2
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#define Re_AATN 1
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/* sc_ioptr (I/O port) bit define
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*/
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#define Rf_PCN_MASK 0xf0
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# define Rf_PCN3 0x80
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# define Rf_PCN2 0x40
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# define Rf_PCN1 0x20
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# define Rf_PCN0 0x10
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#define Rf_PRT_MASK 0x0f
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# define Rf_PRT3 8
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# define Rf_PRT2 4
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# define Rf_PRT1 2
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# define Rf_PRT0 1
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/*
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* CXD1185Q commands
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*/
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/* category 0
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*/
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#define SCMD_NOP 0x00
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#define SCMD_CHIP_RST 0x01
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#define SCMD_AST_RST 0x02
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#define SCMD_FLSH_FIFO 0x03
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#define SCMD_AST_CTRL 0x04
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#define SCMD_NGT_CTRL 0x05
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#define SCMD_AST_DATA 0x06
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#define SCMD_NGT_DATA 0x07
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/* category 1
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*/
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#define SCMD_RESEL 0x40
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#define SCMD_SEL 0x41
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#define SCMD_SEL_ATN 0x42
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#define SCMD_ENB_SEL 0x43
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#define SCMD_DIS_SEL 0x44
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/* category 2
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*/
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#define SCMD_SEND_MES 0x80
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#define SCMD_SEND_STAT 0x81
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#define SCMD_SEND_DATA 0x82
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#define SCMD_DISCONNECT 0x83
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#define SCMD_RCV_MOUT 0x84
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#define SCMD_RCV_CMD 0x85
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#define SCMD_RCV_DATA 0x86
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/* category 3
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*/
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#define SCMD_TR_INFO 0xc0
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#define SCMD_TR_PAD 0xc1
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#define SCMD_NGT_ACK 0xc2
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#define SCMD_AST_ATN 0xc3
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#define SCMD_NGT_ATN 0xc4
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/*
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* scsi parameter definition
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*/
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/* SCSI bus ID
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*/
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#define SC_OWNID 0x7
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#define SC_TG_SHIFT 5
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/* scsi bus phase
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*/
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#define SC_PMASK (R4_MMSG|R4_MCD|R4_MIO)
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# define DAT_OUT 0
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# define DAT_IN R4_MIO
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# define COM_OUT R4_MCD
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# define STAT_IN (R4_MCD|R4_MIO)
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# define MES_OUT (R4_MMSG|R4_MCD)
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# define MES_IN (R4_MMSG|R4_MCD|R4_MIO)
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/* scsi command types define
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*/
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#define CMD_TYPEMASK 0xe0
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# define CMD_T0 0 /* 6 byte commands */
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# define CMD_T1 0x20 /* 10 byte commands */
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# define CMD_T5 0xa0 /* 12 byte commands */
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# define CMD_T6 0xc0
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# define CMD_T7 0xe0
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#define MAXNSCSI 1
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