465 lines
13 KiB
C
465 lines
13 KiB
C
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/* $NetBSD: igsfb_subr.c,v 1.1 2002/09/24 18:17:25 uwe Exp $ */
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/*
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* Copyright (c) 2002 Valeriy E. Ushakov
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Integraphics Systems IGA 168x and CyberPro series.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: igsfb_subr.c,v 1.1 2002/09/24 18:17:25 uwe Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <dev/wscons/wsconsio.h>
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#include <dev/ic/igsfbreg.h>
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#include <dev/ic/igsfbvar.h>
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static void igsfb_init_seq(struct igsfb_softc *);
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static void igsfb_init_crtc(struct igsfb_softc *);
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static void igsfb_init_grfx(struct igsfb_softc *);
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static void igsfb_init_attr(struct igsfb_softc *);
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static void igsfb_init_ext(struct igsfb_softc *);
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static void igsfb_init_dac(struct igsfb_softc *);
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static void igsfb_freq_latch(struct igsfb_softc *);
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static void igsfb_video_on(struct igsfb_softc *);
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/*
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* Enable chip.
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*/
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int
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igsfb_enable(iot)
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bus_space_tag_t iot;
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{
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bus_space_handle_t vdoh;
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bus_space_handle_t vseh;
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bus_space_handle_t regh;
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int ret;
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ret = bus_space_map(iot, IGS_VDO, 1, 0, &vdoh);
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if (ret != 0) {
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printf("unable to map VDO register\n");
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goto out0;
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}
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ret = bus_space_map(iot, IGS_VSE, 1, 0, &vseh);
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if (ret != 0) {
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printf("unable to map VSE register\n");
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goto out1;
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}
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ret = bus_space_map(iot, IGS_REG_BASE, IGS_REG_SIZE, 0, ®h);
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if (ret != 0) {
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printf("unable to map I/O registers\n");
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goto out2;
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}
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/*
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* Start decoding i/o space accesses.
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*/
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bus_space_write_1(iot, vdoh, 0, IGS_VDO_ENABLE | IGS_VDO_SETUP);
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bus_space_write_1(iot, vseh, 0, IGS_VSE_ENABLE);
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bus_space_write_1(iot, vdoh, 0, IGS_VDO_ENABLE);
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/*
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* Start decoding memory space accesses (XXX: move out of here?
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* we program this register in igsfb_init_ext).
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* While here, enable coprocessor and select IGS_COP_BASE_B.
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*/
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igs_ext_write(iot, regh, IGS_EXT_BIU_MISC_CTL,
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(IGS_EXT_BIU_LINEAREN
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| IGS_EXT_BIU_COPREN | IGS_EXT_BIU_COPASELB));
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bus_space_unmap(iot, regh, IGS_REG_SIZE);
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out2: bus_space_unmap(iot, vseh, 1);
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out1: bus_space_unmap(iot, vdoh, 1);
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out0: return (ret);
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}
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/*
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* Init sequencer.
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* This is common for all video modes.
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*/
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static void
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igsfb_init_seq(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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/* start messing with sequencer */
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igs_seq_write(iot, ioh, IGS_SEQ_RESET, 0);
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igs_seq_write(iot, ioh, 1, 0x01); /* 8 dot clock */
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igs_seq_write(iot, ioh, 2, 0x0f); /* enable all maps */
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igs_seq_write(iot, ioh, 3, 0x00); /* character generator */
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igs_seq_write(iot, ioh, 4, 0x0e); /* memory mode */
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/* this selects color mode among other things */
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bus_space_write_1(iot, ioh, IGS_MISC_OUTPUT_W, 0xef);
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/* normal sequencer operation */
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igs_seq_write(iot, ioh, IGS_SEQ_RESET,
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IGS_SEQ_RESET_SYNC | IGS_SEQ_RESET_ASYNC);
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}
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/*
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* Init CRTC to 640x480 8bpp at 60Hz
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*/
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static void
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igsfb_init_crtc(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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igs_crtc_write(iot, ioh, 0x00, 0x5f);
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igs_crtc_write(iot, ioh, 0x01, 0x4f);
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igs_crtc_write(iot, ioh, 0x02, 0x50);
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igs_crtc_write(iot, ioh, 0x03, 0x80);
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igs_crtc_write(iot, ioh, 0x04, 0x52);
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igs_crtc_write(iot, ioh, 0x05, 0x9d);
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igs_crtc_write(iot, ioh, 0x06, 0x0b);
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igs_crtc_write(iot, ioh, 0x07, 0x3e);
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/* next block is almost constant, only bit 6 in reg 9 differs */
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igs_crtc_write(iot, ioh, 0x08, 0x00);
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igs_crtc_write(iot, ioh, 0x09, 0x40); /* <- either 0x40 or 0x60 */
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igs_crtc_write(iot, ioh, 0x0a, 0x00);
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igs_crtc_write(iot, ioh, 0x0b, 0x00);
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igs_crtc_write(iot, ioh, 0x0c, 0x00);
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igs_crtc_write(iot, ioh, 0x0d, 0x00);
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igs_crtc_write(iot, ioh, 0x0e, 0x00);
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igs_crtc_write(iot, ioh, 0x0f, 0x00);
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igs_crtc_write(iot, ioh, 0x10, 0xe9);
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igs_crtc_write(iot, ioh, 0x11, 0x8b);
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igs_crtc_write(iot, ioh, 0x12, 0xdf);
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igs_crtc_write(iot, ioh, 0x13, 0x50);
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igs_crtc_write(iot, ioh, 0x14, 0x00);
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igs_crtc_write(iot, ioh, 0x15, 0xe6);
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igs_crtc_write(iot, ioh, 0x16, 0x04);
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igs_crtc_write(iot, ioh, 0x17, 0xc3);
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igs_crtc_write(iot, ioh, 0x18, 0xff);
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}
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/*
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* Init graphics controller.
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* This is common for all video modes.
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*/
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static void
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igsfb_init_grfx(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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igs_grfx_write(iot, ioh, 0, 0x00);
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igs_grfx_write(iot, ioh, 1, 0x00);
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igs_grfx_write(iot, ioh, 2, 0x00);
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igs_grfx_write(iot, ioh, 3, 0x00);
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igs_grfx_write(iot, ioh, 4, 0x00);
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igs_grfx_write(iot, ioh, 5, 0x60); /* SRMODE, MODE256 */
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igs_grfx_write(iot, ioh, 6, 0x05); /* 64k @ a0000, GRAPHICS */
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igs_grfx_write(iot, ioh, 7, 0x0f); /* color compare all */
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igs_grfx_write(iot, ioh, 8, 0xff); /* bitmask = all bits mutable */
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}
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/*
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* Init attribute controller.
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* This is common for all video modes.
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*/
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static void
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igsfb_init_attr(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int i;
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igs_attr_flip_flop(iot, ioh); /* reset attr flip-flop to address */
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for (i = 0; i < 16; ++i) /* crt palette */
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igs_attr_write(iot, ioh, i, i);
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igs_attr_write(iot, ioh, 0x10, 0x01); /* select graphic mode */
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igs_attr_write(iot, ioh, 0x11, 0x00); /* crt overscan color */
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igs_attr_write(iot, ioh, 0x12, 0x0f); /* color plane enable */
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igs_attr_write(iot, ioh, 0x13, 0x00);
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igs_attr_write(iot, ioh, 0x14, 0x00);
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}
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/*
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* When done with ATTR controller, call this to unblank the screen.
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*/
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static void
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igsfb_video_on(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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igs_attr_flip_flop(iot, ioh);
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bus_space_write_1(iot, ioh, IGS_ATTR_IDX, 0x20);
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bus_space_write_1(iot, ioh, IGS_ATTR_IDX, 0x20);
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}
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/*
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* Latch VCLK (b0/b1) and MCLK (b2/b3) values.
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*/
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static void
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igsfb_freq_latch(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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bus_space_write_1(iot, ioh, IGS_EXT_IDX, 0xb9);
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bus_space_write_1(iot, ioh, IGS_EXT_PORT, 0x80);
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bus_space_write_1(iot, ioh, IGS_EXT_PORT, 0x00);
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}
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static void
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igsfb_init_ext(sc)
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struct igsfb_softc *sc;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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igs_ext_write(iot, ioh, 0x10, 0x10); /* IGS_EXT_START_ADDR enable */
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igs_ext_write(iot, ioh, 0x12, 0x00); /* IGS_EXT_IRQ_CTL disable */
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igs_ext_write(iot, ioh, 0x13, 0x00); /* MBZ for normal operation */
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igs_ext_write(iot, ioh, 0x31, 0x00); /* segment write ptr */
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igs_ext_write(iot, ioh, 0x32, 0x00); /* segment read ptr */
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/* IGS_EXT_BIU_MISC_CTL: linear, segon */
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igs_ext_write(iot, ioh, 0x33, 0x11);
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/* sprite location */
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igs_ext_write(iot, ioh, 0x50, 0x00);
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igs_ext_write(iot, ioh, 0x51, 0x00);
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igs_ext_write(iot, ioh, 0x52, 0x00);
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igs_ext_write(iot, ioh, 0x53, 0x00);
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igs_ext_write(iot, ioh, 0x54, 0x00);
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igs_ext_write(iot, ioh, 0x55, 0x00);
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igs_ext_write(iot, ioh, 0x56, 0x00); /* sprite control */
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/* IGS_EXT_GRFX_MODE */
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igs_ext_write(iot, ioh, 0x57, 0x01); /* raster fb */
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/* overscan R/G/B */
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igs_ext_write(iot, ioh, 0x58, 0x00);
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igs_ext_write(iot, ioh, 0x59, 0x00);
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igs_ext_write(iot, ioh, 0x5A, 0x00);
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/*
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* Video memory size &c. We rely on firmware to program
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* BUS_CTL(30), MEM_CTL1(71), MEM_CTL2(72) appropriately.
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*/
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/* ext memory ctl0 */
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igs_ext_write(iot, ioh, 0x70, 0x0B); /* enable fifo, seq */
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/* ext hidden ctl1 */
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igs_ext_write(iot, ioh, 0x73, 0x30); /* XXX: krups: 0x20 */
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/* ext fifo control */
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igs_ext_write(iot, ioh, 0x74, 0x10); /* XXX: krups: 0x1b */
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igs_ext_write(iot, ioh, 0x75, 0x10); /* XXX: krups: 0x1e */
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igs_ext_write(iot, ioh, 0x76, 0x00); /* ext seq. */
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igs_ext_write(iot, ioh, 0x7A, 0xC8); /* ext. hidden ctl */
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/* ext graphics ctl: GCEXTPATH. krups 1, nettrom 1, docs 3 */
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igs_ext_write(iot, ioh, 0x90, 0x01);
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if (sc->sc_is2k) /* select normal vclk/mclk registers */
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igs_ext_write(iot, ioh, 0xBF, 0x00);
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igs_ext_write(iot, ioh, 0xB0, 0xD2); /* VCLK = 25.175MHz */
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igs_ext_write(iot, ioh, 0xB1, 0xD3);
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igs_ext_write(iot, ioh, 0xB2, 0xDB); /* MCLK = 75MHz*/
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igs_ext_write(iot, ioh, 0xB3, 0x54);
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igsfb_freq_latch(sc);
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if (sc->sc_is2k)
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igs_ext_write(iot, ioh, 0xF8, 0x04); /* XXX: ??? */
|
||
|
|
|
||
|
|
/* 640x480 8bpp at 60Hz */
|
||
|
|
igs_ext_write(iot, ioh, 0x11, 0x00);
|
||
|
|
igs_ext_write(iot, ioh, 0x77, 0x01); /* 8bpp, indexed */
|
||
|
|
igs_ext_write(iot, ioh, 0x14, 0x51);
|
||
|
|
igs_ext_write(iot, ioh, 0x15, 0x00);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static void
|
||
|
|
igsfb_init_dac(sc)
|
||
|
|
struct igsfb_softc *sc;
|
||
|
|
{
|
||
|
|
bus_space_tag_t iot = sc->sc_iot;
|
||
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
||
|
|
u_int8_t reg;
|
||
|
|
|
||
|
|
/* RAMDAC address 2 select */
|
||
|
|
reg = igs_ext_read(iot, ioh, IGS_EXT_SPRITE_CTL);
|
||
|
|
igs_ext_write(iot, ioh, IGS_EXT_SPRITE_CTL,
|
||
|
|
reg | IGS_EXT_SPRITE_DAC_PEL);
|
||
|
|
|
||
|
|
/* VREFEN, DAC8 */
|
||
|
|
bus_space_write_1(iot, ioh, IGS_DAC_CMD, 0x06);
|
||
|
|
|
||
|
|
/* restore */
|
||
|
|
igs_ext_write(iot, ioh, IGS_EXT_SPRITE_CTL, reg);
|
||
|
|
|
||
|
|
bus_space_write_1(iot, ioh, IGS_PEL_MASK, 0xff);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void
|
||
|
|
igsfb_1024x768_8bpp_60Hz(sc)
|
||
|
|
struct igsfb_softc *sc;
|
||
|
|
{
|
||
|
|
bus_space_tag_t iot = sc->sc_iot;
|
||
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
||
|
|
|
||
|
|
igs_crtc_write(iot, ioh, 0x11, 0x00); /* write enable CRTC 0..7 */
|
||
|
|
|
||
|
|
igs_crtc_write(iot, ioh, 0x00, 0xa3);
|
||
|
|
igs_crtc_write(iot, ioh, 0x01, 0x7f);
|
||
|
|
igs_crtc_write(iot, ioh, 0x02, 0x7f); /* krups: 80 */
|
||
|
|
igs_crtc_write(iot, ioh, 0x03, 0x85); /* krups: 84 */
|
||
|
|
igs_crtc_write(iot, ioh, 0x04, 0x84); /* krups: 88 */
|
||
|
|
igs_crtc_write(iot, ioh, 0x05, 0x95); /* krups: 99 */
|
||
|
|
igs_crtc_write(iot, ioh, 0x06, 0x24);
|
||
|
|
igs_crtc_write(iot, ioh, 0x07, 0xfd);
|
||
|
|
|
||
|
|
/* next block is almost constant, only bit 6 in reg 9 differs */
|
||
|
|
igs_crtc_write(iot, ioh, 0x08, 0x00);
|
||
|
|
igs_crtc_write(iot, ioh, 0x09, 0x60); /* <- either 0x40 or 0x60 */
|
||
|
|
igs_crtc_write(iot, ioh, 0x0a, 0x00);
|
||
|
|
igs_crtc_write(iot, ioh, 0x0b, 0x00);
|
||
|
|
igs_crtc_write(iot, ioh, 0x0c, 0x00);
|
||
|
|
igs_crtc_write(iot, ioh, 0x0d, 0x00);
|
||
|
|
igs_crtc_write(iot, ioh, 0x0e, 0x00);
|
||
|
|
igs_crtc_write(iot, ioh, 0x0f, 0x00);
|
||
|
|
|
||
|
|
igs_crtc_write(iot, ioh, 0x10, 0x06);
|
||
|
|
igs_crtc_write(iot, ioh, 0x11, 0x8c);
|
||
|
|
igs_crtc_write(iot, ioh, 0x12, 0xff);
|
||
|
|
igs_crtc_write(iot, ioh, 0x13, 0x80); /* depends on BPP */
|
||
|
|
igs_crtc_write(iot, ioh, 0x14, 0x0f);
|
||
|
|
igs_crtc_write(iot, ioh, 0x15, 0x02);
|
||
|
|
igs_crtc_write(iot, ioh, 0x16, 0x21);
|
||
|
|
igs_crtc_write(iot, ioh, 0x17, 0xe3);
|
||
|
|
igs_crtc_write(iot, ioh, 0x18, 0xff);
|
||
|
|
|
||
|
|
igs_ext_write(iot, ioh, 0xB0, 0xE2); /* VCLK */
|
||
|
|
igs_ext_write(iot, ioh, 0xB1, 0x58);
|
||
|
|
#if 1
|
||
|
|
/* XXX: hmm, krups does this */
|
||
|
|
igs_ext_write(iot, ioh, 0xB2, 0xE2); /* MCLK */
|
||
|
|
igs_ext_write(iot, ioh, 0xB3, 0x58);
|
||
|
|
#endif
|
||
|
|
igsfb_freq_latch(sc);
|
||
|
|
|
||
|
|
igs_ext_write(iot, ioh, 0x11, 0x00);
|
||
|
|
igs_ext_write(iot, ioh, 0x77, 0x01); /* 8bpp, indexed */
|
||
|
|
igs_ext_write(iot, ioh, 0x14, 0x81);
|
||
|
|
igs_ext_write(iot, ioh, 0x15, 0x00);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static void igsfb_xxx_snoop(struct igsfb_softc *); /* XXX: debugging */
|
||
|
|
|
||
|
|
static void
|
||
|
|
igsfb_xxx_snoop(sc)
|
||
|
|
struct igsfb_softc *sc;
|
||
|
|
{
|
||
|
|
bus_space_tag_t iot = sc->sc_iot;
|
||
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
||
|
|
u_int8_t reg;
|
||
|
|
|
||
|
|
/* Memory size */
|
||
|
|
reg = igs_ext_read(iot, ioh, IGS_EXT_BUS_CTL);
|
||
|
|
printf(">>> EXT.30 = 0x%02x\n", reg);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Memory type &c.
|
||
|
|
* netwinder = 0x63 -> serial DRAM 1Mx16 chips
|
||
|
|
* krups = 0x03 -> serial DRAM 256Kx?? chips
|
||
|
|
*/
|
||
|
|
reg = igs_ext_read(iot, ioh, IGS_EXT_MEM_CTL1);
|
||
|
|
printf(">>> EXT.71 = 0x%02x\n", reg);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* netwinder = 0x02 -> 4Mb, 32bit bus
|
||
|
|
* krups = 0x05 -> 2Mb, 64bit bus
|
||
|
|
*/
|
||
|
|
reg = igs_ext_read(iot, ioh, IGS_EXT_MEM_CTL2);
|
||
|
|
printf(">>> EXT.72 = 0x%02x\n", reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* igs-video-init from krups prom
|
||
|
|
*/
|
||
|
|
void
|
||
|
|
igsfb_hw_setup(sc)
|
||
|
|
struct igsfb_softc *sc;
|
||
|
|
{
|
||
|
|
igsfb_xxx_snoop(sc); /* misc debugging printfs */
|
||
|
|
|
||
|
|
igsfb_init_seq(sc);
|
||
|
|
igsfb_init_crtc(sc);
|
||
|
|
igsfb_init_attr(sc);
|
||
|
|
igsfb_init_grfx(sc);
|
||
|
|
igsfb_init_ext(sc);
|
||
|
|
igsfb_init_dac(sc);
|
||
|
|
|
||
|
|
igsfb_1024x768_8bpp_60Hz(sc);
|
||
|
|
igsfb_video_on(sc);
|
||
|
|
}
|