104 lines
4.1 KiB
C
104 lines
4.1 KiB
C
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/* $NetBSD: if_ne_pcireg.h,v 1.1 1998/10/27 22:30:56 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register description for NE2000-compatible PCI Ethernet interfaces.
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*/
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/*
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* Registers on RealTek 8029 NE2000-compatible network interfaces.
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*
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* Data sheets for this chip can be found at:
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*
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* http://www.realtek.com.tw
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*/
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/*
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* Page 3 register offsets.
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*/
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#define NEPCI_RTL3_EECR 0x01 /* EEPROM Command Register */
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#define RTL3_EECR_EEM1 0x80 /* EEPROM Operating Mode */
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#define RTL3_EECR_EEM0 0x40
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/* 0 0 Normal operation */
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/* 0 1 Auto-load */
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/* 1 0 9346 programming */
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/* 1 1 Config register write enab */
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#define RTL3_EECR_EECS 0x08 /* EEPROM Chip Select */
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#define RTL3_EECR_EESK 0x04 /* EEPROM Clock */
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#define RTL3_EECR_EEDI 0x02 /* EEPROM Data In */
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#define RTL3_EECR_EEDO 0x01 /* EEPROM Data Out */
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#define NEPCI_RTL3_CONFIG0 0x03 /* Configuration 0 (ro) */
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#define RTL3_CONFIG0_BNC 0x04 /* BNC is active */
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#define NEPCI_RTL3_CONFIG2 0x05 /* Configuration 2 */
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#define RTL3_CONFIG2_PL1 0x80 /* Network media type */
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#define RTL3_CONFIG2_PL0 0x40
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/* 0 0 TP/CX auto-detect */
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/* 0 1 10baseT */
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/* 1 0 10base5 */
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/* 1 1 10base2 */
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#define RTL3_CONFIG2_FCE 0x20 /* Flow Control Enable */
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#define RTL3_CONFIG2_PF 0x10 /* Pause Flag */
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#define RTL3_CONFIG2_BS1 0x02 /* Boot Rom Size */
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#define RTL3_CONFIG2_BS0 0x01
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/* 0 0 No Boot Rom */
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/* 0 1 8k */
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/* 1 0 16k */
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/* 1 1 32k */
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#define NEPCI_RTL3_CONFIG3 0x06 /* Configuration 3 */
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#define RTL3_CONFIG3_FUDUP 0x40 /* Full Duplex */
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#define RTL3_CONFIG3_LEDS1 0x20 /* LED1/2 pin configuration */
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/* 0 LED1 == LED_RX, LED2 == LED_TX */
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/* 1 LED1 == LED_CRS, LED2 == MCSB */
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#define RTL3_CONFIG3_LEDS0 0x10 /* LED0 pin configration */
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/* 0 LED0 pin == LED_COL */
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/* 1 LED0 pin == LED_LINK */
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#define RTL3_CONFIG3_SLEEP 0x04 /* Sleep mode */
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#define RTL3_CONFIG3_PWRDN 0x02 /* Power Down */
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#define NEPCI_RTL3_HLTCLK 0x09 /* Halt Clock */
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#define RTL3_HLTCLK_RUNNING 'R' /* clock runs in power down */
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#define RTL3_HLTCLK_HALTED 'H' /* clock halted in power down */
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#define NEPCI_RTL3_ID0 0x0e /* ID register 0 */
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#define NEPCI_RTL3_ID1 0x0f /* ID register 1 */
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