2004-09-21 06:46:46 +04:00
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/* $NetBSD: wdc_isapnp.c,v 1.31 2004/09/21 02:46:46 thorpej Exp $ */
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1998-01-23 23:40:58 +03:00
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1998-08-15 14:10:47 +04:00
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/*-
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2003-09-20 01:35:56 +04:00
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* Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
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1998-08-15 14:10:47 +04:00
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* All rights reserved.
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1998-01-23 23:40:58 +03:00
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*
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1998-08-15 14:10:47 +04:00
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Onno van der Linden.
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1998-01-23 23:40:58 +03:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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1998-08-15 14:10:47 +04:00
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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1998-01-23 23:40:58 +03:00
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*
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1998-08-15 14:10:47 +04:00
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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1998-01-23 23:40:58 +03:00
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*/
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2001-11-13 10:56:39 +03:00
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#include <sys/cdefs.h>
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2004-09-21 06:46:46 +04:00
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__KERNEL_RCSID(0, "$NetBSD: wdc_isapnp.c,v 1.31 2004/09/21 02:46:46 thorpej Exp $");
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2001-11-13 10:56:39 +03:00
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1998-01-23 23:40:58 +03:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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1998-10-12 20:09:10 +04:00
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#include <sys/malloc.h>
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1998-01-23 23:40:58 +03:00
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmavar.h>
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#include <dev/isapnp/isapnpreg.h>
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#include <dev/isapnp/isapnpvar.h>
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1998-07-23 23:30:44 +04:00
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#include <dev/isapnp/isapnpdevs.h>
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1998-01-23 23:40:58 +03:00
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1998-10-12 20:09:10 +04:00
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#include <dev/ata/atavar.h>
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1998-01-23 23:40:58 +03:00
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#include <dev/ic/wdcreg.h>
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#include <dev/ic/wdcvar.h>
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struct wdc_isapnp_softc {
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struct wdc_softc sc_wdcdev;
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2004-08-14 19:08:04 +04:00
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struct ata_channel *wdc_chanlist[1];
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struct ata_channel ata_channel;
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2004-01-01 20:18:53 +03:00
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struct ata_queue wdc_chqueue;
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2004-08-14 19:08:04 +04:00
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struct wdc_regs wdc_regs;
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1998-06-09 04:05:19 +04:00
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isa_chipset_tag_t sc_ic;
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1998-01-23 23:40:58 +03:00
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void *sc_ih;
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int sc_drq;
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};
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2004-08-20 03:30:09 +04:00
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static int wdc_isapnp_probe(struct device *, struct cfdata *, void *);
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static void wdc_isapnp_attach(struct device *, struct device *, void *);
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1998-01-23 23:40:58 +03:00
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2002-10-01 01:31:52 +04:00
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CFATTACH_DECL(wdc_isapnp, sizeof(struct wdc_isapnp_softc),
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2002-10-02 20:33:28 +04:00
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wdc_isapnp_probe, wdc_isapnp_attach, NULL, NULL);
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1998-01-23 23:40:58 +03:00
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#ifdef notyet
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2004-08-20 03:30:09 +04:00
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static void wdc_isapnp_dma_setup(struct wdc_isapnp_softc *);
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static void wdc_isapnp_dma_start(void *, void *, size_t, int);
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static void wdc_isapnp_dma_finish(void *);
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1998-01-23 23:40:58 +03:00
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#endif
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2004-08-20 03:30:09 +04:00
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static int
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wdc_isapnp_probe(struct device *parent, struct cfdata *match, void *aux)
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1998-01-23 23:40:58 +03:00
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{
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1999-03-22 13:00:09 +03:00
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int pri, variant;
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1999-03-22 12:44:12 +03:00
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1999-03-22 13:00:09 +03:00
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pri = isapnp_devmatch(aux, &isapnp_wdc_devinfo, &variant);
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if (pri && variant > 0)
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pri = 0;
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return (pri);
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1998-01-23 23:40:58 +03:00
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}
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2004-08-20 03:30:09 +04:00
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static void
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wdc_isapnp_attach(struct device *parent, struct device *self, void *aux)
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1998-01-23 23:40:58 +03:00
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{
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struct wdc_isapnp_softc *sc = (void *)self;
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2004-08-14 19:08:04 +04:00
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struct wdc_regs *wdr;
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1998-01-23 23:40:58 +03:00
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struct isapnp_attach_args *ipa = aux;
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There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
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int i;
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1998-01-23 23:40:58 +03:00
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if (ipa->ipa_nio != 2 ||
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ipa->ipa_nmem != 0 ||
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ipa->ipa_nmem32 != 0 ||
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ipa->ipa_nirq != 1 ||
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ipa->ipa_ndrq > 1) {
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2003-03-22 23:05:20 +03:00
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printf(": unexpected configuration\n");
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1998-01-23 23:40:58 +03:00
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return;
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}
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if (isapnp_config(ipa->ipa_iot, ipa->ipa_memt, ipa)) {
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2003-03-22 23:05:20 +03:00
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printf(": couldn't map registers\n");
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1998-01-23 23:40:58 +03:00
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return;
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}
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2003-03-22 23:05:20 +03:00
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printf(": %s %s\n", ipa->ipa_devident, ipa->ipa_devclass);
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1998-01-23 23:40:58 +03:00
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2004-08-14 19:08:04 +04:00
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sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
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wdr->cmd_iot = ipa->ipa_iot;
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wdr->ctl_iot = ipa->ipa_iot;
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1998-09-13 01:40:22 +04:00
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/*
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* An IDE controller can feed us the regions in any order. Pass
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* them along with the 8-byte region in sc_ad.ioh, and the other
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* (2 byte) region in auxioh.
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*/
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if (ipa->ipa_io[0].length == 8) {
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2004-08-14 19:08:04 +04:00
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wdr->cmd_baseioh = ipa->ipa_io[0].h;
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wdr->ctl_ioh = ipa->ipa_io[1].h;
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1998-09-13 01:40:22 +04:00
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} else {
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2004-08-14 19:08:04 +04:00
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wdr->cmd_baseioh = ipa->ipa_io[1].h;
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wdr->ctl_ioh = ipa->ipa_io[0].h;
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1998-09-13 01:40:22 +04:00
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}
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There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
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for (i = 0; i < WDC_NREG; i++) {
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2004-08-14 19:08:04 +04:00
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if (bus_space_subregion(wdr->cmd_iot,
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wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
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&wdr->cmd_iohs[i]) != 0) {
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There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
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printf(": couldn't subregion registers\n");
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return;
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}
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}
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2004-08-14 19:08:04 +04:00
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wdr->data32iot = wdr->cmd_iot;
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wdr->data32ioh = wdr->cmd_iohs[0];
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1998-01-23 23:40:58 +03:00
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1998-10-12 20:09:10 +04:00
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sc->sc_ic = ipa->ipa_ic;
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1998-01-23 23:40:58 +03:00
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sc->sc_ih = isa_intr_establish(ipa->ipa_ic, ipa->ipa_irq[0].num,
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2004-08-14 19:08:04 +04:00
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ipa->ipa_irq[0].type, IPL_BIO, wdcintr, &sc->ata_channel);
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1998-01-23 23:40:58 +03:00
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#ifdef notyet
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if (ipa->ipa_ndrq > 0) {
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sc->sc_drq = ipa->ipa_drq[0].num;
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2004-08-20 10:39:37 +04:00
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.dma_start = &wdc_isapnp_dma_start;
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sc->sc_wdcdev.dma_finish = &wdc_isapnp_dma_finish;
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1998-10-12 20:09:10 +04:00
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wdc_isapnp_dma_setup(sc);
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1998-01-23 23:40:58 +03:00
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}
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#endif
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2004-08-20 10:39:37 +04:00
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
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2004-08-14 19:08:04 +04:00
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sc->wdc_chanlist[0] = &sc->ata_channel;
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2004-08-20 10:39:37 +04:00
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
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sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
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2004-08-14 19:08:04 +04:00
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sc->ata_channel.ch_channel = 0;
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2004-08-20 10:39:37 +04:00
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sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
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2004-08-14 19:08:04 +04:00
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sc->ata_channel.ch_queue = &sc->wdc_chqueue;
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2003-09-20 01:35:56 +04:00
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2004-09-21 06:46:46 +04:00
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wdc_init_shadow_regs(&sc->ata_channel);
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2004-08-14 19:08:04 +04:00
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wdcattach(&sc->ata_channel);
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1998-01-23 23:40:58 +03:00
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}
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#ifdef notyet
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static void
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2004-08-20 03:30:09 +04:00
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wdc_isapnp_dma_setup(struct wdc_isapnp_softc *sc)
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1998-01-23 23:40:58 +03:00
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{
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1998-06-09 04:05:19 +04:00
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if (isa_dmamap_create(sc->sc_ic, sc->sc_drq,
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1998-01-23 23:40:58 +03:00
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MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) {
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printf("%s: can't create map for drq %d\n",
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sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
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2004-08-20 10:39:37 +04:00
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sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
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1998-01-23 23:40:58 +03:00
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}
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}
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static void
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2004-08-20 03:30:09 +04:00
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wdc_isapnp_dma_start(void *scv, void *buf, size_t size, int read)
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1998-01-23 23:40:58 +03:00
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{
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struct wdc_isapnp_softc *sc = scv;
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1999-02-22 06:24:33 +03:00
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isa_dmastart(sc->sc_ic, sc->sc_drq, buf, size, NULL,
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(read ? DMAMODE_READ : DMAMODE_WRITE) | DMAMODE_DEMAND,
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1998-01-23 23:40:58 +03:00
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BUS_DMA_NOWAIT);
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}
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static void
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2004-08-20 03:30:09 +04:00
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wdc_isapnp_dma_finish(void *scv)
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1998-01-23 23:40:58 +03:00
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{
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struct wdc_isapnp_softc *sc = scv;
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1998-06-09 04:05:19 +04:00
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isa_dmadone(sc->sc_ic, sc->sc_drq);
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1998-01-23 23:40:58 +03:00
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}
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#endif
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