1996-04-27 00:05:28 +04:00
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/* $NetBSD: div.S,v 1.2 1996/04/26 20:05:28 mark Exp $ */
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/*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by NetBSD Project
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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1996-02-01 02:44:43 +03:00
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a1 .req r0
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a2 .req r1
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a3 .req r2
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a4 .req r3
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v1 .req r4
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v2 .req r5
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v3 .req r6
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v4 .req r7
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v5 .req r8
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v6 .req r9
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v7 .req r10
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fp .req r11
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ip .req r12
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sp .req r13
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lr .req r14
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pc .req r15
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.text
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.global __rt_sdiv
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__rt_sdiv:
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b x_divide
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.global __rt_udiv
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__rt_udiv:
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b x_udivide
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.global ___umodsi3
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___umodsi3:
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mov a3, a1
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mov a1, a2
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mov a2, a3
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b x_uremainder
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.global ___udivsi3
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___udivsi3:
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mov a3, a1
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mov a1, a2
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mov a2, a3
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b x_udivide
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.global ___modsi3
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___modsi3:
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mov a3, a1
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mov a1, a2
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mov a2, a3
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b x_remainder
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.global ___divsi3
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___divsi3:
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mov a3, a1
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mov a1, a2
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mov a2, a3
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b x_divide
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.global x_divtest
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x_divtest:
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mov pc,lr
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.global x_remainder
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x_remainder:
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stmfd sp!,{lr}
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bl x_divide
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mov a1,a2
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ldmfd sp!,{pc}
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.global x_uremainder
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x_uremainder:
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stmfd sp!,{lr}
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bl x_udivide
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mov a1,a2
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ldmfd sp!,{pc}
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x_overflow:
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mvn a1,#0
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mov pc,lr
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.global x_udivide /* a1 = a2 / a1; a2 = a2 % a1 */
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x_udivide:
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cmp a1,#1
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bcc x_overflow
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beq x_divide_l0
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mov ip,#0
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movs a2,a2
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bpl x_divide_l1
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orr ip,ip,#0x20000000 /* ip bit 0x20000000 = -ve a2 */
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movs a2,a2,lsr #1
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orrcs ip,ip,#0x10000000 /* ip bit 0x10000000 = bit 0 of a2 */
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b x_divide_l1
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x_divide_l0: /* a1 == 1 */
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mov a1,a2
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mov a2,#0
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mov pc,lr
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.global x_divide /* a1 = a2 / a1; a2 = a2 % a1 */
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x_divide:
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cmp a1,#1
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bcc x_overflow
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beq x_divide_l0
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ands ip,a1,#0x80000000
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rsbmi a1,a1,#0
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ands a3,a2,#0x80000000
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eor ip,ip,a3
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rsbmi a2,a2,#0
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orr ip,a3,ip,lsr #1 /* ip bit 0x40000000 = -ve division */
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/* ip bit 0x80000000 = -ve remainder */
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x_divide_l1:
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mov a3,#1
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mov a4,#0
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cmp a2,a1
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bcc x_divide_b0
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cmp a2,a1,lsl #1
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bcc x_divide_b1
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cmp a2,a1,lsl #2
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bcc x_divide_b2
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cmp a2,a1,lsl #3
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bcc x_divide_b3
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cmp a2,a1,lsl #4
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bcc x_divide_b4
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cmp a2,a1,lsl #5
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bcc x_divide_b5
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cmp a2,a1,lsl #6
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bcc x_divide_b6
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cmp a2,a1,lsl #7
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bcc x_divide_b7
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cmp a2,a1,lsl #8
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bcc x_divide_b8
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cmp a2,a1,lsl #9
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bcc x_divide_b9
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cmp a2,a1,lsl #10
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bcc x_divide_b10
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cmp a2,a1,lsl #11
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bcc x_divide_b11
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cmp a2,a1,lsl #12
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bcc x_divide_b12
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cmp a2,a1,lsl #13
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bcc x_divide_b13
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cmp a2,a1,lsl #14
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bcc x_divide_b14
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cmp a2,a1,lsl #15
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bcc x_divide_b15
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cmp a2,a1,lsl #16
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bcc x_divide_b16
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cmp a2,a1,lsl #17
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bcc x_divide_b17
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cmp a2,a1,lsl #18
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bcc x_divide_b18
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cmp a2,a1,lsl #19
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bcc x_divide_b19
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cmp a2,a1,lsl #20
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bcc x_divide_b20
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cmp a2,a1,lsl #21
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bcc x_divide_b21
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cmp a2,a1,lsl #22
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bcc x_divide_b22
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cmp a2,a1,lsl #23
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bcc x_divide_b23
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cmp a2,a1,lsl #24
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bcc x_divide_b24
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cmp a2,a1,lsl #25
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bcc x_divide_b25
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cmp a2,a1,lsl #26
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bcc x_divide_b26
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cmp a2,a1,lsl #27
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bcc x_divide_b27
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cmp a2,a1,lsl #28
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bcc x_divide_b28
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cmp a2,a1,lsl #29
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bcc x_divide_b29
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cmp a2,a1,lsl #30
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bcc x_divide_b30
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cmp a2,a1,lsl #31
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subhs a2,a2,a1,lsl #31
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addhs a4,a4,a3,lsl #31
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cmp a2,a1,lsl #30
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subhs a2,a2,a1,lsl #30
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addhs a4,a4,a3,lsl #30
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x_divide_b30:
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cmp a2,a1,lsl #29
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subhs a2,a2,a1,lsl #29
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addhs a4,a4,a3,lsl #29
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x_divide_b29:
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cmp a2,a1,lsl #28
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subhs a2,a2,a1,lsl #28
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addhs a4,a4,a3,lsl #28
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x_divide_b28:
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cmp a2,a1,lsl #27
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subhsS a2,a2,a1,lsl #27
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addhs a4,a4,a3,lsl #27
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x_divide_b27:
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cmp a2,a1,lsl #26
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subhs a2,a2,a1,lsl #26
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addhs a4,a4,a3,lsl #26
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x_divide_b26:
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cmp a2,a1,lsl #25
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subhs a2,a2,a1,lsl #25
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addhs a4,a4,a3,lsl #25
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x_divide_b25:
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cmp a2,a1,lsl #24
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subhs a2,a2,a1,lsl #24
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addhs a4,a4,a3,lsl #24
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x_divide_b24:
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cmp a2,a1,lsl #23
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subhs a2,a2,a1,lsl #23
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addhs a4,a4,a3,lsl #23
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x_divide_b23:
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cmp a2,a1,lsl #22
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subhs a2,a2,a1,lsl #22
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addhs a4,a4,a3,lsl #22
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x_divide_b22:
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cmp a2,a1,lsl #21
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subhs a2,a2,a1,lsl #21
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addhs a4,a4,a3,lsl #21
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x_divide_b21:
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cmp a2,a1,lsl #20
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subhs a2,a2,a1,lsl #20
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addhs a4,a4,a3,lsl #20
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x_divide_b20:
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cmp a2,a1,lsl #19
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subhs a2,a2,a1,lsl #19
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addhs a4,a4,a3,lsl #19
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x_divide_b19:
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cmp a2,a1,lsl #18
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subhs a2,a2,a1,lsl #18
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addhs a4,a4,a3,lsl #18
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x_divide_b18:
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cmp a2,a1,lsl #17
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subhs a2,a2,a1,lsl #17
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addhs a4,a4,a3,lsl #17
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x_divide_b17:
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cmp a2,a1,lsl #16
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subhs a2,a2,a1,lsl #16
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addhs a4,a4,a3,lsl #16
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x_divide_b16:
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cmp a2,a1,lsl #15
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subhs a2,a2,a1,lsl #15
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addhs a4,a4,a3,lsl #15
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x_divide_b15:
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cmp a2,a1,lsl #14
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subhs a2,a2,a1,lsl #14
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addhs a4,a4,a3,lsl #14
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x_divide_b14:
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cmp a2,a1,lsl #13
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subhs a2,a2,a1,lsl #13
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addhs a4,a4,a3,lsl #13
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x_divide_b13:
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cmp a2,a1,lsl #12
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subhs a2,a2,a1,lsl #12
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addhs a4,a4,a3,lsl #12
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x_divide_b12:
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cmp a2,a1,lsl #11
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subhs a2,a2,a1,lsl #11
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addhs a4,a4,a3,lsl #11
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x_divide_b11:
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cmp a2,a1,lsl #10
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subhs a2,a2,a1,lsl #10
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addhs a4,a4,a3,lsl #10
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x_divide_b10:
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cmp a2,a1,lsl #9
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subhs a2,a2,a1,lsl #9
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addhs a4,a4,a3,lsl #9
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x_divide_b9:
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cmp a2,a1,lsl #8
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subhs a2,a2,a1,lsl #8
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addhs a4,a4,a3,lsl #8
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x_divide_b8:
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cmp a2,a1,lsl #7
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subhs a2,a2,a1,lsl #7
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addhs a4,a4,a3,lsl #7
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x_divide_b7:
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cmp a2,a1,lsl #6
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subhs a2,a2,a1,lsl #6
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addhs a4,a4,a3,lsl #6
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x_divide_b6:
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cmp a2,a1,lsl #5
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subhs a2,a2,a1,lsl #5
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addhs a4,a4,a3,lsl #5
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x_divide_b5:
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cmp a2,a1,lsl #4
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subhs a2,a2,a1,lsl #4
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addhs a4,a4,a3,lsl #4
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x_divide_b4:
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cmp a2,a1,lsl #3
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subhs a2,a2,a1,lsl #3
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addhs a4,a4,a3,lsl #3
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x_divide_b3:
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cmp a2,a1,lsl #2
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subhs a2,a2,a1,lsl #2
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addhs a4,a4,a3,lsl #2
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x_divide_b2:
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cmp a2,a1,lsl #1
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subhs a2,a2,a1,lsl #1
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addhs a4,a4,a3,lsl #1
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x_divide_b1:
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cmp a2,a1
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subhs a2,a2,a1
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addhs a4,a4,a3
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x_divide_b0:
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tst ip,#0x20000000
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bne x_udivide_l1
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mov a1,a4
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cmp ip,#0
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rsbmi a2,a2,#0
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movs ip,ip,lsl #1
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rsbmi a1,a1,#0
|
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mov pc,lr
|
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x_udivide_l1:
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tst ip,#0x10000000
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mov a2,a2,lsl #1
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orrne a2,a2,#1
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mov a4,a4,lsl #1
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cmp a2,a1
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|
subhs a2,a2,a1
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|
addhs a4,a4,a3
|
|
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mov a1,a4
|
|
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|
mov pc,lr
|
|
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|
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|
