197 lines
8.3 KiB
C
197 lines
8.3 KiB
C
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/* $NetBSD: hdc9224.h,v 1.1 1996/07/20 18:55:12 ragge Exp $ */
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/*
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* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
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* All rights reserved.
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*
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* This code is derived from software contributed to Ludd by Bertram Barth.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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struct hdc9224_DKCreg {
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unsigned char dkc_reg; /* Disk Register Data Access Port (rw)*/
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unsigned char fill[3]; /* bytes are longword aligned */
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unsigned char dkc_cmd; /* Disk Controller Command Port (wo) */
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#define dkc_stat dkc_cmd /* Interrupt Status Port (ro) */
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};
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/*
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* definition of some commands (constant bits only, incomplete!)
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*/
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#define DKC_CMD_RESET 0x00 /* terminate non-data-transfer cmds */
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#define DKC_CMD_DRDESELECT 0x01 /* done when no drive is in use */
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#define DKC_CMD_SETREGPTR 0x40 /* logically or-ed with reg-number */
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#define DKC_CMD_DRSELECT 0x20
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#define DKC_CMD_DRSEL_HDD 0x24 /* select HDD, or-ed with unit-numb. */
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#define DKC_CMD_DRSEL_RX33 0x28 /* or-ed with unit-number of RX33 */
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#define DKC_CMD_DRSEL_RX50 0x2C /* or-ed with unit-number of RX50 */
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#define DKC_CMD_RESTORE 0x02
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#define DKC_CMD_STEP 0x04
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#define DKC_CMD_STEPIN_FDD 0x04 /* one step inward for floppy */
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#define DKC_CMD_STEPOUT_FDD 0x06 /* one step outward (toward cyl #0) */
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#define DKC_CMD_POLLDRIVE 0x10
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#define DKC_CMD_SEEKREADID 0x50
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#define DKC_CMD_FORMATTRACK 0x60
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#define DKC_CMD_READTRACK 0x5A
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#define DKC_CMD_READPHYSICAL 0x58
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#define DKC_CMD_READLOGICAL 0x5C
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#define DKC_CMD_READ_HDD 0x5D /* read-logical, bypass=0, xfer=1 */
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#define DKC_CMD_READ_RX33 0x5D /* ??? */
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#define DKC_CMD_WRITEPHYSICAL 0x80
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#define DKC_CMD_WRITELOGICAL 0xC0
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#define DKC_CMD_WRITE_HDD 0xA0 /* bypass=0, ddmark=0 */
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#define DKC_CMD_WRITE_RX33 0xA1 /* precompensation differs... */
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#define DKC_CMD_WRITE_RX50 0xA4
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/*
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* Definition of bits in the DKC_STAT register
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*/
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#define DKC_ST_INTPEND (1<<7) /* interrupt pending */
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#define DKC_ST_DMAREQ (1<<6) /* DMA request */
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#define DKC_ST_DONE (1<<5) /* command done */
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#define DKC_ST_TERMCOD (3<<3) /* termination code (see below) */
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#define DKC_ST_RDYCHNG (1<<2) /* ready change */
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#define DKC_ST_OVRUN (1<<1) /* overrun/underrun */
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#define DKC_ST_BADSECT (1<<0) /* bad sector */
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/*
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* Definition of the termination codes
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*/
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#define DKC_TC_SUCCESS (0<<3) /* Successful completion */
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#define DKC_TC_RDIDERR (1<<3) /* Error in READ-ID sequence */
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#define DKC_TC_VRFYERR (2<<3) /* Error in VERIFY sequence */
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#define DKC_TC_DATAERR (3<<3) /* Error in DATA-TRANSFER seq. */
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/*
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* Definitions of delays neccessary for floppy-operation
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*/
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#define DKC_DELAY_MOTOR 500 /* allow 500 ms to reach speed */
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#define DKC_DELAY_SELECT 70 /* 70 ms for data-recovery-circuit */
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#define DKC_DELAY_POSITION 59 /* 59 ms for RX33, 100 ms for RX50 */
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#define DKC_DELAY_HEADSET 18 /* 18 ms when changing head-number */
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/*
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* The HDC9224 has 11/15(?) internal registers which are accessible via
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* the Disk-Register-Data-Access-Port DKC_REG
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*/
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struct hdc9224_UDCreg { /* internal disk controller registers */
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u_char udc_dma7; /* 0: DMA adress bits 0 - 7 */
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u_char udc_dma15; /* 1: DMA adress bits 8 - 15 */
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u_char udc_dma23; /* 2: DMA adress bits 16 - 23 */
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u_char udc_dsect; /* 3: desired/starting sector number */
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#define udc_csect udc_dsect /* current sector number */
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u_char udc_dhead; /* 4: cyl-bits 8-10, desired head number */
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#define udc_chead udc_dhead /* current head number */
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u_char udc_dcyl; /* 5: desired cylinder number */
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#define udc_ccyl udc_dcyl /* current cylinder number */
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u_char udc_scnt; /* 6: sector count register */
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u_char udc_rtcnt; /* 7: retry count register */
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u_char udc_mode; /* 8: operation mode/chip status */
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#define udc_cstat udc_mode /* chip status register */
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u_char udc_term; /* 9: termination conditions/drive status */
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#define udc_dstat udc_term /* drive status register */
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u_char udc_data; /* 10: data */
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};
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/*
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* Definition of bits in the Current-Head register
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*/
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#define UDC_CH_BADSECT (1<<7) /* indicates a bad sector (if bypass=0) */
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#define UDC_CH_CYLBITS (0x70) /* bits 10-8 of current cylinder number */
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#define UDC_CH_HEADNO (0x0F) /* current head number */
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/*
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* Definition of bits in the Retry-Count register
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*/
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#define UDC_RC_RTRYCNT (0xF0) /* 1's compl. in read-log, 0 all others */
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#define UDC_RC_RXDISAB (1<<3) /* must/should be 0 for normal operation */
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#define UDC_RC_INVRDY (1<<2) /* polarity of floppy-status, important! */
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#define UDC_RC_MOTOR (1<<1) /* turn on floppy-motor, no effect on HDD */
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#define UDC_RC_LOSPEED (1<<0) /* floppy-speed select, RX33: 0, RX50: 1 */
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#define UDC_RC_HDD_READ 0xF2 /* 0x72 ??? */
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#define UDC_RC_HDD_WRT 0xF2 /* 0xF0 ??? */
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#define UDC_RC_RX33READ 0x76 /* enable retries when reading floppies */
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#define UDC_RC_RX33WRT 0xF6
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#define UDC_RC_RX50READ 0x77 /* enable retries when reading floppies */
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#define UDC_RC_RX50WRT 0xF7
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/*
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* Definition of bits in the Operating-Mode register
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*/
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#define UDC_MD_HDMODE (1<<7) /* must be 1 for all FDD and HDD */
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#define UDC_MD_CHKCOD (3<<5) /* error-check: FDD/CRC: 0, HDD/ECC: 1 */
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#define UDC_MD_DENS (1<<4) /* density select, must be 0 */
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#define UDC_MD_UNUSED (1<<3) /* bit 3 is not used and must be 0 */
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#define UDC_MD_SRATE (7<<0) /* seek step rate */
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#define UDC_MD_HDD 0xC0
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#define UDC_MD_RX33 0x82
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#define UDC_MD_RX50 0x81
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/*
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* Definition of bits in the Chip-Status register
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*/
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#define UDC_CS_RETREQ (1<<7) /* retry required */
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#define UDC_CS_ECCATT (1<<6) /* error correction attempted */
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#define UDC_CS_ECCERR (1<<5) /* ECC/CRC error */
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#define UDC_CS_DELDATA (1<<4) /* deleted data mark */
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#define UDC_CS_SYNCERR (1<<3) /* synchronization error */
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#define UDC_CS_COMPERR (1<<2) /* compare error */
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#define UDC_CS_PRESDRV (0x3) /* present drive selected */
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/*
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* Definition of bits in the Termination-Conditions register
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*/
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#define UDC_TC_CRCPRE (1<<7) /* CRC register preset, must be 1 */
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#define UDC_TC_UNUSED (1<<6) /* bit 6 is not used and must be 0 */
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#define UDC_TC_INTDONE (1<<5) /* interrupt on done */
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#define UDC_TC_TDELDAT (1<<4) /* terminate on deleted data */
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#define UDC_TC_TDSTAT3 (1<<3) /* terminate on drive status 3 change */
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#define UDC_TC_TWPROT (1<<2) /* terminate on write-protect (FDD only) */
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#define UDC_TC_INTRDCH (1<<1) /* interrupt on ready change (FDD only) */
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#define UDC_TC_TWRFLT (1<<0) /* interrupt on write-fault (HDD only) */
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#define UDC_TC_HDD 0xA5 /* 0xB5 ??? */
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#define UDC_TC_FDD 0xA0 /* 0xAA ??? 0xB4 ??? */
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/*
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* Definition of bits in the Disk-Status register
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*/
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#define UDC_DS_SELACK (1<<7) /* select acknowledge (harddisk only!) */
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#define UDC_DS_INDEX (1<<6) /* index point */
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#define UDC_DS_SKCOM (1<<5) /* seek complete */
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#define UDC_DS_TRK00 (1<<4) /* track 0 */
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#define UDC_DS_DSTAT3 (1<<3) /* drive status 3 (MBZ) */
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#define UDC_DS_WRPROT (1<<2) /* write protect (floppy only!) */
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#define UDC_DS_READY (1<<1) /* drive ready bit */
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#define UDC_DS_WRFAULT (1<<0) /* write fault */
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