111 lines
4.0 KiB
C
111 lines
4.0 KiB
C
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/* $NetBSD: plumicureg.h,v 1.1 1999/11/21 06:50:26 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* INTERRUPT CONTROLLER
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*/
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#define PLUM_INT_REGBASE 0x8000
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#define PLUM_INT_REGSIZE 0x1000
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/* interrupt status register */
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#define PLUM_INT_INTSTA_REG 0x000
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#define PLUM_INT_INTSTA_EXTINT 0x00000080
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#define PLUM_INT_INTSTA_SMINT 0x00000040
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#define PLUM_INT_INTSTA_USBWAKE 0x00000020
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#define PLUM_INT_INTSTA_USBINT 0x00000010
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#define PLUM_INT_INTSTA_DISPINT 0x00000008
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#define PLUM_INT_INTSTA_C2SCINT 0x00000004
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#define PLUM_INT_INTSTA_C1SCINT 0x00000002
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#define PLUM_INT_INTSTA_PCCINT 0x00000001
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/* interrupt enable register */
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#define PLUM_INT_INTIEN_REG 0x010
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#define PLUM_INT_INTIEN 0x00000001
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/* outside input interrupt status register */
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#define PLUM_INT_EXTINTS_REG 0x100
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#define PLUM_INT_EXTINTS_IO5INT0 0x00000020
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#define PLUM_INT_EXTINTS_IO5INT1 0x00000010
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#define PLUM_INT_EXTINTS_IO5INT2 0x00000008
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#define PLUM_INT_EXTINTS_IO5INT3 0x00000004
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#define PLUM_INT_EXTINTS_IO3INT0 0x00000002
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#define PLUM_INT_EXTINTS_IO3INT1 0x00000001
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#define PLUM_INT_EXTINTM_REG 0x104
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#define PLUM_INT_EXTIEN_REG 0x110
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#define PLUM_INT_EXTIEN_IENIO5INT0 0x00000020
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#define PLUM_INT_EXTIEN_IENIO5INT1 0x00000010
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#define PLUM_INT_EXTIEN_IENIO5INT2 0x00000008
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#define PLUM_INT_EXTIEN_IENIO5INT3 0x00000004
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#define PLUM_INT_EXTIEN_IENIO3INT0 0x00000002
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#define PLUM_INT_EXTIEN_IENIO3INT1 0x00000001
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#define PLUM_INT_EXTIEN_SENIO5INT0 0x00002000
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#define PLUM_INT_EXTIEN_SENIO5INT1 0x00001000
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#define PLUM_INT_EXTIEN_SENIO5INT2 0x00000800
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#define PLUM_INT_EXTIEN_SENIO5INT3 0x00000400
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#define PLUM_INT_EXTIEN_SENIO3INT0 0x00000200
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#define PLUM_INT_EXTIEN_SENIO3INT1 0x00000100
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/* PC-card interrupt status register */
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#define PLUM_INT_PCCINTS_REG 0x200
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#define PLUM_INT_PCCINTS_C2RI 0x00000008
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#define PLUM_INT_PCCINTS_C2IO 0x00000004
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#define PLUM_INT_PCCINTS_C1RI 0x00000002
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#define PLUM_INT_PCCINTS_C1IO 0x00000001
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/* PC-card interrupt status register (masked) */
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#define PLUM_INT_PCCINTM_REG 0x204
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/* PC-card interrupt enable register */
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#define PLUM_INT_PCCIEN_REG 0x210
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#define PLUM_INT_PCCIEN_IENC2RI 0x00000008
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#define PLUM_INT_PCCIEN_IENC2IO 0x00000004
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#define PLUM_INT_PCCIEN_IENC1RI 0x00000002
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#define PLUM_INT_PCCIEN_IENC1IO 0x00000001
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#define PLUM_INT_PCCIEN_SENC2RI 0x00000800
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#define PLUM_INT_PCCIEN_SENC2IO 0x00000400
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#define PLUM_INT_PCCIEN_SENC1RI 0x00000200
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#define PLUM_INT_PCCIEN_SENC1IO 0x00000100
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/* PC-card interrupt detection register */
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#define PLUM_INT_PCCLKSL_REG 0x220
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#define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/
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/* USB interrupt enable register */
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#define PLUM_INT_USBINTEN_REG 0x310
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#define PLUM_INT_USBINTEN_WIEN 0x00000002
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#define PLUM_INT_USBINTEN_IEN 0x00000001
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/* SmartMedia interrupt enable register */
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#define PLUM_INT_SMIEN_REG 0x410
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#define PLUM_INT_SMIEN 0x00000001
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