1997-11-07 16:31:15 +03:00
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/* $NetBSD: if_mcreg.h,v 1.2 1997/11/07 13:31:18 briggs Exp $ */
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1997-11-04 06:44:42 +03:00
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/*-
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* Copyright (c) 1997 David Huang <khym@bga.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* AMD MACE (Am79C940) register definitions
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*/
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#define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */
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#define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */
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#define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */
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#define MACE_XMTFS 3 /* Transmit Frame Status (read only) */
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#define MACE_XMTRC 4 /* Transmit Retry Count (read only) */
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#define MACE_RCVFC 5 /* Receive Frame Control (read/write) */
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#define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */
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#define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */
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#define MACE_IR 8 /* Interrupt Register (read only) */
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#define MACE_IMR 9 /* Interrupt Mask Register (read/write) */
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#define MACE_PR 10 /* Poll Register (read only) */
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#define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */
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#define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */
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#define MACE_MACCC 13 /* MAC Configuration Control (read/write) */
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#define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */
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#define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */
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#define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */
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#define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */
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#define MACE_IAC 18 /* Internal Address Configuration (read/write) */
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/* RESERVED 19 Reserved (read/write as 0) */
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#define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */
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#define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */
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/* RESERVED 22 Reserved (read/write as 0) */
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/* RESERVED 23 Reserved (read/write as 0) */
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#define MACE_MPC 24 /* Missed Packet Count (read only) */
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/* RESERVED 25 Reserved (read/write as 0) */
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#define MACE_RNTPC 26 /* Runt Packet Count (read only) */
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#define MACE_RCVCC 27 /* Receive Collision Count (read only) */
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/* RESERVED 28 Reserved (read/write as 0) */
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#define MACE_UTR 29 /* User Test Register (read/write) */
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#define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */
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#define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */
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#define MACE_NREGS 32
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/* 2: Transmit Frame Control (XMTFC) */
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#define DRTRY 0x80 /* Disable Retry */
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#define DXMTFCS 0x08 /* Disable Transmit FCS */
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#define APADXMT 0x01 /* Auto Pad Transmit */
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/* 3: Transmit Frame Status (XMTFS) */
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#define XMTSV 0x80 /* Transmit Status Valid */
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#define UFLO 0x40 /* Underflow */
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#define LCOL 0x20 /* Late Collision */
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#define MORE 0x10 /* More than one retry needed */
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#define ONE 0x08 /* Exactly one retry needed */
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#define DEFER 0x04 /* Transmission deferred */
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#define LCAR 0x02 /* Loss of Carrier */
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#define RTRY 0x01 /* Retry Error */
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/* 4: Transmit Retry Count (XMTRC) */
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#define EXDEF 0x80 /* Excessive Defer */
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#define XMTRC 0x0f /* Transmit Retry Count */
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/* 5: Receive Frame Control (RCVFC) */
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#define LLRCV 0x08 /* Low Latency Receive */
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#define MR 0x04 /* Match/Reject */
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#define ASTRPRCV 0x01 /* Auto Strip Receive */
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/* 6: Receive Frame Status (RCVFS) */
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/* 4 byte register; read 4 times to get all of the bytes */
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/* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */
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/* Read 2: RFS1 - Receive Status (RCVSTS) */
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#define OFLO 0x80 /* Overflow flag */
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#define CLSN 0x40 /* Collision flag */
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#define FRAM 0x20 /* Framing Error flag */
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#define FCS 0x10 /* FCS Error flag */
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#define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */
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/* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */
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/* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */
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/* 7: FIFO Frame Count (FIFOFC) */
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#define RCVFC 0xf0 /* Receive Frame Count */
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#define XMTFC 0x0f /* Transmit Frame Count */
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/* 8: Interrupt Register (IR) */
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#define JAB 0x80 /* Jabber Error */
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#define BABL 0x40 /* Babble Error */
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#define CERR 0x20 /* Collision Error */
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#define RCVCCO 0x10 /* Receive Collision Count Overflow */
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#define RNTPCO 0x08 /* Runt Packet Count Overflow */
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#define MPCO 0x04 /* Missed Packet Count Overflow */
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#define RCVINT 0x02 /* Receive Interrupt */
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#define XMTINT 0x01 /* Transmit Interrupt */
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/* 9: Interrut Mask Register (IMR) */
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#define JABM 0x80 /* Jabber Error Mask */
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#define BABLM 0x40 /* Babble Error Mask */
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#define CERRM 0x20 /* Collision Error Mask */
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#define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */
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#define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */
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#define MPCOM 0x04 /* Missed Packet Count Overflow Mask */
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#define RCVINTM 0x02 /* Receive Interrupt Mask */
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#define XMTINTM 0x01 /* Transmit Interrupt Mask */
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/* 10: Poll Register (PR) */
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#define XMTSV 0x80 /* Transmit Status Valid */
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#define TDTREQ 0x40 /* Transmit Data Transfer Request */
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#define RDTREQ 0x20 /* Receive Data Transfer Request */
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/* 11: BIU Configuration Control (BIUCC) */
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#define BSWP 0x40 /* Byte Swap */
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#define XMTSP 0x30 /* Transmit Start Point */
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#define XMTSP_4 0x00 /* 4 bytes */
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#define XMTSP_16 0x10 /* 16 bytes */
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#define XMTSP_64 0x20 /* 64 bytes */
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#define XMTSP_112 0x30 /* 112 bytes */
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#define SWRST 0x01 /* Software Reset */
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/* 12: FIFO Configuration Control (FIFOCC) */
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#define XMTFW 0xc0 /* Transmit FIFO Watermark */
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#define XMTFW_8 0x00 /* 8 write cycles */
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#define XMTFW_16 0x40 /* 16 write cycles */
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#define XMTFW_32 0x80 /* 32 write cycles */
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#define RCVFW 0x30 /* Receive FIFO Watermark */
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#define RCVFW_16 0x00 /* 16 bytes */
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#define RCVFW_32 0x10 /* 32 bytes */
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#define RCVFW_64 0x20 /* 64 bytes */
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#define XMTFWU 0x08 /* Transmit FIFO Watermark Update */
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#define RCVFWU 0x04 /* Receive FIFO Watermark Update */
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#define XMTBRST 0x02 /* Transmit Burst */
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#define RCVBRST 0x01 /* Receive Burst */
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/* 13: MAC Configuration (MACCC) */
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#define PROM 0x80 /* Promiscuous */
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#define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */
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#define EMBA 0x20 /* Enable Modified Back-off Algorithm */
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#define DRCVPA 0x08 /* Disable Receive Physical Address */
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#define DRCVBC 0x04 /* Disable Receive Broadcast */
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#define ENXMT 0x02 /* Enable Transmit */
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#define ENRCV 0x01 /* Enable Receive */
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/* 14: PLS Configuration Control (PLSCC) */
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#define XMTSEL 0x08 /* Transmit Mode Select */
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#define PORTSEL 0x06 /* Port Select */
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#define PORTSEL_AUI 0x00 /* Select AUI */
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#define PORTSEL_10BT 0x02 /* Select 10BASE-T */
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#define PORTSEL_DAI 0x04 /* Select DAI port */
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#define PORTSEL_GPSI 0x06 /* Select GPSI */
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#define ENPLSIO 0x01 /* Enable PLS I/O */
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/* 15: PHY Configuration (PHYCC) */
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#define LNKFL 0x80 /* Link Fail */
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#define DLNKTST 0x40 /* Disable Link Test */
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#define REVPOL 0x20 /* Reversed Polarity */
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#define DAPC 0x10 /* Disable Auto Polarity Correction */
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#define LRT 0x08 /* Low Receive Threshold */
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#define ASEL 0x04 /* Auto Select */
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#define RWAKE 0x02 /* Remote Wake */
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#define AWAKE 0x01 /* Auto Wake */
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/* 18: Internal Address Configuration (IAC) */
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#define ADDRCHG 0x80 /* Address Change */
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#define PHYADDR 0x04 /* Physical Address Reset */
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#define LOGADDR 0x02 /* Logical Address Reset */
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/* 28: User Test Register (UTR) */
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#define RTRE 0x80 /* Reserved Test Register Enable */
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#define RTRD 0x40 /* Reserved Test Register Disable */
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#define RPA 0x20 /* Run Packet Accept */
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#define FCOLL 0x10 /* Force Collision */
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#define RCVFCSE 0x08 /* Receive FCS Enable */
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#define LOOP 0x06 /* Loopback Control */
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#define LOOP_NONE 0x00 /* No Loopback */
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#define LOOP_EXT 0x02 /* External Loopback */
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#define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */
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#define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */
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