Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
NetBSD/sys/dev/ic/upcvar.h

77 lines
2.7 KiB
C
Raw Normal View History

Add support for the 82C710, the original Universal Peripheral Controller. It turns out (now that I've found the data sheet) to have a substantially different configuration mechanism from its successors.
2003-03-02 03:21:47 +03:00
/* $NetBSD: upcvar.h,v 1.2 2003/03/02 00:21:47 bjh21 Exp $ */
Basic driver for CHIPS 82C710 Universal Peripheral Controller and friends, as used on later arm26 system (A5000, A4, A3010, A3020, A4000). What we have got: ... upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00 fdc at upc0 offset 0x3f4 not configured wdc0 at upc0 offset 0x1f0 lpt0 at upc0 offset 0x278 com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo ... What we haven't got: - FDC support (found, but not configured). - Clearing lpt interrupts on arm26 systems (needs help from IOEB). - A upc(4) manual page. - More than minimal testing (my A3020s don't have root devices). - A proper probe routine (arm26 can't use one anyway).
2000-08-17 03:56:08 +04:00
/*-
Add support for the 82C710, the original Universal Peripheral Controller. It turns out (now that I've found the data sheet) to have a substantially different configuration mechanism from its successors.
2003-03-02 03:21:47 +03:00
* Copyright (c) 2000, 2003 Ben Harris
Basic driver for CHIPS 82C710 Universal Peripheral Controller and friends, as used on later arm26 system (A5000, A4, A3010, A3020, A4000). What we have got: ... upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00 fdc at upc0 offset 0x3f4 not configured wdc0 at upc0 offset 0x1f0 lpt0 at upc0 offset 0x278 com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo ... What we haven't got: - FDC support (found, but not configured). - Clearing lpt interrupts on arm26 systems (needs help from IOEB). - A upc(4) manual page. - More than minimal testing (my A3020s don't have root devices). - A proper probe routine (arm26 can't use one anyway).
2000-08-17 03:56:08 +04:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __UPCVAR_H
#define __UPCVAR_H
#include <machine/bus.h>
struct upc_irqhandle {
int (*uih_func)(void *);
void *uih_arg;
int uih_level;
};
struct upc_softc {
struct device sc_dev;
/* These fields are filled in by the bus attachment. */
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
/*
* These fields are filled in by upc_attach(). The bus attachment
* for upc is expected to establish them according to the way the
* chip is wired.
*/
struct upc_irqhandle sc_irq3;
struct upc_irqhandle sc_irq4;
struct upc_irqhandle sc_pintr;
struct upc_irqhandle sc_fintr;
struct upc_irqhandle sc_wintr;
};
extern void upc_attach(struct upc_softc *);
Add support for the 82C710, the original Universal Peripheral Controller. It turns out (now that I've found the data sheet) to have a substantially different configuration mechanism from its successors.
2003-03-02 03:21:47 +03:00
extern int upc1_read_config(struct upc_softc *, int);
extern void upc1_write_config(struct upc_softc *, int, int);
extern int upc2_read_config(struct upc_softc *, int);
extern void upc2_write_config(struct upc_softc *, int, int);
Basic driver for CHIPS 82C710 Universal Peripheral Controller and friends, as used on later arm26 system (A5000, A4, A3010, A3020, A4000). What we have got: ... upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00 fdc at upc0 offset 0x3f4 not configured wdc0 at upc0 offset 0x1f0 lpt0 at upc0 offset 0x278 com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo ... What we haven't got: - FDC support (found, but not configured). - Clearing lpt interrupts on arm26 systems (needs help from IOEB). - A upc(4) manual page. - More than minimal testing (my A3020s don't have root devices). - A proper probe routine (arm26 can't use one anyway).
2000-08-17 03:56:08 +04:00
/* This is the structure passed to children of upc. */
struct upc_attach_args {
char const *ua_devtype;
int ua_offset;
bus_space_tag_t ua_iot;
bus_space_handle_t ua_ioh;
bus_space_handle_t ua_ioh2; /* for wdc */
struct upc_irqhandle *ua_irqhandle;
};
extern void upc_intr_establish(struct upc_irqhandle *, int, int (*)(void *),
void *arg);
#endif